diff --git a/lib/FIFO/sim/tb_fifo_async.fdo b/lib/FIFO/sim/tb_fifo_async.fdo
index c164ab6..ad9ac50 100644
--- a/lib/FIFO/sim/tb_fifo_async.fdo
+++ b/lib/FIFO/sim/tb_fifo_async.fdo
@@ -3,7 +3,7 @@
 vlib work
 vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../src/gray_counter.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
 vcom -explicit  -93 "../src/fifo_async_ctrl.vhd"
 vcom -explicit  -93 "../src/fifo_async.vhd"
 vcom -explicit  -93 "../src/tb_fifo_async.vhd"
diff --git a/lib/FIFO/sim/tb_fifo_sync.fdo b/lib/FIFO/sim/tb_fifo_sync.fdo
index 6922e87..b247a72 100644
--- a/lib/FIFO/sim/tb_fifo_sync.fdo
+++ b/lib/FIFO/sim/tb_fifo_sync.fdo
@@ -2,7 +2,7 @@
 ##
 vlib work
 vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
 vcom -explicit  -93 "../src/fifo_sync_ctrl.vhd"
 vcom -explicit  -93 "../src/fifo_sync.vhd"
 vcom -explicit  -93 "../src/tb_fifo_sync.vhd"
diff --git a/lib/FIFO/src/fifo_async_ctrl.vhd b/lib/FIFO/src/fifo_async_ctrl.vhd
index 17733b6..349c4b5 100644
--- a/lib/FIFO/src/fifo_async_ctrl.vhd
+++ b/lib/FIFO/src/fifo_async_ctrl.vhd
@@ -71,6 +71,7 @@ architecture Behavioral of fifo_async_ctrl is
 
 	signal pre_empty, pre_full : std_logic;
 	signal full, empty : std_logic;
+	signal rst_w, rst_r : std_logic;
 
 	-- synthesis translate_off
 	signal diffw		: signed (addr_width downto 0);
@@ -85,25 +86,45 @@ begin
 	fifo_empty		<= empty;
 	fifo_pre_full	<= pre_full;
 	fifo_pre_empty	<= pre_empty;
+	
+sync_reset_w:
+	process(clk_w)
+	begin
+		if rising_edge(clk_w) then
+			rst_w <= rst;
+		end if;
+	end process;
+
+sync_reset_r:
+	process(clk_r)
+	begin
+		if rising_edge(clk_r) then
+			rst_r <= rst;
+		end if;
+	end process;
 	
 proc_write_inhibit:
-	process(rst, clk_w)
+	process(clk_w)
 	begin
-		if rst = '1' then
-			full	<= '0';
-		elsif rising_edge(clk_w) then
-			full	<= pre_full;
+		if rising_edge(clk_w) then
+			if rst_w = '1' then
+				full	<= '0';
+			else
+				full	<= pre_full;
+			end if;
 		end if;
 	end process;
 	
 proc_read_inhibit:
-	process(rst, clk_r)
+	process(clk_r)
 	begin
-		if rst = '1' then
-			empty	<= '1';
-		elsif rising_edge(clk_r) then
-			empty	<= pre_empty;
-		end if;
+		if rising_edge(clk_r) then
+			if rst_r = '1' then
+				empty	<= '1';
+			else
+				empty	<= pre_empty;
+			end if;
+		end if;
 	end process;
 
 proc_sync_grptr:
@@ -171,42 +192,46 @@ proc_ptr_awptr:
 	end process;
 	
 proc_status_almost_full:
-	process(rst, clk_w)
+	process(clk_w)
 	variable diff : unsigned (addr_width downto 0);
 	begin
 	-- synthesis translate_off
 		diffw <= signed(diff);
 	-- synthesis translate_on
-		if rst = '1' then
-			fifo_afull <= '0';
-			diff := (others => '0');
-		elsif rising_edge(clk_w) then
-			if diff >= almost_full_thresh-1 then
-				fifo_afull <= '1';
-			else
-				fifo_afull <= '0';
-			end if;	
-			diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
+		if rising_edge(clk_w) then
+			if rst_w = '1' then
+				fifo_afull <= '0';
+				diff := (others => '0');
+			else
+				if diff >= almost_full_thresh-1 then
+					fifo_afull <= '1';
+				else
+					fifo_afull <= '0';
+				end if;	
+				diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
+			end if;
 		end if;
 	end process;
 
 proc_status_almost_empty:
-	process(rst, clk_r)
+	process(clk_r)
 	variable diff : unsigned (addr_width downto 0);
 	begin
 	-- synthesis translate_off
 		diffr <= signed(diff);
 	-- synthesis translate_on
-		if rst = '1' then
-			fifo_aempty <= '1';
-			diff := (others => '0');
-		elsif rising_edge(clk_r) then
-			if diff <= almost_empty_thresh+1 then
-				fifo_aempty <= '1';
-			else
-				fifo_aempty <= '0';
-			end if;	
-			diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
+		if rising_edge(clk_r) then
+			if rst_r = '1' then
+				fifo_aempty <= '1';
+				diff := (others => '0');
+			else
+				if diff <= almost_empty_thresh+1 then
+					fifo_aempty <= '1';
+				else
+					fifo_aempty <= '0';
+				end if;	
+				diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
+			end if;
 		end if;
 	end process;
 
@@ -218,7 +243,7 @@ inst_gray_counter_w : entity work.gray_counter
 		)
 	port map
 	(
-		rst			=> rst,
+		rst			=> rst_w,
 		clk			=> clk_w,
 		ce			=> winc, 
 		bcnt		=> bcnt_w,
@@ -235,7 +260,7 @@ inst_gray_counter_r : entity work.gray_counter
 		)
 	port map
 	(
-		rst			=> rst,
+		rst			=> rst_r,
 		clk			=> clk_r,
 		ce			=> rinc, 
 		bcnt		=> bcnt_r,
diff --git a/lib/FIFO/src/fifo_sync_ctrl.vhd b/lib/FIFO/src/fifo_sync_ctrl.vhd
index a198fa1..988daea 100644
--- a/lib/FIFO/src/fifo_sync_ctrl.vhd
+++ b/lib/FIFO/src/fifo_sync_ctrl.vhd
@@ -68,64 +68,74 @@ begin
 
 
 proc_diff_gen:
-	process(rst, clk)
+	process(clk)
 	begin
-		if rst = '1' then
-			diff <= (others => '0');
-		elsif rising_edge(clk) then
-			if winc = '1' and rinc = '0' then
-				diff <= diff + 1;
-			elsif winc = '0' and rinc = '1' then
-				diff <= diff - 1;
-			end if;
+		if rising_edge(clk) then
+			if rst = '1' then
+				diff <= (others => '0');
+			else
+				if winc = '1' and rinc = '0' then
+					diff <= diff + 1;
+				elsif winc = '0' and rinc = '1' then
+					diff <= diff - 1;
+				end if;
+			end if;
 		end if;
 	end process;
 
 proc_status_almost_full:
-	process(rst, clk)
+	process(clk)
 	begin
-		if rst = '1' then
-			fifo_afull <= '0';
-		elsif rising_edge(clk) then
-			if diff >= almost_full_thresh-1 then
-				fifo_afull <= '1';
-			else
-				fifo_afull <= '0';
-			end if;	
+		if rising_edge(clk) then
+			if rst = '1' then
+				fifo_afull <= '0';
+			else
+				if diff >= almost_full_thresh-1 then
+					fifo_afull <= '1';
+				else
+					fifo_afull <= '0';
+				end if;	
+			end if;
 		end if;
 	end process;
 
 proc_status_almost_empty:
-	process(rst, clk)
+	process(clk)
 	begin
-		if rst = '1' then
-			fifo_aempty <= '1';
-		elsif rising_edge(clk) then
-			if diff <= almost_empty_thresh+1 then
-				fifo_aempty <= '1';
-			else
-				fifo_aempty <= '0';
-			end if;	
+		if rising_edge(clk) then
+			if rst = '1' then
+				fifo_aempty <= '1';
+			else
+				if diff <= almost_empty_thresh+1 then
+					fifo_aempty <= '1';
+				else
+					fifo_aempty <= '0';
+				end if;	
+			end if;
 		end if;
 	end process;
 
 proc_full_reg:
-	process(rst, clk)
+	process(clk)
 	begin
-		if rst = '1' then
-			full <= '0';
-		elsif rising_edge(clk) then
-			full <= pre_full;
+		if rising_edge(clk) then
+			if rst = '1' then
+				full <= '0';
+			else
+				full <= pre_full;
+			end if;
 		end if;
 	end process;
 	
 proc_empty_reg:
-	process(rst, clk)
+	process(clk)
 	begin
-		if rst = '1' then
-			empty <= '1';
-		elsif rising_edge(clk) then
-			empty <= pre_empty;
+		if rising_edge(clk) then
+			if rst = '1' then
+				empty <= '1';
+			else
+				empty <= pre_empty;
+			end if;
 		end if;
 	end process;
 	
@@ -147,10 +157,10 @@ proc_status_w:
 proc_flag_write:
 	process(rst, clk)
 	begin
-		if rst = '1' then
-			was_write <= '0';
-		elsif rising_edge(clk) then
-			if winc = '1' then
+		if rising_edge(clk) then
+			if rst = '1' then
+				was_write <= '0';
+			elsif winc = '1' then
 				was_write <= '1';
 			elsif rinc = '1' then
 				was_write <= '0';
@@ -158,40 +168,34 @@ proc_flag_write:
 		end if;
 	end process;
 	
+	pW_next <= (pW + 1) when winc = '1' else pW;
+	ptr_w		<= pW;
+
 proc_ptr_w:
-	process(rst, clk, pW, winc)
+	process(clk)
 	begin
-		if rst = '1' then
-			pW <= to_unsigned(0, addr_width);
-			pW_next <= to_unsigned(0, addr_width);
-		elsif rising_edge(clk) then
-			if winc = '1' then 
+		if rising_edge(clk) then
+			if rst = '1' then
+				pW <= to_unsigned(0, addr_width);
+			else
 				pW <= pW_next;
 			end if;
 		end if;
-		pW_next <= pW;
-		if winc = '1' then 
-			pW_next <= pW + 1;
-		end if;
-		ptr_w		<= pW;
 	end process;
 
+	pR_next	<= (pR + 1) when rinc = '1' else pR;
+	ptr_r		<= pR_next;
+
 proc_ptr_r:
-	process(rst, clk, pR_next, pR, rinc)
+	process(clk)
 	begin
-		if rst = '1' then
-			pR <= to_unsigned(0, addr_width);
-			pR_next <= to_unsigned(0, addr_width);
-		elsif rising_edge(clk) then
-			if rinc = '1' then
+		if rising_edge(clk) then
+			if rst = '1' then
+				pR <= to_unsigned(0, addr_width);
+			else
 				pR <= pR_next;
 			end if;	
 		end if;
-		pR_next	<= pR;
-		if rinc = '1' then
-			pR_next	<= pR + 1;
-		end if;
-		ptr_r		<= pR_next;
 	end process;
 
 end Behavioral;
diff --git a/lib/FIFO/src/gray_counter.vhd b/lib/FIFO/src/gray_counter.vhd
index 990f15b..ae814fd 100644
--- a/lib/FIFO/src/gray_counter.vhd
+++ b/lib/FIFO/src/gray_counter.vhd
@@ -60,25 +60,21 @@ begin
 	bcnt	<= cntb;
 	gcnt	<= cntg;
 
-	process(rst, clk, ce, cntb, nxtb)
-	begin
-		if rst = '1' then
-			cntb	<= to_unsigned(init_value, width);
-			nxtb	<= to_unsigned(init_value, width);
-			nxtg	<= to_unsigned(init_value, width);
-			cntg	<= to_unsigned(init_value, width);
-		else
-			if rising_edge(clk) then
-				cntg	<= nxtg;
-				cntb	<= nxtb;
-			end if;	
-			nxtg <= bin2gray(nxtb);
-			nxtb <= cntb;
-			if ce = '1' then
-				nxtb <= cntb + 1;
-			end if;	
-		end if;	
-	end process;
-
+	nxtg <= bin2gray(nxtb);
+	nxtb <= (cntb + 1) when ce = '1' else cntb;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				cntb	<= to_unsigned(init_value, width);
+				cntg	<= to_unsigned(init_value, width);
+			else
+				cntg	<= nxtg;
+				cntb	<= nxtb;
+			end if;
+		end if;	
+	end process;
+
 end Behavioral;