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- reworked FIFOs

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- use synchronous resets

git-svn-id: http://moon:8086/svn/vhdl/trunk@1090 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-16 15:05:04 +00:00
parent bbd2673d42
commit deefbcffb3
5 changed files with 145 additions and 120 deletions
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lib/FIFO/src/fifo_sync_ctrl.vhd
+67 -63
View File
@@ -68,64 +68,74 @@ begin
proc_diff_gen:
process(rst, clk)
process(clk)
begin
if rst = '1' then
diff <= (others => '0');
elsif rising_edge(clk) then
if winc = '1' and rinc = '0' then
diff <= diff + 1;
elsif winc = '0' and rinc = '1' then
diff <= diff - 1;
end if;
if rising_edge(clk) then
if rst = '1' then
diff <= (others => '0');
else
if winc = '1' and rinc = '0' then
diff <= diff + 1;
elsif winc = '0' and rinc = '1' then
diff <= diff - 1;
end if;
end if;
end if;
end process;
proc_status_almost_full:
process(rst, clk)
process(clk)
begin
if rst = '1' then
fifo_afull <= '0';
elsif rising_edge(clk) then
if diff >= almost_full_thresh-1 then
fifo_afull <= '1';
else
fifo_afull <= '0';
end if;
if rising_edge(clk) then
if rst = '1' then
fifo_afull <= '0';
else
if diff >= almost_full_thresh-1 then
fifo_afull <= '1';
else
fifo_afull <= '0';
end if;
end if;
end if;
end process;
proc_status_almost_empty:
process(rst, clk)
process(clk)
begin
if rst = '1' then
fifo_aempty <= '1';
elsif rising_edge(clk) then
if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1';
else
fifo_aempty <= '0';
end if;
if rising_edge(clk) then
if rst = '1' then
fifo_aempty <= '1';
else
if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1';
else
fifo_aempty <= '0';
end if;
end if;
end if;
end process;
proc_full_reg:
process(rst, clk)
process(clk)
begin
if rst = '1' then
full <= '0';
elsif rising_edge(clk) then
full <= pre_full;
if rising_edge(clk) then
if rst = '1' then
full <= '0';
else
full <= pre_full;
end if;
end if;
end process;
proc_empty_reg:
process(rst, clk)
process(clk)
begin
if rst = '1' then
empty <= '1';
elsif rising_edge(clk) then
empty <= pre_empty;
if rising_edge(clk) then
if rst = '1' then
empty <= '1';
else
empty <= pre_empty;
end if;
end if;
end process;
@@ -147,10 +157,10 @@ proc_status_w:
proc_flag_write:
process(rst, clk)
begin
if rst = '1' then
was_write <= '0';
elsif rising_edge(clk) then
if winc = '1' then
if rising_edge(clk) then
if rst = '1' then
was_write <= '0';
elsif winc = '1' then
was_write <= '1';
elsif rinc = '1' then
was_write <= '0';
@@ -158,40 +168,34 @@ proc_flag_write:
end if;
end process;
pW_next <= (pW + 1) when winc = '1' else pW;
ptr_w <= pW;
proc_ptr_w:
process(rst, clk, pW, winc)
process(clk)
begin
if rst = '1' then
pW <= to_unsigned(0, addr_width);
pW_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if winc = '1' then
if rising_edge(clk) then
if rst = '1' then
pW <= to_unsigned(0, addr_width);
else
pW <= pW_next;
end if;
end if;
pW_next <= pW;
if winc = '1' then
pW_next <= pW + 1;
end if;
ptr_w <= pW;
end process;
pR_next <= (pR + 1) when rinc = '1' else pR;
ptr_r <= pR_next;
proc_ptr_r:
process(rst, clk, pR_next, pR, rinc)
process(clk)
begin
if rst = '1' then
pR <= to_unsigned(0, addr_width);
pR_next <= to_unsigned(0, addr_width);
elsif rising_edge(clk) then
if rinc = '1' then
if rising_edge(clk) then
if rst = '1' then
pR <= to_unsigned(0, addr_width);
else
pR <= pR_next;
end if;
end if;
pR_next <= pR;
if rinc = '1' then
pR_next <= pR + 1;
end if;
ptr_r <= pR_next;
end process;
end Behavioral;