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- reworked FIFOs

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- use synchronous resets

git-svn-id: http://moon:8086/svn/vhdl/trunk@1090 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-16 15:05:04 +00:00
parent bbd2673d42
commit deefbcffb3
5 changed files with 145 additions and 120 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/FIFO/src/fifo_async_ctrl.vhd
+60 -35
View File
@@ -71,6 +71,7 @@ architecture Behavioral of fifo_async_ctrl is
signal pre_empty, pre_full : std_logic;
signal full, empty : std_logic;
signal rst_w, rst_r : std_logic;
-- synthesis translate_off
signal diffw : signed (addr_width downto 0);
@@ -85,25 +86,45 @@ begin
fifo_empty <= empty;
fifo_pre_full <= pre_full;
fifo_pre_empty <= pre_empty;
sync_reset_w:
process(clk_w)
begin
if rising_edge(clk_w) then
rst_w <= rst;
end if;
end process;
sync_reset_r:
process(clk_r)
begin
if rising_edge(clk_r) then
rst_r <= rst;
end if;
end process;
proc_write_inhibit:
process(rst, clk_w)
process(clk_w)
begin
if rst = '1' then
full <= '0';
elsif rising_edge(clk_w) then
full <= pre_full;
if rising_edge(clk_w) then
if rst_w = '1' then
full <= '0';
else
full <= pre_full;
end if;
end if;
end process;
proc_read_inhibit:
process(rst, clk_r)
process(clk_r)
begin
if rst = '1' then
empty <= '1';
elsif rising_edge(clk_r) then
empty <= pre_empty;
end if;
if rising_edge(clk_r) then
if rst_r = '1' then
empty <= '1';
else
empty <= pre_empty;
end if;
end if;
end process;
proc_sync_grptr:
@@ -171,42 +192,46 @@ proc_ptr_awptr:
end process;
proc_status_almost_full:
process(rst, clk_w)
process(clk_w)
variable diff : unsigned (addr_width downto 0);
begin
-- synthesis translate_off
diffw <= signed(diff);
-- synthesis translate_on
if rst = '1' then
fifo_afull <= '0';
diff := (others => '0');
elsif rising_edge(clk_w) then
if diff >= almost_full_thresh-1 then
fifo_afull <= '1';
else
fifo_afull <= '0';
end if;
diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
if rising_edge(clk_w) then
if rst_w = '1' then
fifo_afull <= '0';
diff := (others => '0');
else
if diff >= almost_full_thresh-1 then
fifo_afull <= '1';
else
fifo_afull <= '0';
end if;
diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
end if;
end if;
end process;
proc_status_almost_empty:
process(rst, clk_r)
process(clk_r)
variable diff : unsigned (addr_width downto 0);
begin
-- synthesis translate_off
diffr <= signed(diff);
-- synthesis translate_on
if rst = '1' then
fifo_aempty <= '1';
diff := (others => '0');
elsif rising_edge(clk_r) then
if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1';
else
fifo_aempty <= '0';
end if;
diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
if rising_edge(clk_r) then
if rst_r = '1' then
fifo_aempty <= '1';
diff := (others => '0');
else
if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1';
else
fifo_aempty <= '0';
end if;
diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
end if;
end if;
end process;
@@ -218,7 +243,7 @@ inst_gray_counter_w : entity work.gray_counter
)
port map
(
rst => rst,
rst => rst_w,
clk => clk_w,
ce => winc,
bcnt => bcnt_w,
@@ -235,7 +260,7 @@ inst_gray_counter_r : entity work.gray_counter
)
port map
(
rst => rst,
rst => rst_r,
clk => clk_r,
ce => rinc,
bcnt => bcnt_r,