jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- fixed mips_sys after refactoring

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1562 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-28 18:02:48 +00:00
parent 3803aa154c
commit dda7811902
4 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/src/mips_sys.ssram.vhd
+6 -6
View File
@@ -307,7 +307,7 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
COMPONENT vga_frontend
COMPONENT vga_frontend_jb64
GENERIC
(
sys_freq : integer;
@@ -937,15 +937,15 @@ inst_clockgen : entity work.clockgen
rst => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0°
sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270°
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0
sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270
sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0
sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270
locked_out => locked, -- DCM locked status
error_out => open
);
inst_vga_frontend : vga_frontend
inst_vga_frontend : vga_frontend_jb64
GENERIC MAP
(
sys_freq => 100E6,
projects/mips_sys/src/mips_sys.vhd
+1 -1
View File
@@ -290,7 +290,7 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
COMPONENT vga_frontend64
COMPONENT vga_frontend_jb64
GENERIC
(
fifo_depth : integer;