From dda7811902d47ffb04b90ad9a82bad21c724da9a Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 28 Mar 2021 18:02:48 +0000 Subject: [PATCH] - fixed mips_sys after refactoring git-svn-id: http://moon:8086/svn/vhdl/trunk@1562 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/ghdl/tb_mips_sys.make | 4 ++-- .../mips_sys/ise101/mips_sys/project/mips_sys.prj | 2 +- projects/mips_sys/src/mips_sys.ssram.vhd | 12 ++++++------ projects/mips_sys/src/mips_sys.vhd | 2 +- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/projects/mips_sys/ghdl/tb_mips_sys.make b/projects/mips_sys/ghdl/tb_mips_sys.make index 324cb51..87617db 100644 --- a/projects/mips_sys/ghdl/tb_mips_sys.make +++ b/projects/mips_sys/ghdl/tb_mips_sys.make @@ -38,7 +38,7 @@ SRCS += $(LIB_PATH)/VGA_ctrl/src/char_gen.vhd SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_sync.vhd SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_timing.vhd SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_backend.vhd -SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_frontend64.vhd +SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_frontend_jb64.vhd # UART SRCS += $(LIB_PATH)/uart/src/uart_types.vhd @@ -99,7 +99,7 @@ TARGET := tb_mips_sys ENTITY = tb_mips_sys RUN_TIME := 10ms -GHDL_OPTS := -P$(ROOT_PATH)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit +GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit include $(VHDL_HOME)/make/ghdl.mk diff --git a/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj index c9e5d95..f04dd2c 100644 --- a/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj +++ b/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj @@ -46,7 +46,7 @@ vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd" vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd" vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd" vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd" +vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend_jb64.vhd" vhdl work "../../../../lib/ps2_port/src/ps2_core.vhd" vhdl work "../../../../lib/ps2_port/src/debounce.vhd" vhdl work "../../../../lib/ps2_port/src/ps2_wb.vhd" diff --git a/projects/mips_sys/src/mips_sys.ssram.vhd b/projects/mips_sys/src/mips_sys.ssram.vhd index 845d560..da137da 100644 --- a/projects/mips_sys/src/mips_sys.ssram.vhd +++ b/projects/mips_sys/src/mips_sys.ssram.vhd @@ -307,7 +307,7 @@ ARCHITECTURE behavior OF mips_sys IS ); END COMPONENT; - COMPONENT vga_frontend + COMPONENT vga_frontend_jb64 GENERIC ( sys_freq : integer; @@ -937,15 +937,15 @@ inst_clockgen : entity work.clockgen rst => rst_in, -- external async reset, low active clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board clk_fb_in => sys_sdr_clk_fb, -- feedback clock - sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0° - sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270° + sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0 + sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270 + sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0 + sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270 locked_out => locked, -- DCM locked status error_out => open ); -inst_vga_frontend : vga_frontend +inst_vga_frontend : vga_frontend_jb64 GENERIC MAP ( sys_freq => 100E6, diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index 99f3c61..0676ca3 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -290,7 +290,7 @@ ARCHITECTURE behavior OF mips_sys IS ); END COMPONENT; - COMPONENT vga_frontend64 + COMPONENT vga_frontend_jb64 GENERIC ( fifo_depth : integer;