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Introduced J-Bus

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git-svn-id: http://moon:8086/svn/vhdl/trunk@27 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-07 17:26:27 +00:00
parent 3ecd76f185
commit dd38d30198
14 changed files with 4720 additions and 4523 deletions
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lib/CPUs/MIPS/src/core/dcache.vhd
+43 -43
View File
@@ -14,8 +14,14 @@ ENTITY dcache IS
); );
Port Port
( (
clk : in STD_LOGIC; RST_I : in STD_LOGIC;
rst : in STD_LOGIC; CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
STB_O : out STD_LOGIC;
CYC_O : out STD_LOGIC;
en : in STD_LOGIC; en : in STD_LOGIC;
cpu_en : in STD_LOGIC; cpu_en : in STD_LOGIC;
cpu_r_wn : in STD_LOGIC; cpu_r_wn : in STD_LOGIC;
@@ -23,14 +29,7 @@ ENTITY dcache IS
cpu_addr : in word_t; cpu_addr : in word_t;
cpu_din : in word_t; cpu_din : in word_t;
cpu_dout : out word_t; cpu_dout : out word_t;
cpu_busy : out STD_LOGIC; cpu_busy : out STD_LOGIC
mem_req : out STD_LOGIC;
mem_gnt : in STD_LOGIC;
mem_en : out STD_LOGIC;
mem_addr : out word_t;
mem_din : in word_t;
mem_valid : in STD_LOGIC;
mem_rdy : in STD_LOGIC
); );
END dcache; END dcache;
@@ -181,10 +180,10 @@ begin
cpu_index_reg: cpu_index_reg:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if rst = '1' then if RST_I = '1' then
cache_index_reg <= (others => '0'); cache_index_reg <= (others => '0');
tag_index_reg <= (others => '0'); tag_index_reg <= (others => '0');
cpu_was_write <= '0'; cpu_was_write <= '0';
@@ -200,9 +199,9 @@ cpu_index_reg:
end process; end process;
cpu_was_wr_reg: cpu_was_wr_reg:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
cpu_was_en <= '0'; cpu_was_en <= '0';
cpu_we2 <= '0'; cpu_we2 <= '0';
if cpu_en = '1' and en = '1' then if cpu_en = '1' and en = '1' then
@@ -219,8 +218,8 @@ inst_tag_ram : dpram_1w1r
data_width => tram_data_width data_width => tram_data_width
) )
PORT MAP ( PORT MAP (
clka => clk, clka => CLK_I,
clkb => clk, clkb => CLK_I,
en_a => '1', en_a => '1',
en_b => tram_re, en_b => tram_re,
we_a => tram_we, we_a => tram_we,
@@ -240,8 +239,8 @@ gen_data_ram:
data_width => word_t'length/4 data_width => word_t'length/4
) )
PORT MAP ( PORT MAP (
clk_a => clk, clk_a => CLK_I,
clk_b => clk, clk_b => CLK_I,
en_a => '1', en_a => '1',
en_b => dram_en, en_b => dram_en,
we_a => ctrl_dram_we(i), we_a => ctrl_dram_we(i),
@@ -256,10 +255,10 @@ gen_data_ram:
end generate; end generate;
cache_state_next: cache_state_next:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if rst = '1' then if RST_I = '1' then
s <= init; s <= init;
else else
s <= sn; s <= sn;
@@ -277,14 +276,14 @@ cache_state_next:
tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
cache_entry_out <= to_dcache_entry(tram_dout); cache_entry_out <= to_dcache_entry(tram_dout);
cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg); cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg);
mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
ctrl_dram_din <= mem_din; ctrl_dram_din <= DAT_I;
ctrl_dram_we <= (3 downto 0 => (data_write and mem_valid)) or ctrl_force_we; ctrl_dram_we <= (3 downto 0 => (data_write and ACK_I)) or ctrl_force_we;
cpu_dram_we <= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0'); cpu_dram_we <= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0');
cache_state: cache_state:
process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, cpu_r_wn, mem_gnt, mem_rdy, cpu_was_en, cpu_was_write, cpu_we_reg) process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, cpu_r_wn, SRDY_I, cpu_was_en, cpu_was_write, cpu_we_reg)
begin begin
cpu_reg_en <= '0'; cpu_reg_en <= '0';
cache_busy <= '1'; cache_busy <= '1';
@@ -293,8 +292,8 @@ cache_state:
ram_index_count_rst <= '0'; ram_index_count_rst <= '0';
mem_index_count_en <= '0'; mem_index_count_en <= '0';
mem_index_count_rst <= '0'; mem_index_count_rst <= '0';
mem_req <= '0'; CYC_O <= '0';
mem_en <= '0'; STB_O <= '0';
dram_en <= '0'; dram_en <= '0';
tram_re <= '0'; tram_re <= '0';
was_miss <= '0'; was_miss <= '0';
@@ -320,6 +319,7 @@ cache_state:
sn <= mem_request; sn <= mem_request;
cpu_reg_en <= '0'; cpu_reg_en <= '0';
cache_busy <= '1'; cache_busy <= '1';
CYC_O <= '1';
end if; end if;
end if; end if;
when flush => when flush =>
@@ -339,30 +339,30 @@ cache_state:
when mem_request => when mem_request =>
ram_index_count_rst <= '1'; ram_index_count_rst <= '1';
mem_index_count_rst <= '1'; mem_index_count_rst <= '1';
mem_req <= '1'; CYC_O <= '1';
if mem_gnt = '1' then if SRDY_I = '1' then
sn <= mem_access; sn <= mem_access;
end if; end if;
when mem_access => when mem_access =>
data_write <= '1'; data_write <= '1';
mem_req <= '1'; CYC_O <= '1';
if mem_rdy = '1' then if SRDY_I = '1' then
mem_index_count_en <= '1'; mem_index_count_en <= '1';
mem_en <= '1'; STB_O <= '1';
if mem_index_count = 2**word_index_width-1 then if mem_index_count = 2**word_index_width-1 then
sn <= mem_data; sn <= mem_data;
end if; end if;
end if; end if;
when mem_data => when mem_data =>
mem_req <= '1'; CYC_O <= '1';
data_write <= '1'; data_write <= '1';
if ram_index_count = 2**word_index_width-1 then if ram_index_count = 2**word_index_width-1 then
if mem_valid = '1' then if ACK_I = '1' then
sn <= upd_cache; sn <= upd_cache;
end if; end if;
end if; end if;
when upd_cache => when upd_cache =>
mem_req <= '1'; CYC_O <= '1';
tram_addr_wr <= cache_index_reg; tram_addr_wr <= cache_index_reg;
tram_we <= '1'; tram_we <= '1';
cache_entry_in.valid <= '1'; cache_entry_in.valid <= '1';
@@ -388,9 +388,9 @@ cache_state:
end process; end process;
cache_index_counter: cache_index_counter:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if cache_index_count_en = '0' then if cache_index_count_en = '0' then
cache_index_count <= 2**cache_index_width-1; cache_index_count <= 2**cache_index_width-1;
elsif cache_index_count /= 0 then elsif cache_index_count /= 0 then
@@ -400,12 +400,12 @@ cache_index_counter:
end process; end process;
ram_index_counter: ram_index_counter:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if ram_index_count_rst = '1' then if ram_index_count_rst = '1' then
ram_index_count <= 0; ram_index_count <= 0;
elsif data_write = '1' and mem_valid = '1' then elsif data_write = '1' and ACK_I = '1' then
if ram_index_count /= 2**word_index_width-1 then if ram_index_count /= 2**word_index_width-1 then
ram_index_count <= ram_index_count + 1; ram_index_count <= ram_index_count + 1;
end if; end if;
@@ -414,9 +414,9 @@ ram_index_counter:
end process; end process;
mem_index_counter: mem_index_counter:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if mem_index_count_rst = '1' then if mem_index_count_rst = '1' then
mem_index_count <= 0; mem_index_count <= 0;
elsif mem_index_count_en = '1' then elsif mem_index_count_en = '1' then
lib/CPUs/MIPS/src/core/icache.vhd
+42 -42
View File
@@ -14,20 +14,19 @@ ENTITY icache IS
); );
Port Port
( (
clk : in STD_LOGIC; RST_I : in STD_LOGIC;
rst : in STD_LOGIC; CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
STB_O : out STD_LOGIC;
CYC_O : out STD_LOGIC;
en : in STD_LOGIC; en : in STD_LOGIC;
cpu_en : in STD_LOGIC; cpu_en : in STD_LOGIC;
cpu_addr : in word_t; cpu_addr : in word_t;
cpu_dout : out word_t; cpu_dout : out word_t;
cpu_busy : out STD_LOGIC; cpu_busy : out STD_LOGIC
mem_req : out STD_LOGIC;
mem_gnt : in STD_LOGIC;
mem_en : out STD_LOGIC;
mem_addr : out word_t;
mem_din : in word_t;
mem_valid : in STD_LOGIC;
mem_rdy : in STD_LOGIC
); );
END icache; END icache;
@@ -143,10 +142,10 @@ begin
cpu_index_reg: cpu_index_reg:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if rst = '1' then if RST_I = '1' then
cache_index_reg <= (others => '0'); cache_index_reg <= (others => '0');
tag_index_reg <= (others => '0'); tag_index_reg <= (others => '0');
elsif cpu_reg_en = '1' then elsif cpu_reg_en = '1' then
@@ -163,8 +162,8 @@ inst_tag_ram : dpram_1w1r
data_width => tag_ram_data_width data_width => tag_ram_data_width
) )
PORT MAP ( PORT MAP (
clka => clk, clka => CLK_I,
clkb => clk, clkb => CLK_I,
en_a => '1', en_a => '1',
en_b => tag_ram_re, en_b => tag_ram_re,
we_a => tag_ram_we, we_a => tag_ram_we,
@@ -180,8 +179,8 @@ inst_data_ram : dpram_1w1r
data_width => word_t'length data_width => word_t'length
) )
PORT MAP ( PORT MAP (
clka => clk, clka => CLK_I,
clkb => clk, clkb => CLK_I,
en_a => '1', en_a => '1',
en_b => data_ram_re, en_b => data_ram_re,
we_a => data_ram_we, we_a => data_ram_we,
@@ -193,10 +192,10 @@ inst_data_ram : dpram_1w1r
cache_state_next: cache_state_next:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if rst = '1' then if RST_I = '1' then
s <= init; s <= init;
else else
s <= sn; s <= sn;
@@ -213,13 +212,13 @@ cache_state_next:
tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
cache_entry_out <= to_icache_entry(tag_ram_data_rd); cache_entry_out <= to_icache_entry(tag_ram_data_rd);
data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg); data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg);
mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
data_ram_addr_wr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); data_ram_addr_wr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
data_ram_data_wr <= mem_din; data_ram_data_wr <= DAT_I;
data_ram_we <= data_write and mem_valid; data_ram_we <= data_write and ACK_I;
cache_state: cache_state:
process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, mem_gnt, mem_rdy, en) process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, en)
begin begin
cpu_reg_en <= '0'; cpu_reg_en <= '0';
cache_busy <= '1'; cache_busy <= '1';
@@ -228,8 +227,8 @@ cache_state:
ram_index_count_rst <= '0'; ram_index_count_rst <= '0';
mem_index_count_en <= '0'; mem_index_count_en <= '0';
mem_index_count_rst <= '0'; mem_index_count_rst <= '0';
mem_req <= '0'; CYC_O <= '0';
mem_en <= '0'; STB_O <= '0';
data_ram_re <= '0'; data_ram_re <= '0';
tag_ram_re <= '0'; tag_ram_re <= '0';
was_miss <= '0'; was_miss <= '0';
@@ -250,6 +249,7 @@ cache_state:
sn <= mem_request; sn <= mem_request;
cpu_reg_en <= '0'; cpu_reg_en <= '0';
cache_busy <= '1'; cache_busy <= '1';
CYC_O <= '1';
elsif cpu_en = '1' then elsif cpu_en = '1' then
cpu_reg_en <= '1'; cpu_reg_en <= '1';
data_ram_re <= '1'; data_ram_re <= '1';
@@ -273,37 +273,37 @@ cache_state:
when mem_request => when mem_request =>
ram_index_count_rst <= '1'; ram_index_count_rst <= '1';
mem_index_count_rst <= '1'; mem_index_count_rst <= '1';
mem_req <= '1'; CYC_O <= '1';
if mem_gnt = '1' then if SRDY_I = '1' then
sn <= mem_access; sn <= mem_access;
end if; end if;
when mem_access => when mem_access =>
data_write <= '1'; data_write <= '1';
mem_req <= '1'; CYC_O <= '1';
if mem_rdy = '1' then if SRDY_I = '1' then
mem_index_count_en <= '1'; mem_index_count_en <= '1';
mem_en <= '1'; STB_O <= '1';
if mem_index_count = 2**word_index_width-1 then if mem_index_count = 2**word_index_width-1 then
sn <= mem_data; sn <= mem_data;
end if; end if;
end if; end if;
when mem_data => when mem_data =>
mem_req <= '1'; CYC_O <= '1';
data_write <= '1'; data_write <= '1';
if ram_index_count = 2**word_index_width-1 then if ram_index_count = 2**word_index_width-1 then
if mem_valid = '1' then if ACK_I = '1' then
sn <= upd_cache; sn <= upd_cache;
end if; end if;
end if; end if;
when upd_cache => when upd_cache =>
mem_req <= '1'; CYC_O <= '1';
tag_ram_addr_wr <= cache_index_reg; tag_ram_addr_wr <= cache_index_reg;
tag_ram_we <= '1'; tag_ram_we <= '1';
cache_entry_in.valid <= '1'; cache_entry_in.valid <= '1';
sn <= rd_cache; sn <= rd_cache;
when rd_cache => when rd_cache =>
-- mem_req <= '1'; -- CYC_O <= '1';
tag_ram_re <= '1'; tag_ram_re <= '1';
data_ram_re <= '1'; data_ram_re <= '1';
was_miss <= '1'; was_miss <= '1';
@@ -314,9 +314,9 @@ cache_state:
end process; end process;
cache_index_counter: cache_index_counter:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if cache_index_count_en = '0' then if cache_index_count_en = '0' then
cache_index_count <= 2**cache_index_width-1; cache_index_count <= 2**cache_index_width-1;
elsif cache_index_count /= 0 then elsif cache_index_count /= 0 then
@@ -326,12 +326,12 @@ cache_index_counter:
end process; end process;
ram_index_counter: ram_index_counter:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if ram_index_count_rst = '1' then if ram_index_count_rst = '1' then
ram_index_count <= 0; ram_index_count <= 0;
elsif data_write = '1' and mem_valid = '1' then elsif data_write = '1' and ACK_I = '1' then
if ram_index_count /= 2**word_index_width-1 then if ram_index_count /= 2**word_index_width-1 then
ram_index_count <= ram_index_count + 1; ram_index_count <= ram_index_count + 1;
end if; end if;
@@ -340,9 +340,9 @@ ram_index_counter:
end process; end process;
mem_index_counter: mem_index_counter:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if mem_index_count_rst = '1' then if mem_index_count_rst = '1' then
mem_index_count <= 0; mem_index_count <= 0;
elsif mem_index_count_en = '1' then elsif mem_index_count_en = '1' then
lib/CPUs/MIPS/src/core/mips_bui.vhd
+275 -200
View File
@@ -31,10 +31,18 @@ use work.mips_types.all;
entity bui is entity bui is
Port Port
( (
rst : in STD_LOGIC; RST_I : in STD_LOGIC;
clk : in STD_LOGIC; CLK_I : in STD_LOGIC;
ce : in STD_LOGIC; ACK_I : in STD_LOGIC;
cpu_wait : out STD_LOGIC; SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
DAT_O : out word_t;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC;
cpu_imem_rdy : out STD_LOGIC; cpu_imem_rdy : out STD_LOGIC;
cpu_imem_en : in STD_LOGIC; cpu_imem_en : in STD_LOGIC;
cpu_imem_addr : in word_t; cpu_imem_addr : in word_t;
@@ -45,22 +53,13 @@ entity bui is
cpu_dmem_we : in unsigned(3 downto 0); cpu_dmem_we : in unsigned(3 downto 0);
cpu_dmem_dout : in word_t; cpu_dmem_dout : in word_t;
cpu_dmem_din : out word_t; cpu_dmem_din : out word_t;
cpu_dmem_addr : in word_t; cpu_dmem_addr : in word_t
mem_valid : in STD_LOGIC;
mem_rdy : in STD_LOGIC;
mem_addr : out word_t;
mem_din : in word_t;
mem_dout : out word_t;
mem_re : out STD_LOGIC;
mem_we : out unsigned(3 downto 0);
mem_ce : out STD_LOGIC
); );
end bui; end bui;
architecture behavior of bui is architecture behavior of bui is
COMPONENT icache COMPONENT icache
GENERIC GENERIC
( (
cache_size : natural := 2048; -- words cache_size : natural := 2048; -- words
@@ -68,24 +67,23 @@ COMPONENT icache
); );
PORT PORT
( (
clk : in STD_LOGIC; RST_I : in STD_LOGIC;
rst : in STD_LOGIC; CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
STB_O : out STD_LOGIC;
CYC_O : out STD_LOGIC;
en : in STD_LOGIC; en : in STD_LOGIC;
cpu_en : in STD_LOGIC; cpu_en : in STD_LOGIC;
cpu_addr : in word_t; cpu_addr : in word_t;
cpu_dout : out word_t; cpu_dout : out word_t;
cpu_busy : out STD_LOGIC; cpu_busy : out STD_LOGIC
mem_en : out STD_LOGIC;
mem_req : out STD_LOGIC;
mem_gnt : in STD_LOGIC;
mem_addr : out word_t;
mem_din : in word_t;
mem_valid : in STD_LOGIC;
mem_rdy : in STD_LOGIC
); );
END COMPONENT; END COMPONENT;
COMPONENT dcache COMPONENT dcache
GENERIC GENERIC
( (
cache_size : natural := 2048; -- words cache_size : natural := 2048; -- words
@@ -93,8 +91,14 @@ COMPONENT dcache
); );
PORT PORT
( (
clk : in STD_LOGIC; RST_I : in STD_LOGIC;
rst : in STD_LOGIC; CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
STB_O : out STD_LOGIC;
CYC_O : out STD_LOGIC;
en : in STD_LOGIC; en : in STD_LOGIC;
cpu_en : in STD_LOGIC; cpu_en : in STD_LOGIC;
cpu_r_wn : in STD_LOGIC; cpu_r_wn : in STD_LOGIC;
@@ -102,54 +106,141 @@ COMPONENT dcache
cpu_addr : in word_t; cpu_addr : in word_t;
cpu_din : in word_t; cpu_din : in word_t;
cpu_dout : out word_t; cpu_dout : out word_t;
cpu_busy : out STD_LOGIC; cpu_busy : out STD_LOGIC
mem_req : out STD_LOGIC;
mem_gnt : in STD_LOGIC;
mem_en : out STD_LOGIC;
mem_addr : out word_t;
mem_din : in word_t;
mem_valid : in STD_LOGIC;
mem_rdy : in STD_LOGIC
); );
END COMPONENT; END COMPONENT;
type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, d_bus_start, d_bus_access, d_bus_finish); type ca_state_t is (ca_init, ca_ready, ca_bus_access, ca_bus_fin);
type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, uncached_bus_access);
signal s, sn : bus_state_t; signal s, sn : bus_state_t;
signal dmem_re : std_logic; signal s_ca, sn_ca : ca_state_t;
signal dmem_we : unsigned(3 downto 0); signal dmem_we : unsigned(3 downto 0);
signal dcache_dout : word_t; signal dcache_dout : word_t;
signal dmem_dout : word_t; signal dcache_mem_gnt : std_logic;
signal dmem_din : word_t; signal icache_mem_gnt : std_logic;
signal dmem_addr : word_t; signal dmem_mem_gnt : std_logic;
signal imem_addr : word_t;
signal imem_mem_out_en : std_logic;
signal dmem_mem_out_en : std_logic;
signal dmem_ack : std_logic;
signal dcache_busy1 : std_logic; signal dcache_busy1 : std_logic;
signal dcache_busy2 : std_logic; signal dcache_busy2 : std_logic;
signal icache_busy : std_logic; signal icache_busy : std_logic;
signal bus_req : std_logic; signal CYC_O_icache : std_logic;
signal icache_mem_en : std_logic; signal CYC_O_dcache : std_logic;
signal icache_mem_req : std_logic; signal CYC_O_dmem : std_logic;
signal icache_mem_gnt : std_logic; signal SRDY_I_icache : std_logic;
signal icache_mem_addr : word_t; signal SRDY_I_dcache : std_logic;
signal dcache_mem_en : std_logic; signal SRDY_I_dmem : std_logic;
signal dcache_mem_req : std_logic; signal ADDR_O_icache : word_t;
signal dcache_mem_gnt : std_logic; signal ADDR_O_dcache : word_t;
signal dcache_mem_addr : word_t; signal ADDR_O_dmem : word_t;
signal STB_O_icache : std_logic;
signal STB_O_dcache : std_logic;
signal STB_O_dmem : std_logic;
signal DAT_I_dmem : word_t;
signal DAT_O_dmem : word_t;
signal SEL_O_dmem : unsigned(3 downto 0);
signal WE_O_dmem : std_logic;
signal dcached : std_logic; signal dcached : std_logic;
signal duncached_access : std_logic;
signal dcache_en : std_logic; signal dcache_en : std_logic;
signal ca_reg_en : std_logic;
type bui_eval_t is record
addr : word_t;
dout : word_t;
en : std_logic;
re : std_logic;
we : unsigned (3 downto 0);
end record;
signal bui_eval : bui_eval_t;
begin begin
mem_ce <= mem_rdy and bus_req; proc_bui_eval:
process(CLK_I)
variable en : std_logic;
begin
if rising_edge(CLK_I) then
en := cpu_dmem_en and not dcache_busy1;
bui_eval.en <= en;
if RST_I = '1' then
bui_eval.addr <= (others => '0');
bui_eval.dout <= (others => '0');
bui_eval.re <= '0';
bui_eval.we <= (others => '0');
elsif en = '1' then
bui_eval.addr <= cpu_dmem_addr;
bui_eval.dout <= cpu_dmem_dout;
bui_eval.re <= cpu_dmem_re;
bui_eval.we <= cpu_dmem_we;
end if;
end if;
end process;
bus_strobe:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
STB_O <= '0';
elsif dmem_mem_gnt = '1' then
STB_O <= STB_O_dmem;
elsif dcache_mem_gnt = '1' then
STB_O <= STB_O_dcache;
elsif icache_mem_gnt = '1' then
STB_O <= STB_O_icache;
elsif SRDY_I = '1' then
STB_O <= '0';
end if;
end if;
end process;
bus_out:
process(CLK_I)
begin
if rising_edge(CLK_I) then
CYC_O <= '0';
WE_O <= '0';
SEL_O <= (others => '0');
if RST_I = '1' then
ADDR_O <= (others => '0');
DAT_O <= (others => '0');
elsif dmem_mem_gnt = '1' then
CYC_O <= CYC_O_dmem;
ADDR_O <= ADDR_O_dmem;
DAT_O <= DAT_O_dmem;
WE_O <= WE_O_dmem;
SEL_O <= SEL_O_dmem;
elsif dcache_mem_gnt = '1' then
CYC_O <= CYC_O_dcache;
ADDR_O <= ADDR_O_dcache;
elsif icache_mem_gnt = '1' then
CYC_O <= CYC_O_icache;
ADDR_O <= ADDR_O_icache;
end if;
end if;
end process;
MRDY_O <= '1';
-- ADDR_O <= ADDR_O_dcache when dcache_mem_gnt = '1' else
-- ADDR_O_icache when icache_mem_gnt = '1' else ADDR_O_dmem;
-- DAT_O <= DAT_O_dmem when dmem_mem_gnt = '1' else X"BEEFBABE";
-- SEL_O <= SEL_O_dmem when dmem_mem_gnt = '1' else "0000";
-- WE_O <= WE_O_dmem when dmem_mem_gnt = '1' else '0';
-- STB_O <= STB_O_icache when icache_mem_gnt = '1' else
-- STB_O_dcache when dcache_mem_gnt = '1' else
-- STB_O_dmem when dmem_mem_gnt = '1' else '0';
-- CYC_O <= CYC_O_icache when icache_mem_gnt = '1' else
-- CYC_O_dcache when dcache_mem_gnt = '1' else
-- CYC_O_dmem when dmem_mem_gnt = '1' else '0';
SRDY_I_icache <= SRDY_I when icache_mem_gnt = '1' else '0';
SRDY_I_dcache <= SRDY_I when dcache_mem_gnt = '1' else '0';
SRDY_I_dmem <= SRDY_I when dmem_mem_gnt = '1' else '0';
cpu_imem_rdy <= not icache_busy after 4.5 ns; cpu_imem_rdy <= not icache_busy after 4.5 ns;
-- cpu_imem_din <= imem_din; -- cpu_imem_din <= imem_din;
-- cpu_wait <= busy after 5.5 ns; -- cpu_wait <= busy after 5.5 ns;
cpu_wait <= '0';
cpu_dmem_rdy <= not (dcache_busy1 or dcache_busy2) after 4.5 ns; cpu_dmem_rdy <= not (dcache_busy1 or dcache_busy2) after 4.5 ns;
inst_icache : icache inst_icache : icache
@@ -160,20 +251,19 @@ inst_icache : icache
) )
PORT MAP PORT MAP
( (
clk => clk, CLK_I => CLK_I,
rst => rst, RST_I => RST_I,
STB_O => STB_O_icache,
CYC_O => CYC_O_icache,
ADDR_O => ADDR_O_icache,
DAT_I => DAT_I,
ACK_I => ACK_I,
SRDY_I => SRDY_I_icache,
en => '1', en => '1',
cpu_en => cpu_imem_en, cpu_en => cpu_imem_en,
cpu_addr => cpu_imem_addr, cpu_addr => cpu_imem_addr,
cpu_dout => cpu_imem_din, cpu_dout => cpu_imem_din,
cpu_busy => icache_busy, cpu_busy => icache_busy
mem_en => icache_mem_en,
mem_req => icache_mem_req,
mem_gnt => icache_mem_gnt,
mem_addr => icache_mem_addr,
mem_din => mem_din,
mem_valid => mem_valid,
mem_rdy => mem_rdy
); );
inst_dcache : dcache inst_dcache : dcache
@@ -184,8 +274,14 @@ inst_dcache : dcache
) )
PORT MAP PORT MAP
( (
clk => clk, CLK_I => CLK_I,
rst => rst, RST_I => RST_I,
CYC_O => CYC_O_dcache,
STB_O => STB_O_dcache,
ADDR_O => ADDR_O_dcache,
DAT_I => DAT_I,
ACK_I => ACK_I,
SRDY_I => SRDY_I_dcache,
en => dcached, en => dcached,
cpu_en => dcache_en, cpu_en => dcache_en,
cpu_r_wn => cpu_dmem_re, cpu_r_wn => cpu_dmem_re,
@@ -193,139 +289,160 @@ inst_dcache : dcache
cpu_addr => cpu_dmem_addr, cpu_addr => cpu_dmem_addr,
cpu_din => cpu_dmem_dout, cpu_din => cpu_dmem_dout,
cpu_dout => dcache_dout, cpu_dout => dcache_dout,
cpu_busy => dcache_busy2, cpu_busy => dcache_busy2
mem_req => dcache_mem_req,
mem_gnt => dcache_mem_gnt,
mem_en => dcache_mem_en,
mem_addr => dcache_mem_addr,
mem_din => mem_din,
mem_valid => mem_valid,
mem_rdy => mem_rdy
); );
dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0'; dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0';
cpu_dmem_din <= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns; cpu_dmem_din <= DAT_I_dmem when dmem_mem_gnt = '1' else dcache_dout;
dcache_en <= cpu_dmem_en and not dcache_busy1; dcache_en <= cpu_dmem_en and not dcache_busy1;
dcache_flags: proc_busy:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if rst = '1' then if RST_I = '1' then
dcache_busy1 <= '0'; dcache_busy1 <= '0';
else elsif ACK_I = '1' and dmem_mem_gnt = '1' then
duncached_access <= '0'; dcache_busy1 <= '0';
if dmem_ack = '1' then elsif cpu_dmem_en = '1' and ca_reg_en = '1' then
duncached_access <= '1'; dcache_busy1 <= '1';
if dmem_re = '1' then end if;
if mem_valid = '1' then
dcache_busy1 <= '0';
end if;
else
dcache_busy1 <= '0';
end if;
end if;
if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then
dcache_busy1 <= '1';
if dcached = '1' and cpu_dmem_re = '1' then
dcache_busy1 <= '0';
end if;
end if;
end if;
end if; end if;
end process; end process;
dcache_regs: dcache_regs:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then if RST_I = '1' then
dmem_dout <= cpu_dmem_dout; WE_O_dmem <= '0';
dmem_addr <= cpu_dmem_addr; SEL_O_dmem <= (others => '0');
dmem_re <= cpu_dmem_re; elsif cpu_dmem_en = '1' and ca_reg_en = '1' then
dmem_we <= cpu_dmem_we; DAT_O_dmem <= cpu_dmem_dout;
ADDR_O_dmem <= cpu_dmem_addr;
WE_O_dmem <= not cpu_dmem_re;
SEL_O_dmem <= cpu_dmem_we;
end if; end if;
end if; end if;
end process; end process;
dcache_data: dcache_data:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if rst = '1' then if RST_I = '1' then
dmem_din <= (others => '0'); DAT_I_dmem <= (others => '0');
elsif dcache_busy1 = '1' and mem_valid = '1' then elsif ACK_I = '1' and dmem_mem_gnt = '1' then
dmem_din <= mem_din; DAT_I_dmem <= DAT_I;
end if; end if;
end if; end if;
end process; end process;
cpu_access_state_next:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
s_ca <= ca_init;
else
s_ca <= sn_ca;
end if;
end if;
end process;
cpu_access_state:
process(s_ca, cpu_dmem_en, cpu_dmem_re, dcached, SRDY_I_dmem, ACK_I)
begin
ca_reg_en <= '0';
CYC_O_dmem <= '0';
STB_O_dmem <= '0';
sn_ca <= s_ca;
case s_ca is
when ca_init =>
sn_ca <= ca_ready;
when ca_ready =>
if cpu_dmem_en = '1' then
if dcached = '0' or cpu_dmem_re = '0' then
ca_reg_en <= '1';
sn_ca <= ca_bus_access;
end if;
end if;
when ca_bus_access =>
CYC_O_dmem <= '1';
if SRDY_I_dmem = '1' then
STB_O_dmem <= '1';
sn_ca <= ca_bus_fin;
end if;
when ca_bus_fin =>
CYC_O_dmem <= '1';
if ACK_I = '1' then
sn_ca <= ca_ready;
-- CYC_O_dmem <= '0';
end if;
when others =>
sn_ca <= ca_ready;
end case;
end process;
bus_state_next: bus_state_next:
process(clk) process(CLK_I)
begin begin
if rising_edge(clk) then if rising_edge(CLK_I) then
if rst = '1' then if RST_I = '1' then
s <= init; s <= init;
elsif ce = '1' then else
s <= sn; s <= sn;
end if; end if;
end if; end if;
end process; end process;
bus_state: bus_state:
process(s, icache_mem_en, icache_mem_req, dcache_busy1, dcache_mem_req, dcache_mem_en, dmem_re, mem_rdy, mem_valid) process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem)
begin begin
imem_mem_out_en <= '0'; icache_mem_gnt <= '0';
dmem_mem_out_en <= '0'; dcache_mem_gnt <= '0';
icache_mem_gnt <= '0'; dmem_mem_gnt <= '0';
dcache_mem_gnt <= '0'; sn <= s;
dmem_ack <= '0';
sn <= s;
case s is case s is
when init => when init =>
if mem_rdy = '1' then sn <= ready;
sn <= ready;
end if;
when ready => when ready =>
if dcache_busy1 = '1' then if CYC_O_dmem = '1' then
if mem_rdy = '1' then sn <= uncached_bus_access;
dmem_mem_out_en <= '1'; dmem_mem_gnt <= '1';
if dmem_re = '0' then elsif CYC_O_icache = '1' then
sn <= d_bus_finish;
else
sn <= d_bus_access;
end if;
end if;
elsif icache_mem_req = '1' then
sn <= i_cache_bus_access; sn <= i_cache_bus_access;
elsif dcache_mem_req = '1' then icache_mem_gnt <= '1';
elsif CYC_O_dcache = '1' then
sn <= d_cache_bus_access; sn <= d_cache_bus_access;
dcache_mem_gnt <= '1';
end if; end if;
when i_cache_bus_access => when i_cache_bus_access =>
icache_mem_gnt <= '1'; icache_mem_gnt <= '1';
if icache_mem_en = '1' then if CYC_O_icache = '0' then
imem_mem_out_en <= '1';
elsif icache_mem_req = '0' then
sn <= ready; sn <= ready;
-- icache_mem_gnt <= '0';
end if; end if;
when d_cache_bus_access => when d_cache_bus_access =>
dcache_mem_gnt <= '1'; dcache_mem_gnt <= '1';
if dcache_mem_en = '1' then if CYC_O_dcache = '0' then
dmem_mem_out_en <= '1';
elsif dcache_mem_req = '0' then
sn <= ready; sn <= ready;
-- dcache_mem_gnt <= '0';
end if; end if;
when d_bus_access => when uncached_bus_access =>
if mem_valid = '1' then dmem_mem_gnt <= '1';
dmem_ack <= '1'; if CYC_O_dmem = '0' then
sn <= ready; sn <= ready;
end if; -- dmem_mem_gnt <= '0';
when d_bus_finish =>
if mem_rdy = '1' then
dmem_ack <= '1';
sn <= ready;
end if; end if;
when others => when others =>
sn <= ready; sn <= ready;
@@ -333,48 +450,6 @@ bus_state:
end process; end process;
bus_request:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
bus_req <= '0';
elsif dmem_mem_out_en = '1' or imem_mem_out_en = '1' then
bus_req <= '1';
elsif mem_rdy = '1' then
bus_req <= '0';
end if;
end if;
end process;
bus_out:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
mem_dout <= (others => '0');
mem_addr <= (others => '0');
mem_re <= '0';
mem_we <= (others => '0');
elsif dmem_mem_out_en = '1' then
if dcache_mem_gnt = '1' then
mem_addr <= dcache_mem_addr;
mem_re <= '1';
mem_we <= (others => '0');
else
mem_dout <= dmem_dout;
mem_addr <= dmem_addr;
mem_re <= dmem_re;
mem_we <= dmem_we;
end if;
elsif imem_mem_out_en = '1' then
mem_addr <= icache_mem_addr;
mem_re <= '1';
mem_we <= (others => '0');
end if;
end if;
end process;
------------------------------------------------------------------- -------------------------------------------------------------------
end behavior; end behavior;
lib/CPUs/MIPS/src/core/mips_top.vhd
+46 -44
View File
@@ -31,17 +31,19 @@ use work.mips_types.all;
entity mips_top is entity mips_top is
Port Port
( (
rst : in STD_LOGIC; RST_I : in STD_LOGIC;
clk : in STD_LOGIC; CLK_I : in STD_LOGIC;
int : in unsigned (5 downto 0); ACK_I : in STD_LOGIC;
mem_valid : in STD_LOGIC; SRDY_I : in STD_LOGIC;
mem_rdy : in STD_LOGIC; ADDR_O : out word_t;
mem_en : out STD_LOGIC; DAT_I : in word_t;
mem_re : out STD_LOGIC; DAT_O : out word_t;
mem_we : out unsigned(3 downto 0); WE_O : out STD_LOGIC;
mem_din : in unsigned (WORD_WIDTH-1 downto 0); SEL_O : out unsigned(3 downto 0);
mem_dout : out unsigned (WORD_WIDTH-1 downto 0); CYC_O : out STD_LOGIC;
mem_addr : out unsigned (WORD_WIDTH-1 downto 0) STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC;
INT : in unsigned (5 downto 0)
); );
end mips_top; end mips_top;
@@ -67,7 +69,6 @@ architecture rtl of mips_top is
dmem_dout : out word_t dmem_dout : out word_t
); );
END COMPONENT; END COMPONENT;
signal halt : std_logic;
signal imem_rdy : std_logic; signal imem_rdy : std_logic;
signal imem_en : std_logic; signal imem_en : std_logic;
signal imem_addr : word_t; signal imem_addr : word_t;
@@ -80,13 +81,22 @@ architecture rtl of mips_top is
signal dmem_din : word_t; signal dmem_din : word_t;
signal dmem_we : unsigned(3 downto 0); signal dmem_we : unsigned(3 downto 0);
COMPONENT bui COMPONENT bui
Port PORT
( (
rst : in STD_LOGIC; RST_I : in STD_LOGIC;
clk : in STD_LOGIC; CLK_I : in STD_LOGIC;
ce : in STD_LOGIC; ACK_I : in STD_LOGIC;
cpu_wait : out STD_LOGIC; SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
DAT_O : out word_t;
WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0);
CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC;
cpu_imem_rdy : out STD_LOGIC; cpu_imem_rdy : out STD_LOGIC;
cpu_imem_en : in STD_LOGIC; cpu_imem_en : in STD_LOGIC;
cpu_imem_addr : in word_t; cpu_imem_addr : in word_t;
@@ -95,17 +105,9 @@ architecture rtl of mips_top is
cpu_dmem_en : in STD_LOGIC; cpu_dmem_en : in STD_LOGIC;
cpu_dmem_re : in STD_LOGIC; cpu_dmem_re : in STD_LOGIC;
cpu_dmem_we : in unsigned(3 downto 0); cpu_dmem_we : in unsigned(3 downto 0);
cpu_dmem_addr : in word_t;
cpu_dmem_din : out word_t;
cpu_dmem_dout : in word_t; cpu_dmem_dout : in word_t;
mem_valid : in STD_LOGIC; cpu_dmem_din : out word_t;
mem_rdy : in STD_LOGIC; cpu_dmem_addr : in word_t
mem_addr : out word_t;
mem_din : in word_t;
mem_dout : out word_t;
mem_re : out STD_LOGIC;
mem_we : out unsigned(3 downto 0);
mem_ce : out STD_LOGIC
); );
END COMPONENT; END COMPONENT;
@@ -116,10 +118,10 @@ begin
inst_pipeline: pipeline inst_pipeline: pipeline
PORT MAP PORT MAP
( (
rst => rst, rst => RST_I,
clk => clk, clk => CLK_I,
halt => halt, halt => '0',
int => int, int => INT,
imem_rdy => imem_rdy, imem_rdy => imem_rdy,
imem_en => imem_en, imem_en => imem_en,
imem_addr => imem_addr, imem_addr => imem_addr,
@@ -136,10 +138,18 @@ inst_pipeline: pipeline
inst_bui: bui inst_bui: bui
PORT MAP PORT MAP
( (
rst => rst, RST_I => RST_I,
clk => clk, CLK_I => CLK_I,
ce => '1', ACK_I => ACK_I,
cpu_wait => halt, SRDY_I => SRDY_I,
ADDR_O => ADDR_O,
DAT_I => DAT_I,
DAT_O => DAT_O,
WE_O => WE_O,
SEL_O => SEL_O,
CYC_O => CYC_O,
STB_O => STB_O,
MRDY_O => MRDY_O,
cpu_imem_rdy => imem_rdy, cpu_imem_rdy => imem_rdy,
cpu_imem_en => imem_en, cpu_imem_en => imem_en,
cpu_imem_addr => imem_addr, cpu_imem_addr => imem_addr,
@@ -150,15 +160,7 @@ inst_bui: bui
cpu_dmem_we => dmem_we, cpu_dmem_we => dmem_we,
cpu_dmem_addr => dmem_addr, cpu_dmem_addr => dmem_addr,
cpu_dmem_din => dmem_din, cpu_dmem_din => dmem_din,
cpu_dmem_dout => dmem_dout, cpu_dmem_dout => dmem_dout
mem_valid => mem_valid,
mem_rdy => mem_rdy,
mem_addr => mem_addr,
mem_din => mem_din,
mem_dout => mem_dout,
mem_re => mem_re,
mem_we => mem_we,
mem_ce => mem_en
); );
end rtl; end rtl;
projects/mips_sys/ise92/mips_sys/mips_sys.prj
+20 -14
View File
@@ -6,14 +6,16 @@ vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd" vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r_dist.vhd" vhdl work "../../../../lib/misc/dpram_1w1r_dist.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r.vhd" vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd" vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd" vhdl work "../../../../lib/uart/kcuart_tx.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd" vhdl work "../../../../lib/uart/kcuart_rx.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd" vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
@@ -23,17 +25,21 @@ vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/icache.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/icache.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/dcache.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/dcache.vhd"
vhdl work "../../../../lib/uart/kcuart_tx.vhd" vhdl work "../../src/sys_types.vhd"
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
vhdl work "../../src/ram_ld.vhd" vhdl work "../../src/ram_ld.vhd"
vhdl work "../../src/bootloader.ROM_ld.vhd" vhdl work "../../src/bootloader.ROM_ld.vhd"
vhdl work "../../../../lib/uart/uart_tx.vhd" vhdl work "../../../../lib/uart/uart_tx.vhd"
vhdl work "../../../../lib/uart/uart_rx.vhd" vhdl work "../../../../lib/uart/uart_rx.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
vhdl work "../../src/rom_wb.vhd"
vhdl work "../../src/ram_wb.vhd"
vhdl work "../../src/gpio_wb.vhd"
vhdl work "../../../../lib/uart/uart_wb.vhd"
vhdl work "../../../../lib/misc/lcd_port.vhd" vhdl work "../../../../lib/misc/lcd_port.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd" vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
vhdl work "../../../../lib/misc/async_port_wb.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
vhdl work "../../src/mips_sys.vhd" vhdl work "../../src/mips_sys.vhd"
projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
+20 -14
View File
@@ -6,14 +6,16 @@ vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd" vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd" vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd" vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd" vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd" vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd" vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd" vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd" vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd" vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
@@ -23,17 +25,21 @@ vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd" vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd" vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd" vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd" vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\rom_wb.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_wb.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\gpio_wb.vhd"
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd" vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_frontend.vhd" vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd" vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
projects/mips_sys/sim/tb_mips_sys.fdo
+20 -10
View File
@@ -8,9 +8,9 @@ vcom -explicit -93 "../src/sdram_config_sim.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
# RAMs # RAMs
vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd" vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd"
@@ -32,6 +32,8 @@ vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
vcom -explicit -93 "../src/ram_sim.vhd" vcom -explicit -93 "../src/ram_sim.vhd"
vcom -explicit -93 "../src/bootloader.ROM.vhd" vcom -explicit -93 "../src/bootloader.ROM.vhd"
vcom -explicit -93 "../src/ram_wb.vhd"
vcom -explicit -93 "../src/rom_wb.vhd"
# UART # UART
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd" vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
@@ -39,23 +41,31 @@ vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd" vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd" vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd" vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
vcom -explicit -93 "../../../lib/uart/uart_wb.vhd"
# GPIO
vcom -explicit -93 "../src/gpio_wb.vhd"
# LCD # LCD
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd" vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
# Flash and USB
vcom -explicit -93 "../src/sys_types.vhd"
vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd"
# FIFOS # FIFOS
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd" vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
# SDRAM # SDRAM
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd" vcom -explicit -93 "../../../lib/misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
# Top and TB # Top and TB
vcom -explicit -93 "../src/mips_sys_sim.vhd" vcom -explicit -93 "../src/mips_sys_sim.vhd"
projects/mips_sys/sim/tb_mips_sys.wdo
+70 -81
View File
@@ -13,6 +13,7 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
add wave -noupdate -format Logic /tb_mips_sys/refresh add wave -noupdate -format Logic /tb_mips_sys/refresh
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
@@ -26,12 +27,61 @@ add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_a_q add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_a_q
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_data add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_data
add wave -noupdate -format Literal /tb_mips_sys/sys_error add wave -noupdate -format Literal /tb_mips_sys/sys_error
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
add wave -noupdate -divider BUI
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s_ca
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval
add wave -noupdate -format Literal -label .addr -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.addr
add wave -noupdate -format Literal -label .dout -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.dout
add wave -noupdate -format Logic -label .en -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.en
add wave -noupdate -format Logic -label .re -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.re
add wave -noupdate -format Literal -label .we -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
add wave -noupdate -divider USB
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
add wave -noupdate -divider Flash
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_d
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_a
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_wrn
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rdn
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rstn
add wave -noupdate -divider {MIPS TOP} add wave -noupdate -divider {MIPS TOP}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_wait
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
@@ -45,18 +95,15 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit
add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending
add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit
@@ -67,55 +114,21 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1 add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/rst
add wave -noupdate -divider BUI
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_req
add wave -noupdate -format Logic /tb_mips_sys/uut/mem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_addr
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_req
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dmem_ack
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dmem_valid
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -divider {Memory Bus}
add wave -noupdate -format Logic /tb_mips_sys/uut/mem_en
add wave -noupdate -format Logic /tb_mips_sys/uut/mem_re
add wave -noupdate -format Logic /tb_mips_sys/uut/mem_re_r
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_we_r
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_re
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_ce
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_valid
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/r_wn
add wave -noupdate -divider {CPU DMEM} add wave -noupdate -divider {CPU DMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/contention add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
@@ -125,7 +138,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
add wave -noupdate -divider {CPU IMEM} add wave -noupdate -divider {CPU IMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
@@ -136,16 +149,9 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_addr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_addr
add wave -noupdate -divider UUT add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_buf_in
add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_busy_q
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_udata_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_udata_out_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_udata_req_wr
add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_udata_vld_q
add wave -noupdate -format Literal /tb_mips_sys/uut/st
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
@@ -159,15 +165,12 @@ add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
add wave -noupdate -format Literal /tb_mips_sys/uut/tick_usec
add wave -noupdate -divider I-Cache add wave -noupdate -divider I-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_wait
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en
@@ -177,13 +180,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_ic
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss
add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram
add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_req
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_gnt
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_din
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_valid
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we
@@ -191,6 +187,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write
add wave -noupdate -divider D-Cache add wave -noupdate -divider D-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_r_wn add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_r_wn
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
@@ -198,13 +195,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_req
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_gnt
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_din
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_valid
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_rdy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_read_miss add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_read_miss
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_write_miss add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_write_miss
@@ -224,9 +214,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/duncached_access
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1165623518 ps} 0} WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1129563255 ps} 0}
configure wave -namecolwidth 218 configure wave -namecolwidth 218
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
@@ -240,4 +229,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40 configure wave -griddelta 40
configure wave -timeline 1 configure wave -timeline 1
update update
WaveRestoreZoom {1165509887 ps} {1165713125 ps} WaveRestoreZoom {1129448646 ps} {1129766075 ps}
projects/mips_sys/src/bootloader.ROM.vhd
+1174 -1174
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File diff suppressed because it is too large Load Diff
projects/mips_sys/src/bootloader.ROM_ld.vhd
+835 -835
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File diff suppressed because it is too large Load Diff
projects/mips_sys/src/bootloader.dis
+1107 -1017
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File diff suppressed because it is too large Load Diff
projects/mips_sys/src/mips_sys.vhd
+510 -511
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File diff suppressed because it is too large Load Diff
projects/mips_sys/src/mips_sys_sim.vhd
+508 -538
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File diff suppressed because it is too large Load Diff
projects/mips_sys/src/tb_mips_sys.vhd
+50
View File
@@ -74,7 +74,24 @@ ARCHITECTURE behavior OF tb_mips_sys IS
signal sys_user_rom_en : std_logic; signal sys_user_rom_en : std_logic;
signal sys_user_rom_din : word_t; signal sys_user_rom_din : word_t;
signal sys_user_rom_addr : word_t; signal sys_user_rom_addr : word_t;
signal sys_usb_d : unsigned(15 downto 0) := (others => '0');
signal sys_usb_a : unsigned(1 downto 0);
signal sys_usb_csn : std_logic;
signal sys_usb_wrn : std_logic;
signal sys_usb_rdn : std_logic;
signal sys_usb_rstn : std_logic;
signal sys_usb_int : std_logic := '0';
signal sys_flash_d : word_t;
signal sys_flash_a : unsigned(24 downto 0);
signal sys_flash_ce : std_logic;
signal sys_flash_wrn : std_logic;
signal sys_flash_rdn : std_logic;
signal sys_flash_rstn : std_logic;
signal sys_flash_byten : std_logic;
signal flash_reg : word_t;
type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t; type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t;
signal urom_data : urom_data_t; signal urom_data : urom_data_t;
@@ -120,6 +137,23 @@ uut: entity work.mips_sys
sys_sdr_ba_q => sys_sdr_ba_q, sys_sdr_ba_q => sys_sdr_ba_q,
sys_sdr_a_q => sys_sdr_a_q, sys_sdr_a_q => sys_sdr_a_q,
sys_sdr_data => sys_sdr_data, sys_sdr_data => sys_sdr_data,
sys_usb_d => sys_usb_d,
sys_usb_a => sys_usb_a,
sys_usb_csn => sys_usb_csn,
sys_usb_wrn => sys_usb_wrn,
sys_usb_rdn => sys_usb_rdn,
sys_usb_rstn => sys_usb_rstn,
sys_usb_int => sys_usb_int,
sys_flash_d => sys_flash_d,
sys_flash_a => sys_flash_a,
sys_flash_ce => sys_flash_ce,
sys_flash_wrn => sys_flash_wrn,
sys_flash_rdn => sys_flash_rdn,
sys_flash_rstn => sys_flash_rstn,
sys_flash_byten => sys_flash_byten,
sys_error => sys_error sys_error => sys_error
); );
@@ -160,6 +194,7 @@ uut: entity work.mips_sys
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps; sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false; refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
sys_usb_d <= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
CLK_GEN: process CLK_GEN: process
begin begin
wait for CLK_PERIOD/2; wait for CLK_PERIOD/2;
@@ -187,6 +222,21 @@ UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
end if; end if;
end process; end process;
FLASH_WRITE: process(sys_flash_ce, sys_flash_wrn, sys_flash_d)
begin
if rising_edge(sys_flash_wrn) and sys_flash_ce = '1' then
flash_reg <= sys_flash_d;
end if;
end process;
FLASH_READ: process(sys_flash_ce, sys_flash_rdn, flash_reg)
begin
sys_flash_d <= (others => 'Z') after 10 ns;
if sys_flash_rdn = '0' and sys_flash_ce = '1' then
sys_flash_d <= flash_reg after 10 ns;
end if;
end process;
STIMULUS: process STIMULUS: process
begin begin