diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd index 367c9d5..a93dd68 100644 --- a/lib/CPUs/MIPS/src/core/dcache.vhd +++ b/lib/CPUs/MIPS/src/core/dcache.vhd @@ -14,8 +14,14 @@ ENTITY dcache IS ); Port ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + STB_O : out STD_LOGIC; + CYC_O : out STD_LOGIC; en : in STD_LOGIC; cpu_en : in STD_LOGIC; cpu_r_wn : in STD_LOGIC; @@ -23,14 +29,7 @@ ENTITY dcache IS cpu_addr : in word_t; cpu_din : in word_t; cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC + cpu_busy : out STD_LOGIC ); END dcache; @@ -181,10 +180,10 @@ begin cpu_index_reg: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then - if rst = '1' then + if rising_edge(CLK_I) then + if RST_I = '1' then cache_index_reg <= (others => '0'); tag_index_reg <= (others => '0'); cpu_was_write <= '0'; @@ -200,9 +199,9 @@ cpu_index_reg: end process; cpu_was_wr_reg: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then + if rising_edge(CLK_I) then cpu_was_en <= '0'; cpu_we2 <= '0'; if cpu_en = '1' and en = '1' then @@ -219,8 +218,8 @@ inst_tag_ram : dpram_1w1r data_width => tram_data_width ) PORT MAP ( - clka => clk, - clkb => clk, + clka => CLK_I, + clkb => CLK_I, en_a => '1', en_b => tram_re, we_a => tram_we, @@ -240,8 +239,8 @@ gen_data_ram: data_width => word_t'length/4 ) PORT MAP ( - clk_a => clk, - clk_b => clk, + clk_a => CLK_I, + clk_b => CLK_I, en_a => '1', en_b => dram_en, we_a => ctrl_dram_we(i), @@ -256,10 +255,10 @@ gen_data_ram: end generate; cache_state_next: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then - if rst = '1' then + if rising_edge(CLK_I) then + if RST_I = '1' then s <= init; else s <= sn; @@ -277,14 +276,14 @@ cache_state_next: tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; cache_entry_out <= to_dcache_entry(tram_dout); cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg); - mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; + ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); - ctrl_dram_din <= mem_din; - ctrl_dram_we <= (3 downto 0 => (data_write and mem_valid)) or ctrl_force_we; + ctrl_dram_din <= DAT_I; + ctrl_dram_we <= (3 downto 0 => (data_write and ACK_I)) or ctrl_force_we; cpu_dram_we <= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0'); cache_state: - process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, cpu_r_wn, mem_gnt, mem_rdy, cpu_was_en, cpu_was_write, cpu_we_reg) + process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, cpu_r_wn, SRDY_I, cpu_was_en, cpu_was_write, cpu_we_reg) begin cpu_reg_en <= '0'; cache_busy <= '1'; @@ -293,8 +292,8 @@ cache_state: ram_index_count_rst <= '0'; mem_index_count_en <= '0'; mem_index_count_rst <= '0'; - mem_req <= '0'; - mem_en <= '0'; + CYC_O <= '0'; + STB_O <= '0'; dram_en <= '0'; tram_re <= '0'; was_miss <= '0'; @@ -320,6 +319,7 @@ cache_state: sn <= mem_request; cpu_reg_en <= '0'; cache_busy <= '1'; + CYC_O <= '1'; end if; end if; when flush => @@ -339,30 +339,30 @@ cache_state: when mem_request => ram_index_count_rst <= '1'; mem_index_count_rst <= '1'; - mem_req <= '1'; - if mem_gnt = '1' then + CYC_O <= '1'; + if SRDY_I = '1' then sn <= mem_access; end if; when mem_access => data_write <= '1'; - mem_req <= '1'; - if mem_rdy = '1' then + CYC_O <= '1'; + if SRDY_I = '1' then mem_index_count_en <= '1'; - mem_en <= '1'; + STB_O <= '1'; if mem_index_count = 2**word_index_width-1 then sn <= mem_data; end if; end if; when mem_data => - mem_req <= '1'; + CYC_O <= '1'; data_write <= '1'; if ram_index_count = 2**word_index_width-1 then - if mem_valid = '1' then + if ACK_I = '1' then sn <= upd_cache; end if; end if; when upd_cache => - mem_req <= '1'; + CYC_O <= '1'; tram_addr_wr <= cache_index_reg; tram_we <= '1'; cache_entry_in.valid <= '1'; @@ -388,9 +388,9 @@ cache_state: end process; cache_index_counter: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then + if rising_edge(CLK_I) then if cache_index_count_en = '0' then cache_index_count <= 2**cache_index_width-1; elsif cache_index_count /= 0 then @@ -400,12 +400,12 @@ cache_index_counter: end process; ram_index_counter: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then + if rising_edge(CLK_I) then if ram_index_count_rst = '1' then ram_index_count <= 0; - elsif data_write = '1' and mem_valid = '1' then + elsif data_write = '1' and ACK_I = '1' then if ram_index_count /= 2**word_index_width-1 then ram_index_count <= ram_index_count + 1; end if; @@ -414,9 +414,9 @@ ram_index_counter: end process; mem_index_counter: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then + if rising_edge(CLK_I) then if mem_index_count_rst = '1' then mem_index_count <= 0; elsif mem_index_count_en = '1' then diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd index d7e3026..7506aac 100644 --- a/lib/CPUs/MIPS/src/core/icache.vhd +++ b/lib/CPUs/MIPS/src/core/icache.vhd @@ -14,20 +14,19 @@ ENTITY icache IS ); Port ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + STB_O : out STD_LOGIC; + CYC_O : out STD_LOGIC; en : in STD_LOGIC; cpu_en : in STD_LOGIC; cpu_addr : in word_t; cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC + cpu_busy : out STD_LOGIC ); END icache; @@ -143,10 +142,10 @@ begin cpu_index_reg: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then - if rst = '1' then + if rising_edge(CLK_I) then + if RST_I = '1' then cache_index_reg <= (others => '0'); tag_index_reg <= (others => '0'); elsif cpu_reg_en = '1' then @@ -163,8 +162,8 @@ inst_tag_ram : dpram_1w1r data_width => tag_ram_data_width ) PORT MAP ( - clka => clk, - clkb => clk, + clka => CLK_I, + clkb => CLK_I, en_a => '1', en_b => tag_ram_re, we_a => tag_ram_we, @@ -180,8 +179,8 @@ inst_data_ram : dpram_1w1r data_width => word_t'length ) PORT MAP ( - clka => clk, - clkb => clk, + clka => CLK_I, + clkb => CLK_I, en_a => '1', en_b => data_ram_re, we_a => data_ram_we, @@ -193,10 +192,10 @@ inst_data_ram : dpram_1w1r cache_state_next: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then - if rst = '1' then + if rising_edge(CLK_I) then + if RST_I = '1' then s <= init; else s <= sn; @@ -213,13 +212,13 @@ cache_state_next: tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; cache_entry_out <= to_icache_entry(tag_ram_data_rd); data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg); - mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; + ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; data_ram_addr_wr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); - data_ram_data_wr <= mem_din; - data_ram_we <= data_write and mem_valid; + data_ram_data_wr <= DAT_I; + data_ram_we <= data_write and ACK_I; cache_state: - process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, mem_gnt, mem_rdy, en) + process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, en) begin cpu_reg_en <= '0'; cache_busy <= '1'; @@ -228,8 +227,8 @@ cache_state: ram_index_count_rst <= '0'; mem_index_count_en <= '0'; mem_index_count_rst <= '0'; - mem_req <= '0'; - mem_en <= '0'; + CYC_O <= '0'; + STB_O <= '0'; data_ram_re <= '0'; tag_ram_re <= '0'; was_miss <= '0'; @@ -250,6 +249,7 @@ cache_state: sn <= mem_request; cpu_reg_en <= '0'; cache_busy <= '1'; + CYC_O <= '1'; elsif cpu_en = '1' then cpu_reg_en <= '1'; data_ram_re <= '1'; @@ -273,37 +273,37 @@ cache_state: when mem_request => ram_index_count_rst <= '1'; mem_index_count_rst <= '1'; - mem_req <= '1'; - if mem_gnt = '1' then + CYC_O <= '1'; + if SRDY_I = '1' then sn <= mem_access; end if; when mem_access => data_write <= '1'; - mem_req <= '1'; - if mem_rdy = '1' then + CYC_O <= '1'; + if SRDY_I = '1' then mem_index_count_en <= '1'; - mem_en <= '1'; + STB_O <= '1'; if mem_index_count = 2**word_index_width-1 then sn <= mem_data; end if; end if; when mem_data => - mem_req <= '1'; + CYC_O <= '1'; data_write <= '1'; if ram_index_count = 2**word_index_width-1 then - if mem_valid = '1' then + if ACK_I = '1' then sn <= upd_cache; end if; end if; when upd_cache => - mem_req <= '1'; + CYC_O <= '1'; tag_ram_addr_wr <= cache_index_reg; tag_ram_we <= '1'; cache_entry_in.valid <= '1'; sn <= rd_cache; when rd_cache => --- mem_req <= '1'; +-- CYC_O <= '1'; tag_ram_re <= '1'; data_ram_re <= '1'; was_miss <= '1'; @@ -314,9 +314,9 @@ cache_state: end process; cache_index_counter: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then + if rising_edge(CLK_I) then if cache_index_count_en = '0' then cache_index_count <= 2**cache_index_width-1; elsif cache_index_count /= 0 then @@ -326,12 +326,12 @@ cache_index_counter: end process; ram_index_counter: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then + if rising_edge(CLK_I) then if ram_index_count_rst = '1' then ram_index_count <= 0; - elsif data_write = '1' and mem_valid = '1' then + elsif data_write = '1' and ACK_I = '1' then if ram_index_count /= 2**word_index_width-1 then ram_index_count <= ram_index_count + 1; end if; @@ -340,9 +340,9 @@ ram_index_counter: end process; mem_index_counter: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then + if rising_edge(CLK_I) then if mem_index_count_rst = '1' then mem_index_count <= 0; elsif mem_index_count_en = '1' then diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd index c11b994..4ef3ced 100644 --- a/lib/CPUs/MIPS/src/core/mips_bui.vhd +++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd @@ -31,10 +31,18 @@ use work.mips_types.all; entity bui is Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - cpu_wait : out STD_LOGIC; + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + DAT_O : out word_t; + WE_O : out STD_LOGIC; + SEL_O : out unsigned(3 downto 0); + CYC_O : out STD_LOGIC; + STB_O : out STD_LOGIC; + MRDY_O : out STD_LOGIC; cpu_imem_rdy : out STD_LOGIC; cpu_imem_en : in STD_LOGIC; cpu_imem_addr : in word_t; @@ -45,22 +53,13 @@ entity bui is cpu_dmem_we : in unsigned(3 downto 0); cpu_dmem_dout : in word_t; cpu_dmem_din : out word_t; - cpu_dmem_addr : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_dout : out word_t; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_ce : out STD_LOGIC + cpu_dmem_addr : in word_t ); - end bui; architecture behavior of bui is -COMPONENT icache + COMPONENT icache GENERIC ( cache_size : natural := 2048; -- words @@ -68,24 +67,23 @@ COMPONENT icache ); PORT ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + STB_O : out STD_LOGIC; + CYC_O : out STD_LOGIC; en : in STD_LOGIC; cpu_en : in STD_LOGIC; cpu_addr : in word_t; cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_en : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC + cpu_busy : out STD_LOGIC ); -END COMPONENT; + END COMPONENT; -COMPONENT dcache + COMPONENT dcache GENERIC ( cache_size : natural := 2048; -- words @@ -93,8 +91,14 @@ COMPONENT dcache ); PORT ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + STB_O : out STD_LOGIC; + CYC_O : out STD_LOGIC; en : in STD_LOGIC; cpu_en : in STD_LOGIC; cpu_r_wn : in STD_LOGIC; @@ -102,54 +106,141 @@ COMPONENT dcache cpu_addr : in word_t; cpu_din : in word_t; cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC + cpu_busy : out STD_LOGIC ); -END COMPONENT; + END COMPONENT; - type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, d_bus_start, d_bus_access, d_bus_finish); + type ca_state_t is (ca_init, ca_ready, ca_bus_access, ca_bus_fin); + type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, uncached_bus_access); - signal s, sn : bus_state_t; - signal dmem_re : std_logic; + signal s, sn : bus_state_t; + signal s_ca, sn_ca : ca_state_t; signal dmem_we : unsigned(3 downto 0); signal dcache_dout : word_t; - signal dmem_dout : word_t; - signal dmem_din : word_t; - signal dmem_addr : word_t; - signal imem_addr : word_t; - signal imem_mem_out_en : std_logic; - signal dmem_mem_out_en : std_logic; - signal dmem_ack : std_logic; + signal dcache_mem_gnt : std_logic; + signal icache_mem_gnt : std_logic; + signal dmem_mem_gnt : std_logic; signal dcache_busy1 : std_logic; signal dcache_busy2 : std_logic; signal icache_busy : std_logic; - signal bus_req : std_logic; - signal icache_mem_en : std_logic; - signal icache_mem_req : std_logic; - signal icache_mem_gnt : std_logic; - signal icache_mem_addr : word_t; - signal dcache_mem_en : std_logic; - signal dcache_mem_req : std_logic; - signal dcache_mem_gnt : std_logic; - signal dcache_mem_addr : word_t; + signal CYC_O_icache : std_logic; + signal CYC_O_dcache : std_logic; + signal CYC_O_dmem : std_logic; + signal SRDY_I_icache : std_logic; + signal SRDY_I_dcache : std_logic; + signal SRDY_I_dmem : std_logic; + signal ADDR_O_icache : word_t; + signal ADDR_O_dcache : word_t; + signal ADDR_O_dmem : word_t; + signal STB_O_icache : std_logic; + signal STB_O_dcache : std_logic; + signal STB_O_dmem : std_logic; + signal DAT_I_dmem : word_t; + signal DAT_O_dmem : word_t; + signal SEL_O_dmem : unsigned(3 downto 0); + signal WE_O_dmem : std_logic; signal dcached : std_logic; - signal duncached_access : std_logic; signal dcache_en : std_logic; + signal ca_reg_en : std_logic; + type bui_eval_t is record + addr : word_t; + dout : word_t; + en : std_logic; + re : std_logic; + we : unsigned (3 downto 0); + end record; + + signal bui_eval : bui_eval_t; + begin - mem_ce <= mem_rdy and bus_req; +proc_bui_eval: + process(CLK_I) + variable en : std_logic; + begin + if rising_edge(CLK_I) then + en := cpu_dmem_en and not dcache_busy1; + bui_eval.en <= en; + if RST_I = '1' then + bui_eval.addr <= (others => '0'); + bui_eval.dout <= (others => '0'); + bui_eval.re <= '0'; + bui_eval.we <= (others => '0'); + elsif en = '1' then + bui_eval.addr <= cpu_dmem_addr; + bui_eval.dout <= cpu_dmem_dout; + bui_eval.re <= cpu_dmem_re; + bui_eval.we <= cpu_dmem_we; + end if; + end if; + end process; + +bus_strobe: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + STB_O <= '0'; + elsif dmem_mem_gnt = '1' then + STB_O <= STB_O_dmem; + elsif dcache_mem_gnt = '1' then + STB_O <= STB_O_dcache; + elsif icache_mem_gnt = '1' then + STB_O <= STB_O_icache; + elsif SRDY_I = '1' then + STB_O <= '0'; + end if; + end if; + end process; + +bus_out: + process(CLK_I) + begin + if rising_edge(CLK_I) then + CYC_O <= '0'; + WE_O <= '0'; + SEL_O <= (others => '0'); + if RST_I = '1' then + ADDR_O <= (others => '0'); + DAT_O <= (others => '0'); + elsif dmem_mem_gnt = '1' then + CYC_O <= CYC_O_dmem; + ADDR_O <= ADDR_O_dmem; + DAT_O <= DAT_O_dmem; + WE_O <= WE_O_dmem; + SEL_O <= SEL_O_dmem; + elsif dcache_mem_gnt = '1' then + CYC_O <= CYC_O_dcache; + ADDR_O <= ADDR_O_dcache; + elsif icache_mem_gnt = '1' then + CYC_O <= CYC_O_icache; + ADDR_O <= ADDR_O_icache; + end if; + end if; + end process; + + MRDY_O <= '1'; + +-- ADDR_O <= ADDR_O_dcache when dcache_mem_gnt = '1' else +-- ADDR_O_icache when icache_mem_gnt = '1' else ADDR_O_dmem; +-- DAT_O <= DAT_O_dmem when dmem_mem_gnt = '1' else X"BEEFBABE"; +-- SEL_O <= SEL_O_dmem when dmem_mem_gnt = '1' else "0000"; +-- WE_O <= WE_O_dmem when dmem_mem_gnt = '1' else '0'; +-- STB_O <= STB_O_icache when icache_mem_gnt = '1' else +-- STB_O_dcache when dcache_mem_gnt = '1' else +-- STB_O_dmem when dmem_mem_gnt = '1' else '0'; +-- CYC_O <= CYC_O_icache when icache_mem_gnt = '1' else +-- CYC_O_dcache when dcache_mem_gnt = '1' else +-- CYC_O_dmem when dmem_mem_gnt = '1' else '0'; + + SRDY_I_icache <= SRDY_I when icache_mem_gnt = '1' else '0'; + SRDY_I_dcache <= SRDY_I when dcache_mem_gnt = '1' else '0'; + SRDY_I_dmem <= SRDY_I when dmem_mem_gnt = '1' else '0'; cpu_imem_rdy <= not icache_busy after 4.5 ns; -- cpu_imem_din <= imem_din; -- cpu_wait <= busy after 5.5 ns; - cpu_wait <= '0'; cpu_dmem_rdy <= not (dcache_busy1 or dcache_busy2) after 4.5 ns; inst_icache : icache @@ -160,20 +251,19 @@ inst_icache : icache ) PORT MAP ( - clk => clk, - rst => rst, + CLK_I => CLK_I, + RST_I => RST_I, + STB_O => STB_O_icache, + CYC_O => CYC_O_icache, + ADDR_O => ADDR_O_icache, + DAT_I => DAT_I, + ACK_I => ACK_I, + SRDY_I => SRDY_I_icache, en => '1', cpu_en => cpu_imem_en, cpu_addr => cpu_imem_addr, cpu_dout => cpu_imem_din, - cpu_busy => icache_busy, - mem_en => icache_mem_en, - mem_req => icache_mem_req, - mem_gnt => icache_mem_gnt, - mem_addr => icache_mem_addr, - mem_din => mem_din, - mem_valid => mem_valid, - mem_rdy => mem_rdy + cpu_busy => icache_busy ); inst_dcache : dcache @@ -184,8 +274,14 @@ inst_dcache : dcache ) PORT MAP ( - clk => clk, - rst => rst, + CLK_I => CLK_I, + RST_I => RST_I, + CYC_O => CYC_O_dcache, + STB_O => STB_O_dcache, + ADDR_O => ADDR_O_dcache, + DAT_I => DAT_I, + ACK_I => ACK_I, + SRDY_I => SRDY_I_dcache, en => dcached, cpu_en => dcache_en, cpu_r_wn => cpu_dmem_re, @@ -193,139 +289,160 @@ inst_dcache : dcache cpu_addr => cpu_dmem_addr, cpu_din => cpu_dmem_dout, cpu_dout => dcache_dout, - cpu_busy => dcache_busy2, - mem_req => dcache_mem_req, - mem_gnt => dcache_mem_gnt, - mem_en => dcache_mem_en, - mem_addr => dcache_mem_addr, - mem_din => mem_din, - mem_valid => mem_valid, - mem_rdy => mem_rdy + cpu_busy => dcache_busy2 ); dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0'; - cpu_dmem_din <= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns; + cpu_dmem_din <= DAT_I_dmem when dmem_mem_gnt = '1' else dcache_dout; dcache_en <= cpu_dmem_en and not dcache_busy1; -dcache_flags: - process(clk) +proc_busy: + process(CLK_I) begin - if rising_edge(clk) then - if rst = '1' then + if rising_edge(CLK_I) then + if RST_I = '1' then dcache_busy1 <= '0'; - else - duncached_access <= '0'; - if dmem_ack = '1' then - duncached_access <= '1'; - if dmem_re = '1' then - if mem_valid = '1' then - dcache_busy1 <= '0'; - end if; - else - dcache_busy1 <= '0'; - end if; - end if; - if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then - dcache_busy1 <= '1'; - if dcached = '1' and cpu_dmem_re = '1' then - dcache_busy1 <= '0'; - end if; - end if; - end if; + elsif ACK_I = '1' and dmem_mem_gnt = '1' then + dcache_busy1 <= '0'; + elsif cpu_dmem_en = '1' and ca_reg_en = '1' then + dcache_busy1 <= '1'; + end if; end if; end process; dcache_regs: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then - if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then - dmem_dout <= cpu_dmem_dout; - dmem_addr <= cpu_dmem_addr; - dmem_re <= cpu_dmem_re; - dmem_we <= cpu_dmem_we; + if rising_edge(CLK_I) then + if RST_I = '1' then + WE_O_dmem <= '0'; + SEL_O_dmem <= (others => '0'); + elsif cpu_dmem_en = '1' and ca_reg_en = '1' then + DAT_O_dmem <= cpu_dmem_dout; + ADDR_O_dmem <= cpu_dmem_addr; + WE_O_dmem <= not cpu_dmem_re; + SEL_O_dmem <= cpu_dmem_we; end if; end if; end process; dcache_data: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then - if rst = '1' then - dmem_din <= (others => '0'); - elsif dcache_busy1 = '1' and mem_valid = '1' then - dmem_din <= mem_din; + if rising_edge(CLK_I) then + if RST_I = '1' then + DAT_I_dmem <= (others => '0'); + elsif ACK_I = '1' and dmem_mem_gnt = '1' then + DAT_I_dmem <= DAT_I; end if; end if; end process; + +cpu_access_state_next: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + s_ca <= ca_init; + else + s_ca <= sn_ca; + end if; + end if; + end process; + +cpu_access_state: + process(s_ca, cpu_dmem_en, cpu_dmem_re, dcached, SRDY_I_dmem, ACK_I) + begin + + ca_reg_en <= '0'; + CYC_O_dmem <= '0'; + STB_O_dmem <= '0'; + sn_ca <= s_ca; + + case s_ca is + when ca_init => + sn_ca <= ca_ready; + + when ca_ready => + if cpu_dmem_en = '1' then + if dcached = '0' or cpu_dmem_re = '0' then + ca_reg_en <= '1'; + sn_ca <= ca_bus_access; + end if; + end if; + + when ca_bus_access => + CYC_O_dmem <= '1'; + if SRDY_I_dmem = '1' then + STB_O_dmem <= '1'; + sn_ca <= ca_bus_fin; + end if; + + when ca_bus_fin => + CYC_O_dmem <= '1'; + if ACK_I = '1' then + sn_ca <= ca_ready; +-- CYC_O_dmem <= '0'; + end if; + + when others => + sn_ca <= ca_ready; + end case; + + end process; + bus_state_next: - process(clk) + process(CLK_I) begin - if rising_edge(clk) then - if rst = '1' then + if rising_edge(CLK_I) then + if RST_I = '1' then s <= init; - elsif ce = '1' then + else s <= sn; end if; end if; end process; bus_state: - process(s, icache_mem_en, icache_mem_req, dcache_busy1, dcache_mem_req, dcache_mem_en, dmem_re, mem_rdy, mem_valid) + process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem) begin - imem_mem_out_en <= '0'; - dmem_mem_out_en <= '0'; - icache_mem_gnt <= '0'; - dcache_mem_gnt <= '0'; - dmem_ack <= '0'; - - sn <= s; + icache_mem_gnt <= '0'; + dcache_mem_gnt <= '0'; + dmem_mem_gnt <= '0'; + sn <= s; case s is when init => - if mem_rdy = '1' then - sn <= ready; - end if; + sn <= ready; when ready => - if dcache_busy1 = '1' then - if mem_rdy = '1' then - dmem_mem_out_en <= '1'; - if dmem_re = '0' then - sn <= d_bus_finish; - else - sn <= d_bus_access; - end if; - end if; - elsif icache_mem_req = '1' then + if CYC_O_dmem = '1' then + sn <= uncached_bus_access; + dmem_mem_gnt <= '1'; + elsif CYC_O_icache = '1' then sn <= i_cache_bus_access; - elsif dcache_mem_req = '1' then + icache_mem_gnt <= '1'; + elsif CYC_O_dcache = '1' then sn <= d_cache_bus_access; + dcache_mem_gnt <= '1'; end if; when i_cache_bus_access => icache_mem_gnt <= '1'; - if icache_mem_en = '1' then - imem_mem_out_en <= '1'; - elsif icache_mem_req = '0' then + if CYC_O_icache = '0' then sn <= ready; +-- icache_mem_gnt <= '0'; end if; when d_cache_bus_access => dcache_mem_gnt <= '1'; - if dcache_mem_en = '1' then - dmem_mem_out_en <= '1'; - elsif dcache_mem_req = '0' then + if CYC_O_dcache = '0' then sn <= ready; +-- dcache_mem_gnt <= '0'; end if; - when d_bus_access => - if mem_valid = '1' then - dmem_ack <= '1'; - sn <= ready; - end if; - when d_bus_finish => - if mem_rdy = '1' then - dmem_ack <= '1'; - sn <= ready; + when uncached_bus_access => + dmem_mem_gnt <= '1'; + if CYC_O_dmem = '0' then + sn <= ready; +-- dmem_mem_gnt <= '0'; end if; when others => sn <= ready; @@ -333,48 +450,6 @@ bus_state: end process; -bus_request: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - bus_req <= '0'; - elsif dmem_mem_out_en = '1' or imem_mem_out_en = '1' then - bus_req <= '1'; - elsif mem_rdy = '1' then - bus_req <= '0'; - end if; - end if; - end process; - -bus_out: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - mem_dout <= (others => '0'); - mem_addr <= (others => '0'); - mem_re <= '0'; - mem_we <= (others => '0'); - elsif dmem_mem_out_en = '1' then - if dcache_mem_gnt = '1' then - mem_addr <= dcache_mem_addr; - mem_re <= '1'; - mem_we <= (others => '0'); - else - mem_dout <= dmem_dout; - mem_addr <= dmem_addr; - mem_re <= dmem_re; - mem_we <= dmem_we; - end if; - elsif imem_mem_out_en = '1' then - mem_addr <= icache_mem_addr; - mem_re <= '1'; - mem_we <= (others => '0'); - end if; - end if; - end process; - ------------------------------------------------------------------- end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd index 3d25c3e..370060e 100644 --- a/lib/CPUs/MIPS/src/core/mips_top.vhd +++ b/lib/CPUs/MIPS/src/core/mips_top.vhd @@ -31,17 +31,19 @@ use work.mips_types.all; entity mips_top is Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - int : in unsigned (5 downto 0); - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_din : in unsigned (WORD_WIDTH-1 downto 0); - mem_dout : out unsigned (WORD_WIDTH-1 downto 0); - mem_addr : out unsigned (WORD_WIDTH-1 downto 0) + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + DAT_O : out word_t; + WE_O : out STD_LOGIC; + SEL_O : out unsigned(3 downto 0); + CYC_O : out STD_LOGIC; + STB_O : out STD_LOGIC; + MRDY_O : out STD_LOGIC; + INT : in unsigned (5 downto 0) ); end mips_top; @@ -67,7 +69,6 @@ architecture rtl of mips_top is dmem_dout : out word_t ); END COMPONENT; - signal halt : std_logic; signal imem_rdy : std_logic; signal imem_en : std_logic; signal imem_addr : word_t; @@ -80,13 +81,22 @@ architecture rtl of mips_top is signal dmem_din : word_t; signal dmem_we : unsigned(3 downto 0); + COMPONENT bui - Port + PORT ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - cpu_wait : out STD_LOGIC; + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + DAT_O : out word_t; + WE_O : out STD_LOGIC; + SEL_O : out unsigned(3 downto 0); + CYC_O : out STD_LOGIC; + STB_O : out STD_LOGIC; + MRDY_O : out STD_LOGIC; cpu_imem_rdy : out STD_LOGIC; cpu_imem_en : in STD_LOGIC; cpu_imem_addr : in word_t; @@ -95,17 +105,9 @@ architecture rtl of mips_top is cpu_dmem_en : in STD_LOGIC; cpu_dmem_re : in STD_LOGIC; cpu_dmem_we : in unsigned(3 downto 0); - cpu_dmem_addr : in word_t; - cpu_dmem_din : out word_t; cpu_dmem_dout : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_dout : out word_t; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_ce : out STD_LOGIC + cpu_dmem_din : out word_t; + cpu_dmem_addr : in word_t ); END COMPONENT; @@ -116,10 +118,10 @@ begin inst_pipeline: pipeline PORT MAP ( - rst => rst, - clk => clk, - halt => halt, - int => int, + rst => RST_I, + clk => CLK_I, + halt => '0', + int => INT, imem_rdy => imem_rdy, imem_en => imem_en, imem_addr => imem_addr, @@ -136,10 +138,18 @@ inst_pipeline: pipeline inst_bui: bui PORT MAP ( - rst => rst, - clk => clk, - ce => '1', - cpu_wait => halt, + RST_I => RST_I, + CLK_I => CLK_I, + ACK_I => ACK_I, + SRDY_I => SRDY_I, + ADDR_O => ADDR_O, + DAT_I => DAT_I, + DAT_O => DAT_O, + WE_O => WE_O, + SEL_O => SEL_O, + CYC_O => CYC_O, + STB_O => STB_O, + MRDY_O => MRDY_O, cpu_imem_rdy => imem_rdy, cpu_imem_en => imem_en, cpu_imem_addr => imem_addr, @@ -150,15 +160,7 @@ inst_bui: bui cpu_dmem_we => dmem_we, cpu_dmem_addr => dmem_addr, cpu_dmem_din => dmem_din, - cpu_dmem_dout => dmem_dout, - mem_valid => mem_valid, - mem_rdy => mem_rdy, - mem_addr => mem_addr, - mem_din => mem_din, - mem_dout => mem_dout, - mem_re => mem_re, - mem_we => mem_we, - mem_ce => mem_en + cpu_dmem_dout => dmem_dout ); end rtl; diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys.prj b/projects/mips_sys/ise92/mips_sys/mips_sys.prj index 16bb313..02ef212 100644 --- a/projects/mips_sys/ise92/mips_sys/mips_sys.prj +++ b/projects/mips_sys/ise92/mips_sys/mips_sys.prj @@ -6,14 +6,16 @@ vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd" vhdl work "../../../../lib/misc/dpram_1w1r_dist.vhd" vhdl work "../../../../lib/misc/dpram_1w1r.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd" +vhdl work "../../../../lib/uart/kcuart_tx.vhd" +vhdl work "../../../../lib/uart/kcuart_rx.vhd" +vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd" @@ -23,17 +25,21 @@ vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/icache.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/dcache.vhd" -vhdl work "../../../../lib/uart/kcuart_tx.vhd" -vhdl work "../../../../lib/uart/kcuart_rx.vhd" -vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd" -vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd" -vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd" +vhdl work "../../src/sys_types.vhd" vhdl work "../../src/ram_ld.vhd" vhdl work "../../src/bootloader.ROM_ld.vhd" vhdl work "../../../../lib/uart/uart_tx.vhd" vhdl work "../../../../lib/uart/uart_rx.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd" +vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd" +vhdl work "../../src/rom_wb.vhd" +vhdl work "../../src/ram_wb.vhd" +vhdl work "../../src/gpio_wb.vhd" +vhdl work "../../../../lib/uart/uart_wb.vhd" vhdl work "../../../../lib/misc/lcd_port.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd" +vhdl work "../../../../lib/misc/clockgen_virtex4.vhd" +vhdl work "../../../../lib/misc/async_port_wb.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd" vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd" vhdl work "../../src/mips_sys.vhd" diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj index 01957df..8f1056a 100644 --- a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj +++ b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj @@ -6,14 +6,16 @@ vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd" vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd" vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd" vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd" vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd" +vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" +vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" +vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\fifo_sync.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd" @@ -23,17 +25,21 @@ vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" -vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd" vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd" vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd" vhdl work "W:\vhdl\lib\uart\uart_tx.vhd" vhdl work "W:\vhdl\lib\uart\uart_rx.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd" +vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\rom_wb.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\ram_wb.vhd" +vhdl work "W:\vhdl\projects\mips_sys\src\gpio_wb.vhd" +vhdl work "W:\vhdl\lib\uart\uart_wb.vhd" vhdl work "W:\vhdl\lib\misc\lcd_port.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_frontend.vhd" +vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd" +vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd" +vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd" vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd" vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd" diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo index 0aab37b..7e0fe04 100644 --- a/projects/mips_sys/sim/tb_mips_sys.fdo +++ b/projects/mips_sys/sim/tb_mips_sys.fdo @@ -8,9 +8,9 @@ vcom -explicit -93 "../src/sdram_config_sim.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd" # RAMs vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd" @@ -32,6 +32,8 @@ vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bui.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd" vcom -explicit -93 "../src/ram_sim.vhd" vcom -explicit -93 "../src/bootloader.ROM.vhd" +vcom -explicit -93 "../src/ram_wb.vhd" +vcom -explicit -93 "../src/rom_wb.vhd" # UART vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd" @@ -39,23 +41,31 @@ vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd" vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd" vcom -explicit -93 "../../../lib/uart/uart_rx.vhd" vcom -explicit -93 "../../../lib/uart/uart_tx.vhd" +vcom -explicit -93 "../../../lib/uart/uart_wb.vhd" + +# GPIO +vcom -explicit -93 "../src/gpio_wb.vhd" # LCD vcom -explicit -93 "../../../lib/misc/lcd_port.vhd" +# Flash and USB +vcom -explicit -93 "../src/sys_types.vhd" +vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd" + # FIFOS vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd" # SDRAM -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd" +vcom -explicit -93 "../../../lib/misc/clockgen_virtex4.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" +vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd" # Top and TB vcom -explicit -93 "../src/mips_sys_sim.vhd" diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo index bd8db46..3e37d0f 100644 --- a/projects/mips_sys/sim/tb_mips_sys.wdo +++ b/projects/mips_sys/sim/tb_mips_sys.wdo @@ -13,6 +13,7 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw add wave -noupdate -format Logic /tb_mips_sys/refresh +add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q @@ -26,12 +27,61 @@ add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_a_q add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_data add wave -noupdate -format Literal /tb_mips_sys/sys_error -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb +add wave -noupdate -format Logic /tb_mips_sys/uut/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o +add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o +add wave -noupdate -format Logic /tb_mips_sys/uut/we_o +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o +add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o +add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i +add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i +add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o +add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area +add wave -noupdate -divider BUI +add wave -noupdate -format Logic /tb_mips_sys/uut/clk +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s_ca +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2 +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1 +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval +add wave -noupdate -format Literal -label .addr -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.addr +add wave -noupdate -format Literal -label .dout -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.dout +add wave -noupdate -format Logic -label .en -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.en +add wave -noupdate -format Logic -label .re -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.re +add wave -noupdate -format Literal -label .we -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr +add wave -noupdate -divider USB +add wave -noupdate -format Logic /tb_mips_sys/uut/clk +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s +add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op +add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a +add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn +add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn +add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn +add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s +add wave -noupdate -divider Flash +add wave -noupdate -format Logic /tb_mips_sys/uut/clk +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_d +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_a +add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce +add wave -noupdate -format Logic /tb_mips_sys/sys_flash_wrn +add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rdn +add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rstn add wave -noupdate -divider {MIPS TOP} +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_wait add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause @@ -45,18 +95,15 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/in add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we -add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in -add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we -add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem +add wave -noupdate -format Logic /tb_mips_sys/uut/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit @@ -67,55 +114,21 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1 -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2 -add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk -add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/rst -add wave -noupdate -divider BUI -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_req -add wave -noupdate -format Logic /tb_mips_sys/uut/mem_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_addr -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_req -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dmem_ack -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dmem_valid -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_rdy -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s -add wave -noupdate -divider {Memory Bus} -add wave -noupdate -format Logic /tb_mips_sys/uut/mem_en -add wave -noupdate -format Logic /tb_mips_sys/uut/mem_re -add wave -noupdate -format Logic /tb_mips_sys/uut/mem_re_r -add wave -noupdate -format Literal /tb_mips_sys/uut/mem_we_r -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_re -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_ce -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_dout -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_valid -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/mem_rdy -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/busy -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend/r_wn add wave -noupdate -divider {CPU DMEM} -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/contention -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en @@ -125,7 +138,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr add wave -noupdate -divider {CPU IMEM} -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din @@ -136,16 +149,9 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_user_rom_en add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_user_rom_addr add wave -noupdate -divider UUT +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_buf_in -add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_busy_q -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_udata_in -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sdr_udata_out_q -add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_udata_req_wr -add wave -noupdate -format Logic /tb_mips_sys/uut/sdr_udata_vld_q -add wave -noupdate -format Literal /tb_mips_sys/uut/st add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn @@ -159,15 +165,12 @@ add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn -add wave -noupdate -format Literal /tb_mips_sys/uut/tick_usec add wave -noupdate -divider I-Cache +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_wait add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/clk add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en @@ -177,13 +180,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_ic add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_req -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_gnt -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_din -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_valid -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_rdy add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we @@ -191,6 +187,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write add wave -noupdate -divider D-Cache +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_r_wn add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we @@ -198,13 +195,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_req -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_gnt -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_din -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_valid -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_rdy add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_read_miss add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_write_miss @@ -224,9 +214,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/duncached_access TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1165623518 ps} 0} +WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1129563255 ps} 0} configure wave -namecolwidth 218 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -240,4 +229,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {1165509887 ps} {1165713125 ps} +WaveRestoreZoom {1129448646 ps} {1129766075 ps} diff --git a/projects/mips_sys/src/bootloader.ROM.vhd b/projects/mips_sys/src/bootloader.ROM.vhd index 649d39c..02a0f4e 100644 --- a/projects/mips_sys/src/bootloader.ROM.vhd +++ b/projects/mips_sys/src/bootloader.ROM.vhd @@ -132,8 +132,8 @@ ARCHITECTURE data OF rom IS X"00000000", -- 000001B8 X"03400008", -- 000001BC X"42000010", -- 000001C0 - X"3C1AA000", -- 000001C4 - X"275A0009", -- 000001C8 + X"3C1AA001", -- 000001C4 + X"275A0008", -- 000001C8 X"241B000D", -- 000001CC X"A35B0000", -- 000001D0 X"3C1DBFD0", -- 000001D4 @@ -297,7 +297,7 @@ ARCHITECTURE data OF rom IS X"241BFFFB", -- 0000044C X"035BD02A", -- 00000450 X"3C1ABFC0", -- 00000454 - X"275A0F4C", -- 00000458 + X"275A0F2C", -- 00000458 X"0340F809", -- 0000045C X"00000000", -- 00000460 X"0BF00118", -- 00000464 @@ -321,1280 +321,1280 @@ ARCHITECTURE data OF rom IS X"27BDFFF0", -- 000004AC X"AFBE000C", -- 000004B0 X"03A0F021", -- 000004B4 - X"3C02A000", -- 000004B8 - X"34420008", -- 000004BC + X"3C02A001", -- 000004B8 + X"34420004", -- 000004BC X"AFC20004", -- 000004C0 - X"3C02A000", -- 000004C4 - X"34420004", -- 000004C8 - X"AFC20000", -- 000004CC - X"8FC20004", -- 000004D0 - X"00000000", -- 000004D4 - X"90420000", -- 000004D8 - X"00000000", -- 000004DC - X"00021600", -- 000004E0 - X"00021603", -- 000004E4 - X"304200FF", -- 000004E8 - X"30420010", -- 000004EC - X"1040FFF7", -- 000004F0 + X"3C02A001", -- 000004C4 + X"AFC20000", -- 000004C8 + X"8FC20004", -- 000004CC + X"00000000", -- 000004D0 + X"8C420000", -- 000004D4 + X"00000000", -- 000004D8 + X"30420010", -- 000004DC + X"1040FFFA", -- 000004E0 + X"00000000", -- 000004E4 + X"8FC20000", -- 000004E8 + X"00000000", -- 000004EC + X"8C420000", -- 000004F0 X"00000000", -- 000004F4 - X"8FC20000", -- 000004F8 - X"00000000", -- 000004FC - X"90420000", -- 00000500 - X"00000000", -- 00000504 - X"00021600", -- 00000508 - X"00021603", -- 0000050C - X"03C0E821", -- 00000510 - X"8FBE000C", -- 00000514 - X"27BD0010", -- 00000518 - X"03E00008", -- 0000051C - X"00000000", -- 00000520 - X"27BDFFE8", -- 00000524 - X"AFBE0014", -- 00000528 - X"03A0F021", -- 0000052C - X"00801021", -- 00000530 - X"A3C20008", -- 00000534 - X"3C02A000", -- 00000538 - X"34420008", -- 0000053C - X"AFC20004", -- 00000540 - X"3C02A000", -- 00000544 - X"34420004", -- 00000548 - X"AFC20000", -- 0000054C - X"8FC20004", -- 00000550 + X"00021600", -- 000004F8 + X"00021603", -- 000004FC + X"03C0E821", -- 00000500 + X"8FBE000C", -- 00000504 + X"27BD0010", -- 00000508 + X"03E00008", -- 0000050C + X"00000000", -- 00000510 + X"27BDFFE8", -- 00000514 + X"AFBE0014", -- 00000518 + X"03A0F021", -- 0000051C + X"00801021", -- 00000520 + X"A3C20008", -- 00000524 + X"3C02A001", -- 00000528 + X"34420004", -- 0000052C + X"AFC20004", -- 00000530 + X"3C02A001", -- 00000534 + X"AFC20000", -- 00000538 + X"8FC20004", -- 0000053C + X"00000000", -- 00000540 + X"8C420000", -- 00000544 + X"00000000", -- 00000548 + X"30420002", -- 0000054C + X"1440FFFA", -- 00000550 X"00000000", -- 00000554 - X"90420000", -- 00000558 - X"00000000", -- 0000055C - X"00021600", -- 00000560 - X"00021603", -- 00000564 - X"304200FF", -- 00000568 - X"30420002", -- 0000056C - X"1440FFF7", -- 00000570 - X"00000000", -- 00000574 - X"8FC30000", -- 00000578 - X"93C20008", -- 0000057C - X"00000000", -- 00000580 - X"A0620000", -- 00000584 - X"03C0E821", -- 00000588 - X"8FBE0014", -- 0000058C - X"27BD0018", -- 00000590 - X"03E00008", -- 00000594 - X"00000000", -- 00000598 - X"27BDFFF0", -- 0000059C - X"AFBF000C", -- 000005A0 - X"AFBE0008", -- 000005A4 - X"03A0F021", -- 000005A8 - X"00801021", -- 000005AC - X"A3C20000", -- 000005B0 - X"83C30000", -- 000005B4 - X"2402000A", -- 000005B8 - X"1462000B", -- 000005BC + X"83C30008", -- 00000558 + X"8FC20000", -- 0000055C + X"00000000", -- 00000560 + X"AC430000", -- 00000564 + X"03C0E821", -- 00000568 + X"8FBE0014", -- 0000056C + X"27BD0018", -- 00000570 + X"03E00008", -- 00000574 + X"00000000", -- 00000578 + X"27BDFFF0", -- 0000057C + X"AFBF000C", -- 00000580 + X"AFBE0008", -- 00000584 + X"03A0F021", -- 00000588 + X"00801021", -- 0000058C + X"A3C20000", -- 00000590 + X"83C30000", -- 00000594 + X"2402000A", -- 00000598 + X"1462000B", -- 0000059C + X"00000000", -- 000005A0 + X"2404000D", -- 000005A4 + X"0FF00145", -- 000005A8 + X"00000000", -- 000005AC + X"83C20000", -- 000005B0 + X"00000000", -- 000005B4 + X"00402021", -- 000005B8 + X"0FF00145", -- 000005BC X"00000000", -- 000005C0 - X"2404000D", -- 000005C4 - X"0FF00149", -- 000005C8 - X"00000000", -- 000005CC - X"83C20000", -- 000005D0 - X"00000000", -- 000005D4 - X"00402021", -- 000005D8 - X"0FF00149", -- 000005DC - X"00000000", -- 000005E0 - X"0BF00180", -- 000005E4 - X"00000000", -- 000005E8 - X"83C20000", -- 000005EC - X"00000000", -- 000005F0 - X"00402021", -- 000005F4 - X"0FF00149", -- 000005F8 - X"00000000", -- 000005FC - X"03C0E821", -- 00000600 - X"8FBF000C", -- 00000604 - X"8FBE0008", -- 00000608 - X"27BD0010", -- 0000060C - X"03E00008", -- 00000610 - X"00000000", -- 00000614 - X"27BDFFE8", -- 00000618 - X"AFBF0014", -- 0000061C - X"AFBE0010", -- 00000620 - X"03A0F021", -- 00000624 - X"AFC40008", -- 00000628 - X"8FC20008", -- 0000062C - X"00000000", -- 00000630 - X"AFC20000", -- 00000634 - X"0BF0019C", -- 00000638 - X"00000000", -- 0000063C - X"8FC20008", -- 00000640 - X"00000000", -- 00000644 - X"80420000", -- 00000648 + X"0BF00178", -- 000005C4 + X"00000000", -- 000005C8 + X"83C20000", -- 000005CC + X"00000000", -- 000005D0 + X"00402021", -- 000005D4 + X"0FF00145", -- 000005D8 + X"00000000", -- 000005DC + X"03C0E821", -- 000005E0 + X"8FBF000C", -- 000005E4 + X"8FBE0008", -- 000005E8 + X"27BD0010", -- 000005EC + X"03E00008", -- 000005F0 + X"00000000", -- 000005F4 + X"27BDFFE8", -- 000005F8 + X"AFBF0014", -- 000005FC + X"AFBE0010", -- 00000600 + X"03A0F021", -- 00000604 + X"AFC40008", -- 00000608 + X"8FC20008", -- 0000060C + X"00000000", -- 00000610 + X"AFC20000", -- 00000614 + X"0BF00194", -- 00000618 + X"00000000", -- 0000061C + X"8FC20008", -- 00000620 + X"00000000", -- 00000624 + X"80420000", -- 00000628 + X"00000000", -- 0000062C + X"00401821", -- 00000630 + X"8FC20008", -- 00000634 + X"00000000", -- 00000638 + X"24420001", -- 0000063C + X"AFC20008", -- 00000640 + X"00602021", -- 00000644 + X"0FF0015F", -- 00000648 X"00000000", -- 0000064C - X"00401821", -- 00000650 - X"8FC20008", -- 00000654 - X"00000000", -- 00000658 - X"24420001", -- 0000065C - X"AFC20008", -- 00000660 - X"00602021", -- 00000664 - X"0FF00167", -- 00000668 - X"00000000", -- 0000066C - X"8FC20008", -- 00000670 - X"00000000", -- 00000674 - X"80420000", -- 00000678 - X"00000000", -- 0000067C - X"1440FFEF", -- 00000680 - X"00000000", -- 00000684 - X"8FC30008", -- 00000688 - X"8FC20000", -- 0000068C - X"00000000", -- 00000690 - X"00621023", -- 00000694 - X"03C0E821", -- 00000698 - X"8FBF0014", -- 0000069C - X"8FBE0010", -- 000006A0 - X"27BD0018", -- 000006A4 - X"03E00008", -- 000006A8 - X"00000000", -- 000006AC - X"27BDFFE8", -- 000006B0 - X"AFBF0014", -- 000006B4 - X"AFBE0010", -- 000006B8 - X"03A0F021", -- 000006BC - X"00801021", -- 000006C0 - X"A3C20008", -- 000006C4 - X"AFC00004", -- 000006C8 - X"0BF001D5", -- 000006CC - X"00000000", -- 000006D0 - X"93C20008", -- 000006D4 + X"8FC20008", -- 00000650 + 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X"00000000", -- 00001500 + X"10400007", -- 00001504 + X"00000000", -- 00001508 + X"3C02BFC0", -- 0000150C + X"2444180C", -- 00001510 + X"0FF0017E", -- 00001514 + X"00000000", -- 00001518 + X"0BF0054D", -- 0000151C + X"00000000", -- 00001520 + X"3C02BFC0", -- 00001524 + X"24441818", -- 00001528 + X"0FF0017E", -- 0000152C + X"00000000", -- 00001530 + X"AFC0002C", -- 00001534 + X"0BF0055B", -- 00001538 X"00000000", -- 0000153C - X"8FC3001C", -- 00001540 - X"24020001", -- 00001544 - X"AC620000", -- 00001548 - X"8FC2012C", -- 0000154C + X"8FC2002C", -- 00001540 + X"00000000", -- 00001544 + X"00021880", -- 00001548 + X"8FC20004", -- 0000154C X"00000000", -- 00001550 - X"00402021", -- 00001554 - X"0FF001E0", -- 00001558 - X"00000000", -- 0000155C - X"3C02BFC0", -- 00001560 - X"2444171C", -- 00001564 - X"0FF00186", -- 00001568 - X"00000000", -- 0000156C - X"8FC20020", -- 00001570 - X"00000000", -- 00001574 - X"2442FFFC", -- 00001578 - X"00402021", -- 0000157C - X"0FF001E0", -- 00001580 - X"00000000", -- 00001584 - X"3C02BFC0", -- 00001588 - X"24441724", -- 0000158C - X"0FF00186", -- 00001590 - X"00000000", -- 00001594 - X"8FC2012C", -- 00001598 - X"00000000", -- 0000159C - X"00402021", -- 000015A0 - X"0FF00360", -- 000015A4 - X"00000000", -- 000015A8 - X"8FC20028", -- 000015AC - X"00000000", -- 000015B0 - X"1440FF97", -- 000015B4 + X"00431021", -- 00001554 + X"AC400000", -- 00001558 + X"8FC2002C", -- 0000155C + X"00000000", -- 00001560 + X"24420001", -- 00001564 + X"AFC2002C", -- 00001568 + X"8FC2002C", -- 0000156C + X"3C030004", -- 00001570 + X"0043102A", -- 00001574 + X"1440FFF1", -- 00001578 + X"00000000", -- 0000157C + X"8FC40000", -- 00001580 + X"0FF0017E", -- 00001584 + X"00000000", -- 00001588 + X"27C20034", -- 0000158C + X"00402021", -- 00001590 + X"0FF00328", -- 00001594 + X"00000000", -- 00001598 + X"AFC20030", -- 0000159C + X"27C20134", -- 000015A0 + X"27C30034", -- 000015A4 + X"00402021", -- 000015A8 + X"00602821", -- 000015AC + X"8FC60030", -- 000015B0 + X"0FF00234", -- 000015B4 X"00000000", -- 000015B8 - X"8FC3001C", -- 000015BC - X"3C024000", -- 000015C0 - X"AC620000", -- 000015C4 - X"0BF00502", -- 000015C8 - X"00000000", -- 000015CC - X"61766E69", -- 000015D0 - X"0064696C", -- 000015D4 - X"30303252", -- 000015D8 - X"00000030", -- 000015DC - X"30303352", -- 000015E0 - X"00000030", -- 000015E4 - X"30303652", -- 000015E8 - X"00000030", -- 000015EC - X"30303452", -- 000015F0 - X"00000030", -- 000015F4 - X"65736572", -- 000015F8 - X"64657672", -- 000015FC - X"00000000", -- 00001600 - X"30303652", -- 00001604 - X"00004130", -- 00001608 - X"74617453", -- 0000160C - X"20207375", -- 00001610 - X"0000203A", -- 00001614 - X"0000000A", -- 00001618 - X"20555043", -- 0000161C - X"65707974", -- 00001620 - X"0000203A", -- 00001624 - X"76655220", -- 00001628 - X"0000002E", -- 0000162C - X"6E6B6E55", -- 00001630 - X"006E776F", -- 00001634 - X"746F6F42", -- 00001638 - X"20746120", -- 0000163C - X"00000000", -- 00001640 - X"41524453", -- 00001644 - X"654D204D", -- 00001648 - X"79726F6D", -- 0000164C - X"73655420", -- 00001650 - X"000A0D74", -- 00001654 - X"74697257", -- 00001658 - X"38282065", -- 0000165C - X"7469422D", -- 00001660 - X"63636120", -- 00001664 - X"29737365", -- 00001668 - X"002E2E2E", -- 0000166C - X"656E6F64", -- 00001670 - X"00000A0D", -- 00001674 - X"69726556", -- 00001678 - X"28207966", -- 0000167C - X"69422D38", -- 00001680 - X"63612074", -- 00001684 - X"73736563", -- 00001688 - X"2E2E2E29", -- 0000168C - X"00000000", -- 00001690 - X"6C696166", -- 00001694 - X"0A0D6465", -- 00001698 - X"00000000", -- 0000169C - X"73736170", -- 000016A0 - X"0A0D6465", -- 000016A4 - X"00000000", -- 000016A8 - X"74697257", -- 000016AC - X"31282065", -- 000016B0 - X"69422D36", -- 000016B4 - X"63612074", -- 000016B8 - X"73736563", -- 000016BC - X"2E2E2E29", -- 000016C0 - X"00000000", -- 000016C4 - X"69726556", -- 000016C8 - X"28207966", -- 000016CC - X"422D3631", -- 000016D0 - X"61207469", -- 000016D4 - X"73656363", -- 000016D8 - X"2E2E2973", -- 000016DC - X"0000002E", -- 000016E0 - X"74697257", -- 000016E4 - X"33282065", -- 000016E8 - X"69422D32", -- 000016EC - X"63612074", -- 000016F0 - X"73736563", -- 000016F4 - X"2E2E2E29", -- 000016F8 + X"AFC20030", -- 000015BC + X"8FC20024", -- 000015C0 + X"00000000", -- 000015C4 + X"AC400000", -- 000015C8 + X"8FC20030", -- 000015CC + X"00000000", -- 000015D0 + X"AFC20150", -- 000015D4 + X"24020002", -- 000015D8 + X"8FC30150", -- 000015DC + X"00000000", -- 000015E0 + X"10620008", -- 000015E4 + X"00000000", -- 000015E8 + X"24020004", -- 000015EC + X"8FC30150", -- 000015F0 + X"00000000", -- 000015F4 + X"1062002F", -- 000015F8 + X"00000000", -- 000015FC + X"0BF005C9", -- 00001600 + X"00000000", -- 00001604 + X"8FC30134", -- 00001608 + X"8FC20138", -- 0000160C + X"00000000", -- 00001610 + X"00621821", -- 00001614 + X"8FC20028", -- 00001618 + X"00000000", -- 0000161C + X"0043102B", -- 00001620 + X"10400006", -- 00001624 + X"00000000", -- 00001628 + X"8FC20134", -- 0000162C + X"8FC30138", -- 00001630 + X"00000000", -- 00001634 + X"00431021", -- 00001638 + X"AFC20028", -- 0000163C + X"8FC20134", -- 00001640 + X"00000000", -- 00001644 + X"AFC20020", -- 00001648 + X"AFC0002C", -- 0000164C + X"0BF005A6", -- 00001650 + X"00000000", -- 00001654 + X"8FC30140", -- 00001658 + X"8FC2002C", -- 0000165C + X"00000000", -- 00001660 + X"00621021", -- 00001664 + X"90430000", -- 00001668 + X"8FC20020", -- 0000166C + X"00000000", -- 00001670 + X"A0430000", -- 00001674 + X"8FC20020", -- 00001678 + X"00000000", -- 0000167C + X"24420001", -- 00001680 + X"AFC20020", -- 00001684 + X"8FC2002C", -- 00001688 + X"00000000", -- 0000168C + X"24420001", -- 00001690 + X"AFC2002C", -- 00001694 + X"8FC2002C", -- 00001698 + X"8FC30138", -- 0000169C + X"00000000", -- 000016A0 + X"0043102B", -- 000016A4 + X"1440FFEB", -- 000016A8 + X"00000000", -- 000016AC + X"0BF005C9", -- 000016B0 + X"00000000", -- 000016B4 + X"8FC30024", -- 000016B8 + X"24020001", -- 000016BC + X"AC620000", -- 000016C0 + X"8FC20134", -- 000016C4 + X"00000000", -- 000016C8 + X"00402021", -- 000016CC + X"0FF001D8", -- 000016D0 + X"00000000", -- 000016D4 + X"3C02BFC0", -- 000016D8 + X"24441894", -- 000016DC + X"0FF0017E", -- 000016E0 + X"00000000", -- 000016E4 + X"8FC20028", -- 000016E8 + X"00000000", -- 000016EC + X"2442FFFC", -- 000016F0 + X"00402021", -- 000016F4 + X"0FF001D8", -- 000016F8 X"00000000", -- 000016FC - X"69726556", -- 00001700 - X"28207966", -- 00001704 - X"422D3233", -- 00001708 - X"61207469", -- 0000170C - X"73656363", -- 00001710 - X"2E2E2973", -- 00001714 - X"0000002E", -- 00001718 - X"206F7420", -- 0000171C + X"3C02BFC0", -- 00001700 + X"2444189C", -- 00001704 + X"0FF0017E", -- 00001708 + X"00000000", -- 0000170C + X"8FC20134", -- 00001710 + X"00000000", -- 00001714 + X"00402021", -- 00001718 + X"0FF00358", -- 0000171C X"00000000", -- 00001720 - X"00000A0D", -- 00001724 + X"8FC20030", -- 00001724 X"00000000", -- 00001728 - X"00000000", -- 0000172C + X"1440FF97", -- 0000172C X"00000000", -- 00001730 - X"00000000", -- 00001734 - X"00000000", -- 00001738 - X"00000000", -- 0000173C - X"00000000", -- 00001740 + X"8FC30024", -- 00001734 + X"3C024000", -- 00001738 + X"AC620000", -- 0000173C + X"0BF00560", -- 00001740 X"00000000", -- 00001744 - X"00000000", -- 00001748 - X"00000000", -- 0000174C - X"00000000", -- 00001750 - X"00000000", -- 00001754 - X"00000000", -- 00001758 - X"00000000", -- 0000175C - X"00000000", -- 00001760 - X"00000000", -- 00001764 - X"00000000", -- 00001768 - X"00000000", -- 0000176C - X"00000000", -- 00001770 - X"00000000", -- 00001774 + X"61766E69", -- 00001748 + X"0064696C", -- 0000174C + X"30303252", -- 00001750 + X"00000030", -- 00001754 + X"30303352", -- 00001758 + X"00000030", -- 0000175C + X"30303652", -- 00001760 + X"00000030", -- 00001764 + X"30303452", -- 00001768 + X"00000030", -- 0000176C + X"65736572", -- 00001770 + X"64657672", -- 00001774 X"00000000", -- 00001778 - X"00000000", -- 0000177C - X"00000000", -- 00001780 - X"00000000", -- 00001784 - X"00000000", -- 00001788 - X"00000000", -- 0000178C - X"00000000", -- 00001790 - X"00000000", -- 00001794 - X"00000000", -- 00001798 - X"00000000", -- 0000179C - X"00000000", -- 000017A0 - X"00000000", -- 000017A4 - X"00000000", -- 000017A8 - X"00000000", -- 000017AC - X"00000000", -- 000017B0 - X"00000000", -- 000017B4 + X"30303652", -- 0000177C + X"00004130", -- 00001780 + X"74617453", -- 00001784 + X"20207375", -- 00001788 + X"0000203A", -- 0000178C + X"0000000A", -- 00001790 + X"20555043", -- 00001794 + X"65707974", -- 00001798 + X"0000203A", -- 0000179C + X"76655220", -- 000017A0 + X"0000002E", -- 000017A4 + X"6E6B6E55", -- 000017A8 + X"006E776F", -- 000017AC + X"746F6F42", -- 000017B0 + X"20746120", -- 000017B4 X"00000000", -- 000017B8 - X"00000000", -- 000017BC - X"00000000", -- 000017C0 - X"00000000", -- 000017C4 - X"00000000", -- 000017C8 - X"00000000", -- 000017CC - X"00000000", -- 000017D0 - X"00000000", -- 000017D4 - X"00000000", -- 000017D8 - X"00000000", -- 000017DC - X"00000000", -- 000017E0 - X"00000000", -- 000017E4 - X"00000000", -- 000017E8 - X"00000000", -- 000017EC - X"00000000", -- 000017F0 - X"00000000", -- 000017F4 - X"00000000", -- 000017F8 - X"00000000", -- 000017FC - X"00000000", -- 00001800 - X"00000000", -- 00001804 + X"41524453", -- 000017BC + X"654D204D", -- 000017C0 + X"79726F6D", -- 000017C4 + X"73655420", -- 000017C8 + X"000A0D74", -- 000017CC + X"74697257", -- 000017D0 + X"38282065", -- 000017D4 + X"7469422D", -- 000017D8 + X"63636120", -- 000017DC + X"29737365", -- 000017E0 + X"002E2E2E", -- 000017E4 + X"656E6F64", -- 000017E8 + X"00000A0D", -- 000017EC + X"69726556", -- 000017F0 + X"28207966", -- 000017F4 + X"69422D38", -- 000017F8 + X"63612074", -- 000017FC + X"73736563", -- 00001800 + X"2E2E2E29", -- 00001804 X"00000000", -- 00001808 - X"00000000", -- 0000180C - X"00000000", -- 00001810 + X"6C696166", -- 0000180C + X"0A0D6465", -- 00001810 X"00000000", -- 00001814 - X"00000000", -- 00001818 - X"00000000", -- 0000181C + X"73736170", -- 00001818 + X"0A0D6465", -- 0000181C X"00000000", -- 00001820 - X"00000000", -- 00001824 - X"00000000", -- 00001828 - X"00000000", -- 0000182C - X"00000000", -- 00001830 - X"00000000", -- 00001834 - X"00000000", -- 00001838 + X"74697257", -- 00001824 + X"31282065", -- 00001828 + X"69422D36", -- 0000182C + X"63612074", -- 00001830 + X"73736563", -- 00001834 + X"2E2E2E29", -- 00001838 X"00000000", -- 0000183C - X"00000000", -- 00001840 - X"00000000", -- 00001844 - X"00000000", -- 00001848 - X"00000000", -- 0000184C - X"00000000", -- 00001850 - X"00000000", -- 00001854 - X"00000000", -- 00001858 - X"00000000", -- 0000185C - X"00000000", -- 00001860 - X"00000000", -- 00001864 - X"00000000", -- 00001868 - X"00000000", -- 0000186C - X"00000000", -- 00001870 + X"69726556", -- 00001840 + X"28207966", -- 00001844 + X"422D3631", -- 00001848 + X"61207469", -- 0000184C + X"73656363", -- 00001850 + X"2E2E2973", -- 00001854 + X"0000002E", -- 00001858 + X"74697257", -- 0000185C + X"33282065", -- 00001860 + X"69422D32", -- 00001864 + X"63612074", -- 00001868 + X"73736563", -- 0000186C + X"2E2E2E29", -- 00001870 X"00000000", -- 00001874 - X"00000000", -- 00001878 - X"00000000", -- 0000187C - X"00000000", -- 00001880 - X"00000000", -- 00001884 - X"00000000", -- 00001888 - X"00000000", -- 0000188C - X"00000000", -- 00001890 - X"00000000", -- 00001894 + X"69726556", -- 00001878 + X"28207966", -- 0000187C + X"422D3233", -- 00001880 + X"61207469", -- 00001884 + X"73656363", -- 00001888 + X"2E2E2973", -- 0000188C + X"0000002E", -- 00001890 + X"206F7420", -- 00001894 X"00000000", -- 00001898 - X"00000000", -- 0000189C + X"00000A0D", -- 0000189C X"00000000", -- 000018A0 X"00000000", -- 000018A4 X"00000000", -- 000018A8 diff --git a/projects/mips_sys/src/bootloader.ROM_ld.vhd b/projects/mips_sys/src/bootloader.ROM_ld.vhd index 1703855..bf18279 100644 --- a/projects/mips_sys/src/bootloader.ROM_ld.vhd +++ b/projects/mips_sys/src/bootloader.ROM_ld.vhd @@ -144,8 +144,8 @@ ARCHITECTURE data OF rom IS X"00000000", -- 000001B8 X"03400008", -- 000001BC X"42000010", -- 000001C0 - X"3C1AA000", -- 000001C4 - X"275A0009", -- 000001C8 + X"3C1AA001", -- 000001C4 + X"275A0008", -- 000001C8 X"241B000D", -- 000001CC X"A35B0000", -- 000001D0 X"3C1DBFD0", -- 000001D4 @@ -309,7 +309,7 @@ ARCHITECTURE data OF rom IS X"241BFFFB", -- 0000044C X"035BD02A", -- 00000450 X"3C1ABFC0", -- 00000454 - X"275A0F4C", -- 00000458 + X"275A0F2C", -- 00000458 X"0340F809", -- 0000045C X"00000000", -- 00000460 X"0BF00118", -- 00000464 @@ -333,1064 +333,1064 @@ ARCHITECTURE data OF rom IS X"27BDFFF0", -- 000004AC X"AFBE000C", -- 000004B0 X"03A0F021", -- 000004B4 - X"3C02A000", -- 000004B8 - X"34420008", -- 000004BC + X"3C02A001", -- 000004B8 + X"34420004", -- 000004BC X"AFC20004", -- 000004C0 - X"3C02A000", -- 000004C4 - X"34420004", -- 000004C8 - X"AFC20000", -- 000004CC - X"8FC20004", -- 000004D0 - X"00000000", -- 000004D4 - X"90420000", -- 000004D8 - X"00000000", -- 000004DC - X"00021600", -- 000004E0 - X"00021603", -- 000004E4 - X"304200FF", -- 000004E8 - X"30420010", -- 000004EC - X"1040FFF7", -- 000004F0 + X"3C02A001", -- 000004C4 + X"AFC20000", -- 000004C8 + X"8FC20004", -- 000004CC + X"00000000", -- 000004D0 + X"8C420000", -- 000004D4 + X"00000000", -- 000004D8 + X"30420010", -- 000004DC + X"1040FFFA", -- 000004E0 + X"00000000", -- 000004E4 + X"8FC20000", -- 000004E8 + X"00000000", -- 000004EC + X"8C420000", -- 000004F0 X"00000000", -- 000004F4 - X"8FC20000", -- 000004F8 - X"00000000", -- 000004FC - X"90420000", -- 00000500 - X"00000000", -- 00000504 - X"00021600", -- 00000508 - X"00021603", -- 0000050C - X"03C0E821", -- 00000510 - X"8FBE000C", -- 00000514 - X"27BD0010", -- 00000518 - X"03E00008", -- 0000051C - X"00000000", -- 00000520 - X"27BDFFE8", -- 00000524 - X"AFBE0014", -- 00000528 - X"03A0F021", -- 0000052C - X"00801021", -- 00000530 - X"A3C20008", -- 00000534 - X"3C02A000", -- 00000538 - X"34420008", -- 0000053C - X"AFC20004", -- 00000540 - X"3C02A000", -- 00000544 - X"34420004", -- 00000548 - X"AFC20000", -- 0000054C - X"8FC20004", -- 00000550 + X"00021600", -- 000004F8 + X"00021603", -- 000004FC + X"03C0E821", -- 00000500 + X"8FBE000C", -- 00000504 + X"27BD0010", -- 00000508 + X"03E00008", -- 0000050C + X"00000000", -- 00000510 + X"27BDFFE8", -- 00000514 + X"AFBE0014", -- 00000518 + X"03A0F021", -- 0000051C + X"00801021", -- 00000520 + X"A3C20008", -- 00000524 + X"3C02A001", -- 00000528 + X"34420004", -- 0000052C + X"AFC20004", -- 00000530 + X"3C02A001", -- 00000534 + X"AFC20000", -- 00000538 + X"8FC20004", -- 0000053C + X"00000000", -- 00000540 + X"8C420000", -- 00000544 + X"00000000", -- 00000548 + X"30420002", -- 0000054C + X"1440FFFA", -- 00000550 X"00000000", -- 00000554 - X"90420000", -- 00000558 - X"00000000", -- 0000055C - X"00021600", -- 00000560 - X"00021603", -- 00000564 - X"304200FF", -- 00000568 - X"30420002", -- 0000056C - X"1440FFF7", -- 00000570 - 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X"AFC20014", -- 00000F50 + X"3C02A002", -- 00000F54 + X"AFC20010", -- 00000F58 + X"3C024000", -- 00000F5C + X"AFC2000C", -- 00000F60 + X"3C024000", -- 00000F64 + X"AFC20008", -- 00000F68 X"3C024000", -- 00000F6C - X"AFC2000C", -- 00000F70 - X"3C024000", -- 00000F74 - X"AFC20008", -- 00000F78 - X"3C024000", -- 00000F7C - X"AFC20004", -- 00000F80 - X"3C02BFC0", -- 00000F84 - X"244215B8", -- 00000F88 - X"AFC20000", -- 00000F8C - X"8FC2001C", -- 00000F90 + X"AFC20004", -- 00000F70 + X"3C02BFC0", -- 00000F74 + X"244215B8", -- 00000F78 + X"AFC20000", -- 00000F7C + X"8FC20024", -- 00000F80 + X"00000000", -- 00000F84 + X"AC400000", -- 00000F88 + X"AFC00028", -- 00000F8C + X"0FF00367", -- 00000F90 X"00000000", -- 00000F94 - X"AC400000", -- 00000F98 - X"AFC00020", -- 00000F9C - X"0FF0036F", -- 00000FA0 + X"3C02BFC0", -- 00000F98 + X"244415C4", -- 00000F9C + X"0FF0017E", -- 00000FA0 X"00000000", -- 00000FA4 X"3C02BFC0", -- 00000FA8 - X"244415C4", -- 00000FAC - X"0FF00186", -- 00000FB0 + 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X"1440FFF0", -- 00001010 + X"24420001", -- 00000FEC + X"AFC2002C", -- 00000FF0 + X"8FC2002C", -- 00000FF4 + X"3C030010", -- 00000FF8 + X"0043102A", -- 00000FFC + X"1440FFF0", -- 00001000 + X"00000000", -- 00001004 + X"3C02BFC0", -- 00001008 + X"244415F0", -- 0000100C + X"0FF0017E", -- 00001010 X"00000000", -- 00001014 X"3C02BFC0", -- 00001018 - X"244415F0", -- 0000101C - X"0FF00186", -- 00001020 + X"244415F8", -- 0000101C + X"0FF0017E", -- 00001020 X"00000000", -- 00001024 - X"3C02BFC0", -- 00001028 - X"244415F8", -- 0000102C - X"0FF00186", -- 00001030 - X"00000000", -- 00001034 - X"3C02003F", -- 00001038 - X"3442FFFF", -- 0000103C - X"AFC20024", -- 00001040 - X"0BF00421", -- 00001044 - X"00000000", -- 00001048 - X"8FC30024", -- 0000104C - X"8FC2000C", -- 00001050 - X"00000000", -- 00001054 - X"00431021", -- 00001058 - X"90430000", -- 0000105C - X"8FC20024", -- 00001060 - X"00000000", -- 00001064 - X"304200FF", -- 00001068 - X"14620009", -- 0000106C + X"3C02000F", -- 00001028 + X"3442FFFF", -- 0000102C + X"AFC2002C", -- 00001030 + X"0BF0041F", -- 00001034 + X"00000000", -- 00001038 + X"8FC3002C", -- 0000103C + X"8FC2000C", -- 00001040 + X"00000000", -- 00001044 + X"00431021", -- 00001048 + X"90420000", -- 0000104C + X"00000000", -- 00001050 + X"304300FF", -- 00001054 + X"8FC2002C", -- 00001058 + X"00000000", -- 0000105C + X"304200FF", -- 00001060 + X"14620009", -- 00001064 + X"00000000", -- 00001068 + X"8FC2002C", -- 0000106C X"00000000", -- 00001070 - X"8FC20024", -- 00001074 - X"00000000", -- 00001078 - X"2442FFFF", -- 0000107C - X"AFC20024", -- 00001080 - X"8FC20024", -- 00001084 + X"2442FFFF", -- 00001074 + X"AFC2002C", -- 00001078 + X"8FC2002C", -- 0000107C + X"00000000", -- 00001080 + X"0441FFED", -- 00001084 X"00000000", -- 00001088 - X"0441FFEF", -- 0000108C + X"8FC2002C", -- 0000108C X"00000000", -- 00001090 - X"8FC20024", -- 00001094 - X"00000000", -- 00001098 - X"24420001", -- 0000109C - X"AFC20024", -- 000010A0 - X"8FC20024", -- 000010A4 + X"24420001", -- 00001094 + X"AFC2002C", -- 00001098 + X"8FC2002C", -- 0000109C + X"00000000", -- 000010A0 + X"10400007", -- 000010A4 X"00000000", -- 000010A8 - X"10400007", -- 000010AC - X"00000000", -- 000010B0 - X"3C02BFC0", -- 000010B4 - X"24441614", -- 000010B8 - X"0FF00186", -- 000010BC + X"3C02BFC0", -- 000010AC + X"24441614", -- 000010B0 + X"0FF0017E", -- 000010B4 + X"00000000", -- 000010B8 + X"0BF00435", -- 000010BC X"00000000", -- 000010C0 - X"0BF00437", -- 000010C4 - X"00000000", -- 000010C8 - X"3C02BFC0", -- 000010CC - X"24441620", -- 000010D0 - X"0FF00186", -- 000010D4 - X"00000000", -- 000010D8 - X"3C02BFC0", -- 000010DC - X"2444162C", -- 000010E0 - X"0FF00186", -- 000010E4 - X"00000000", -- 000010E8 - X"AFC00024", -- 000010EC - X"0BF0044C", -- 000010F0 + X"3C02BFC0", -- 000010C4 + X"24441620", -- 000010C8 + X"0FF0017E", -- 000010CC + X"00000000", -- 000010D0 + X"3C02BFC0", -- 000010D4 + X"2444162C", -- 000010D8 + X"0FF0017E", -- 000010DC + X"00000000", -- 000010E0 + X"AFC0002C", -- 000010E4 + X"0BF0044A", -- 000010E8 + X"00000000", -- 000010EC + X"8FC2002C", -- 000010F0 X"00000000", -- 000010F4 - X"8FC20024", -- 000010F8 - X"00000000", -- 000010FC - X"00021840", -- 00001100 - X"8FC20008", -- 00001104 - X"00000000", -- 00001108 - X"00431821", -- 0000110C - X"8FC20024", -- 00001110 - X"00000000", -- 00001114 - X"3042FFFF", -- 00001118 - X"A4620000", -- 0000111C - X"8FC20024", -- 00001120 - X"00000000", -- 00001124 - X"24420001", -- 00001128 - X"AFC20024", -- 0000112C - X"8FC20024", -- 00001130 - X"3C030020", -- 00001134 - X"0043102A", -- 00001138 - X"1440FFEE", -- 0000113C - X"00000000", -- 00001140 - X"3C02BFC0", -- 00001144 - X"244415F0", -- 00001148 - X"0FF00186", -- 0000114C - X"00000000", -- 00001150 - X"3C02BFC0", -- 00001154 - X"24441648", -- 00001158 - X"0FF00186", -- 0000115C - X"00000000", -- 00001160 - X"3C02001F", -- 00001164 - X"3442FFFF", -- 00001168 - X"AFC20024", -- 0000116C - X"0BF0046E", -- 00001170 + X"00021840", -- 000010F8 + X"8FC20008", -- 000010FC + X"00000000", -- 00001100 + X"00431821", -- 00001104 + X"8FC2002C", -- 00001108 + X"00000000", -- 0000110C + X"3042FFFF", -- 00001110 + X"A4620000", -- 00001114 + X"8FC2002C", -- 00001118 + X"00000000", -- 0000111C + X"24420001", -- 00001120 + X"AFC2002C", -- 00001124 + X"8FC2002C", -- 00001128 + X"3C030008", -- 0000112C + X"0043102A", -- 00001130 + X"1440FFEE", -- 00001134 + X"00000000", -- 00001138 + X"3C02BFC0", -- 0000113C + X"244415F0", -- 00001140 + X"0FF0017E", -- 00001144 + X"00000000", -- 00001148 + X"3C02BFC0", -- 0000114C + X"24441648", -- 00001150 + X"0FF0017E", -- 00001154 + X"00000000", -- 00001158 + X"3C020007", -- 0000115C + X"3442FFFF", -- 00001160 + X"AFC2002C", -- 00001164 + X"0BF0046E", -- 00001168 + X"00000000", -- 0000116C + X"8FC2002C", -- 00001170 X"00000000", -- 00001174 - X"8FC20024", -- 00001178 - X"00000000", -- 0000117C - X"00021840", -- 00001180 - X"8FC20008", -- 00001184 - X"00000000", -- 00001188 - X"00431021", -- 0000118C - X"94430000", -- 00001190 - X"8FC20024", -- 00001194 + X"00021840", -- 00001178 + X"8FC20008", -- 0000117C + X"00000000", -- 00001180 + X"00431021", -- 00001184 + X"94420000", -- 00001188 + X"00000000", -- 0000118C + X"3043FFFF", -- 00001190 + X"8FC2002C", -- 00001194 X"00000000", -- 00001198 X"3042FFFF", -- 0000119C X"14620009", -- 000011A0 X"00000000", -- 000011A4 - X"8FC20024", -- 000011A8 + X"8FC2002C", -- 000011A8 X"00000000", -- 000011AC X"2442FFFF", -- 000011B0 - X"AFC20024", -- 000011B4 - X"8FC20024", -- 000011B8 + X"AFC2002C", -- 000011B4 + X"8FC2002C", -- 000011B8 X"00000000", -- 000011BC - X"0441FFED", -- 000011C0 + X"0441FFEB", -- 000011C0 X"00000000", -- 000011C4 - X"8FC20024", -- 000011C8 + X"8FC2002C", -- 000011C8 X"00000000", -- 000011CC X"24420001", -- 000011D0 - X"AFC20024", -- 000011D4 - X"8FC20024", -- 000011D8 + X"AFC2002C", -- 000011D4 + X"8FC2002C", -- 000011D8 X"00000000", -- 000011DC X"10400007", -- 000011E0 X"00000000", -- 000011E4 X"3C02BFC0", -- 000011E8 X"24441614", -- 000011EC - X"0FF00186", -- 000011F0 + X"0FF0017E", -- 000011F0 X"00000000", -- 000011F4 X"0BF00484", -- 000011F8 X"00000000", -- 000011FC X"3C02BFC0", -- 00001200 X"24441620", -- 00001204 - X"0FF00186", -- 00001208 + X"0FF0017E", -- 00001208 X"00000000", -- 0000120C X"3C02BFC0", -- 00001210 X"24441664", -- 00001214 - X"0FF00186", -- 00001218 + X"0FF0017E", -- 00001218 X"00000000", -- 0000121C - X"AFC00024", -- 00001220 + X"AFC0002C", -- 00001220 X"0BF00498", -- 00001224 X"00000000", -- 00001228 - X"8FC20024", -- 0000122C + X"8FC2002C", -- 0000122C X"00000000", -- 00001230 X"00021880", -- 00001234 X"8FC20004", -- 00001238 X"00000000", -- 0000123C X"00431821", -- 00001240 - X"8FC20024", -- 00001244 + X"8FC2002C", -- 00001244 X"00000000", -- 00001248 X"AC620000", -- 0000124C - X"8FC20024", -- 00001250 + X"8FC2002C", -- 00001250 X"00000000", -- 00001254 X"24420001", -- 00001258 - X"AFC20024", -- 0000125C - X"8FC20024", -- 00001260 - X"3C030010", -- 00001264 + X"AFC2002C", -- 0000125C + X"8FC2002C", -- 00001260 + X"3C030004", -- 00001264 X"0043102A", -- 00001268 X"1440FFEF", -- 0000126C X"00000000", -- 00001270 X"3C02BFC0", -- 00001274 X"244415F0", -- 00001278 - X"0FF00186", -- 0000127C + X"0FF0017E", -- 0000127C X"00000000", -- 00001280 X"3C02BFC0", -- 00001284 X"24441680", -- 00001288 - X"0FF00186", -- 0000128C + X"0FF0017E", -- 0000128C X"00000000", -- 00001290 - X"3C02000F", -- 00001294 + X"3C020003", -- 00001294 X"3442FFFF", -- 00001298 - X"AFC20024", -- 0000129C + X"AFC2002C", -- 0000129C X"0BF004B9", -- 000012A0 X"00000000", -- 000012A4 - X"8FC20024", -- 000012A8 + X"8FC2002C", -- 000012A8 X"00000000", -- 000012AC X"00021880", -- 000012B0 X"8FC20004", -- 000012B4 X"00000000", -- 000012B8 X"00431021", -- 000012BC X"8C430000", -- 000012C0 - X"8FC20024", -- 000012C4 + X"8FC2002C", -- 000012C4 X"00000000", -- 000012C8 X"14620009", -- 000012CC X"00000000", -- 000012D0 - X"8FC20024", -- 000012D4 + X"8FC2002C", -- 000012D4 X"00000000", -- 000012D8 X"2442FFFF", -- 000012DC - X"AFC20024", -- 000012E0 - X"8FC20024", -- 000012E4 + X"AFC2002C", -- 000012E0 + X"8FC2002C", -- 000012E4 X"00000000", -- 000012E8 X"0441FFEE", -- 000012EC X"00000000", -- 000012F0 - X"8FC20024", -- 000012F4 + X"8FC2002C", -- 000012F4 X"00000000", -- 000012F8 X"24420001", -- 000012FC - X"AFC20024", -- 00001300 - X"8FC20024", -- 00001304 + X"AFC2002C", -- 00001300 + X"8FC2002C", -- 00001304 X"00000000", -- 00001308 X"10400007", -- 0000130C X"00000000", -- 00001310 X"3C02BFC0", -- 00001314 X"24441614", -- 00001318 - X"0FF00186", -- 0000131C + X"0FF0017E", -- 0000131C X"00000000", -- 00001320 X"0BF004CF", -- 00001324 X"00000000", -- 00001328 X"3C02BFC0", -- 0000132C X"24441620", -- 00001330 - X"0FF00186", -- 00001334 + X"0FF0017E", -- 00001334 X"00000000", -- 00001338 - X"AFC00024", -- 0000133C + X"AFC0002C", -- 0000133C X"0BF004DD", -- 00001340 X"00000000", -- 00001344 - X"8FC20024", -- 00001348 + X"8FC2002C", -- 00001348 X"00000000", -- 0000134C X"00021880", -- 00001350 X"8FC20004", -- 00001354 X"00000000", -- 00001358 X"00431021", -- 0000135C X"AC400000", -- 00001360 - X"8FC20024", -- 00001364 + X"8FC2002C", -- 00001364 X"00000000", -- 00001368 X"24420001", -- 0000136C - X"AFC20024", -- 00001370 - X"8FC20024", -- 00001374 - X"3C030010", -- 00001378 + X"AFC2002C", -- 00001370 + X"8FC2002C", -- 00001374 + X"3C030004", -- 00001378 X"0043102A", -- 0000137C X"1440FFF1", -- 00001380 X"00000000", -- 00001384 X"8FC40000", -- 00001388 - X"0FF00186", -- 0000138C + X"0FF0017E", -- 0000138C X"00000000", -- 00001390 - X"27C2002C", -- 00001394 + X"27C20034", -- 00001394 X"00402021", -- 00001398 - X"0FF00330", -- 0000139C + X"0FF00328", -- 0000139C X"00000000", -- 000013A0 - X"AFC20028", -- 000013A4 - X"27C2012C", -- 000013A8 - X"27C3002C", -- 000013AC + X"AFC20030", -- 000013A4 + X"27C20134", -- 000013A8 + X"27C30034", -- 000013AC X"00402021", -- 000013B0 X"00602821", -- 000013B4 - X"8FC60028", -- 000013B8 - X"0FF0023C", -- 000013BC + X"8FC60030", -- 000013B8 + X"0FF00234", -- 000013BC X"00000000", -- 000013C0 - X"AFC20028", -- 000013C4 - X"8FC2001C", -- 000013C8 + X"AFC20030", -- 000013C4 + X"8FC20024", -- 000013C8 X"00000000", -- 000013CC X"AC400000", -- 000013D0 - X"8FC20028", -- 000013D4 + X"8FC20030", -- 000013D4 X"00000000", -- 000013D8 - X"AFC20148", -- 000013DC + X"AFC20150", -- 000013DC X"24020002", -- 000013E0 - X"8FC30148", -- 000013E4 + X"8FC30150", -- 000013E4 X"00000000", -- 000013E8 X"10620008", -- 000013EC X"00000000", -- 000013F0 X"24020004", -- 000013F4 - X"8FC30148", -- 000013F8 + X"8FC30150", -- 000013F8 X"00000000", -- 000013FC X"1062002F", -- 00001400 X"00000000", -- 00001404 X"0BF0054B", -- 00001408 X"00000000", -- 0000140C - X"8FC3012C", -- 00001410 - X"8FC20130", -- 00001414 + X"8FC30134", -- 00001410 + X"8FC20138", -- 00001414 X"00000000", -- 00001418 X"00621821", -- 0000141C - X"8FC20020", -- 00001420 + X"8FC20028", -- 00001420 X"00000000", -- 00001424 X"0043102B", -- 00001428 X"10400006", -- 0000142C X"00000000", -- 00001430 - X"8FC2012C", -- 00001434 - X"8FC30130", -- 00001438 + X"8FC20134", -- 00001434 + X"8FC30138", -- 00001438 X"00000000", -- 0000143C X"00431021", -- 00001440 - X"AFC20020", -- 00001444 - X"8FC2012C", -- 00001448 + X"AFC20028", -- 00001444 + X"8FC20134", -- 00001448 X"00000000", -- 0000144C - X"AFC20018", -- 00001450 - X"AFC00024", -- 00001454 + X"AFC20020", -- 00001450 + X"AFC0002C", -- 00001454 X"0BF00528", -- 00001458 X"00000000", -- 0000145C - X"8FC30138", -- 00001460 - X"8FC20024", -- 00001464 + X"8FC30140", -- 00001460 + X"8FC2002C", -- 00001464 X"00000000", -- 00001468 X"00621021", -- 0000146C X"90430000", -- 00001470 - X"8FC20018", -- 00001474 + X"8FC20020", -- 00001474 X"00000000", -- 00001478 X"A0430000", -- 0000147C - X"8FC20018", -- 00001480 + X"8FC20020", -- 00001480 X"00000000", -- 00001484 X"24420001", -- 00001488 - X"AFC20018", -- 0000148C - X"8FC20024", -- 00001490 + X"AFC20020", -- 0000148C + X"8FC2002C", -- 00001490 X"00000000", -- 00001494 X"24420001", -- 00001498 - X"AFC20024", -- 0000149C - X"8FC20024", -- 000014A0 - X"8FC30130", -- 000014A4 + X"AFC2002C", -- 0000149C + X"8FC2002C", -- 000014A0 + X"8FC30138", -- 000014A4 X"00000000", -- 000014A8 X"0043102B", -- 000014AC X"1440FFEB", -- 000014B0 X"00000000", -- 000014B4 X"0BF0054B", -- 000014B8 X"00000000", -- 000014BC - X"8FC3001C", -- 000014C0 + X"8FC30024", -- 000014C0 X"24020001", -- 000014C4 X"AC620000", -- 000014C8 - X"8FC2012C", -- 000014CC + X"8FC20134", -- 000014CC X"00000000", -- 000014D0 X"00402021", -- 000014D4 - X"0FF001E0", -- 000014D8 + X"0FF001D8", -- 000014D8 X"00000000", -- 000014DC X"3C02BFC0", -- 000014E0 X"2444169C", -- 000014E4 - X"0FF00186", -- 000014E8 + X"0FF0017E", -- 000014E8 X"00000000", -- 000014EC - X"8FC20020", -- 000014F0 + X"8FC20028", -- 000014F0 X"00000000", -- 000014F4 X"2442FFFC", -- 000014F8 X"00402021", -- 000014FC - X"0FF001E0", -- 00001500 + X"0FF001D8", -- 00001500 X"00000000", -- 00001504 X"3C02BFC0", -- 00001508 X"244416A4", -- 0000150C - X"0FF00186", -- 00001510 + X"0FF0017E", -- 00001510 X"00000000", -- 00001514 - X"8FC2012C", -- 00001518 + X"8FC20134", -- 00001518 X"00000000", -- 0000151C X"00402021", -- 00001520 - X"0FF00360", -- 00001524 + X"0FF00358", -- 00001524 X"00000000", -- 00001528 - X"8FC20028", -- 0000152C + X"8FC20030", -- 0000152C X"00000000", -- 00001530 X"1440FF97", -- 00001534 X"00000000", -- 00001538 - X"8FC3001C", -- 0000153C + X"8FC30024", -- 0000153C X"3C024000", -- 00001540 X"AC620000", -- 00001544 X"0BF004E2", -- 00001548 diff --git a/projects/mips_sys/src/bootloader.dis b/projects/mips_sys/src/bootloader.dis index 64136b6..db10543 100644 --- a/projects/mips_sys/src/bootloader.dis +++ b/projects/mips_sys/src/bootloader.dis @@ -39,7 +39,7 @@ bfc001c0: 42000010 rfe Disassembly of section .text: bfc001c4 <_init>: -bfc001c4: 3c1aa000 275a0009 241b000d a35b0000 ...<..Z'...$..[. +bfc001c4: 3c1aa001 275a0008 241b000d a35b0000 ...<..Z'...$..[. bfc001d4: 3c1dbfd0 27bdfff0 241a0005 1340009f ...<...'...$..@. bfc001e4: 241afffb 1340009d 241a0000 13400003 ...$..@....$..@. bfc001f4: 00000000 0bf00118 00000000 241a0005 ...............$ @@ -80,7 +80,7 @@ bfc00414: 035bd02a 241afffb 241bfffa 035bd02a *.[....$...$*.[. bfc00424: 241a0006 241b0005 035bd02a 241a0006 ...$...$*.[....$ bfc00434: 241bfffb 035bd02a 241afffa 241b0005 ...$*.[....$...$ bfc00444: 035bd02a 241afffa 241bfffb 035bd02a *.[....$...$*.[. -bfc00454: 3c1abfc0 275a0f4c 0340f809 ...: bfc00460: 00000000 nop @@ -111,1119 +111,1209 @@ bfc004ac : bfc004ac: 27bdfff0 addiu sp,sp,-16 bfc004b0: afbe000c sw s8,12(sp) bfc004b4: 03a0f021 move s8,sp -bfc004b8: 3c02a000 lui v0,0xa000 -bfc004bc: 34420008 ori v0,v0,0x8 +bfc004b8: 3c02a001 lui v0,0xa001 +bfc004bc: 34420004 ori v0,v0,0x4 bfc004c0: afc20004 sw v0,4(s8) -bfc004c4: 3c02a000 lui v0,0xa000 -bfc004c8: 34420004 ori v0,v0,0x4 -bfc004cc: afc20000 sw v0,0(s8) -bfc004d0: 8fc20004 lw v0,4(s8) -bfc004d4: 00000000 nop -bfc004d8: 90420000 lbu v0,0(v0) -bfc004dc: 00000000 nop -bfc004e0: 00021600 sll v0,v0,0x18 -bfc004e4: 00021603 sra v0,v0,0x18 -bfc004e8: 304200ff andi v0,v0,0xff -bfc004ec: 30420010 andi v0,v0,0x10 -bfc004f0: 1040fff7 beqz v0,bfc004d0 +bfc004c4: 3c02a001 lui v0,0xa001 +bfc004c8: afc20000 sw v0,0(s8) +bfc004cc: 8fc20004 lw v0,4(s8) +bfc004d0: 00000000 nop +bfc004d4: 8c420000 lw v0,0(v0) +bfc004d8: 00000000 nop +bfc004dc: 30420010 andi v0,v0,0x10 +bfc004e0: 1040fffa beqz v0,bfc004cc +bfc004e4: 00000000 nop +bfc004e8: 8fc20000 lw v0,0(s8) +bfc004ec: 00000000 nop +bfc004f0: 8c420000 lw v0,0(v0) bfc004f4: 00000000 nop -bfc004f8: 8fc20000 lw v0,0(s8) -bfc004fc: 00000000 nop -bfc00500: 90420000 lbu v0,0(v0) -bfc00504: 00000000 nop -bfc00508: 00021600 sll v0,v0,0x18 -bfc0050c: 00021603 sra v0,v0,0x18 -bfc00510: 03c0e821 move sp,s8 -bfc00514: 8fbe000c lw s8,12(sp) -bfc00518: 27bd0010 addiu sp,sp,16 -bfc0051c: 03e00008 jr ra -bfc00520: 00000000 nop +bfc004f8: 00021600 sll v0,v0,0x18 +bfc004fc: 00021603 sra v0,v0,0x18 +bfc00500: 03c0e821 move sp,s8 +bfc00504: 8fbe000c lw s8,12(sp) +bfc00508: 27bd0010 addiu sp,sp,16 +bfc0050c: 03e00008 jr ra +bfc00510: 00000000 nop -bfc00524 : -bfc00524: 27bdffe8 addiu sp,sp,-24 -bfc00528: afbe0014 sw s8,20(sp) -bfc0052c: 03a0f021 move s8,sp -bfc00530: 00801021 move v0,a0 -bfc00534: a3c20008 sb v0,8(s8) -bfc00538: 3c02a000 lui v0,0xa000 -bfc0053c: 34420008 ori v0,v0,0x8 -bfc00540: afc20004 sw v0,4(s8) -bfc00544: 3c02a000 lui v0,0xa000 -bfc00548: 34420004 ori v0,v0,0x4 -bfc0054c: afc20000 sw v0,0(s8) -bfc00550: 8fc20004 lw v0,4(s8) +bfc00514 : +bfc00514: 27bdffe8 addiu sp,sp,-24 +bfc00518: afbe0014 sw s8,20(sp) +bfc0051c: 03a0f021 move s8,sp +bfc00520: 00801021 move v0,a0 +bfc00524: a3c20008 sb v0,8(s8) +bfc00528: 3c02a001 lui v0,0xa001 +bfc0052c: 34420004 ori v0,v0,0x4 +bfc00530: afc20004 sw v0,4(s8) +bfc00534: 3c02a001 lui v0,0xa001 +bfc00538: afc20000 sw v0,0(s8) +bfc0053c: 8fc20004 lw v0,4(s8) +bfc00540: 00000000 nop +bfc00544: 8c420000 lw v0,0(v0) +bfc00548: 00000000 nop +bfc0054c: 30420002 andi v0,v0,0x2 +bfc00550: 1440fffa bnez v0,bfc0053c bfc00554: 00000000 nop -bfc00558: 90420000 lbu v0,0(v0) -bfc0055c: 00000000 nop -bfc00560: 00021600 sll v0,v0,0x18 -bfc00564: 00021603 sra v0,v0,0x18 -bfc00568: 304200ff andi v0,v0,0xff -bfc0056c: 30420002 andi v0,v0,0x2 -bfc00570: 1440fff7 bnez v0,bfc00550 -bfc00574: 00000000 nop -bfc00578: 8fc30000 lw v1,0(s8) -bfc0057c: 93c20008 lbu v0,8(s8) -bfc00580: 00000000 nop -bfc00584: a0620000 sb v0,0(v1) -bfc00588: 03c0e821 move sp,s8 -bfc0058c: 8fbe0014 lw s8,20(sp) -bfc00590: 27bd0018 addiu sp,sp,24 -bfc00594: 03e00008 jr ra -bfc00598: 00000000 nop +bfc00558: 83c30008 lb v1,8(s8) +bfc0055c: 8fc20000 lw v0,0(s8) +bfc00560: 00000000 nop +bfc00564: ac430000 sw v1,0(v0) +bfc00568: 03c0e821 move sp,s8 +bfc0056c: 8fbe0014 lw s8,20(sp) +bfc00570: 27bd0018 addiu sp,sp,24 +bfc00574: 03e00008 jr ra +bfc00578: 00000000 nop -bfc0059c <_putchar>: -bfc0059c: 27bdfff0 addiu sp,sp,-16 -bfc005a0: afbf000c sw ra,12(sp) -bfc005a4: afbe0008 sw s8,8(sp) -bfc005a8: 03a0f021 move s8,sp -bfc005ac: 00801021 move v0,a0 -bfc005b0: a3c20000 sb v0,0(s8) -bfc005b4: 83c30000 lb v1,0(s8) -bfc005b8: 2402000a li v0,10 -bfc005bc: 1462000b bne v1,v0,bfc005ec <_putchar+0x50> +bfc0057c <_putchar>: +bfc0057c: 27bdfff0 addiu sp,sp,-16 +bfc00580: afbf000c sw ra,12(sp) +bfc00584: afbe0008 sw s8,8(sp) +bfc00588: 03a0f021 move s8,sp +bfc0058c: 00801021 move v0,a0 +bfc00590: a3c20000 sb v0,0(s8) +bfc00594: 83c30000 lb v1,0(s8) +bfc00598: 2402000a li v0,10 +bfc0059c: 1462000b bne v1,v0,bfc005cc <_putchar+0x50> +bfc005a0: 00000000 nop +bfc005a4: 2404000d li a0,13 +bfc005a8: 0ff00145 jal bfc00514 +bfc005ac: 00000000 nop +bfc005b0: 83c20000 lb v0,0(s8) +bfc005b4: 00000000 nop +bfc005b8: 00402021 move a0,v0 +bfc005bc: 0ff00145 jal bfc00514 bfc005c0: 00000000 nop -bfc005c4: 2404000d li a0,13 -bfc005c8: 0ff00149 jal bfc00524 -bfc005cc: 00000000 nop -bfc005d0: 83c20000 lb v0,0(s8) -bfc005d4: 00000000 nop -bfc005d8: 00402021 move a0,v0 -bfc005dc: 0ff00149 jal bfc00524 -bfc005e0: 00000000 nop -bfc005e4: 0bf00180 j bfc00600 <_putchar+0x64> -bfc005e8: 00000000 nop -bfc005ec: 83c20000 lb v0,0(s8) -bfc005f0: 00000000 nop -bfc005f4: 00402021 move a0,v0 -bfc005f8: 0ff00149 jal bfc00524 -bfc005fc: 00000000 nop -bfc00600: 03c0e821 move sp,s8 -bfc00604: 8fbf000c lw ra,12(sp) -bfc00608: 8fbe0008 lw s8,8(sp) -bfc0060c: 27bd0010 addiu sp,sp,16 -bfc00610: 03e00008 jr ra -bfc00614: 00000000 nop +bfc005c4: 0bf00178 j bfc005e0 <_putchar+0x64> +bfc005c8: 00000000 nop +bfc005cc: 83c20000 lb v0,0(s8) +bfc005d0: 00000000 nop +bfc005d4: 00402021 move a0,v0 +bfc005d8: 0ff00145 jal bfc00514 +bfc005dc: 00000000 nop +bfc005e0: 03c0e821 move sp,s8 +bfc005e4: 8fbf000c lw ra,12(sp) +bfc005e8: 8fbe0008 lw s8,8(sp) +bfc005ec: 27bd0010 addiu sp,sp,16 +bfc005f0: 03e00008 jr ra +bfc005f4: 00000000 nop -bfc00618 : -bfc00618: 27bdffe8 addiu sp,sp,-24 -bfc0061c: afbf0014 sw ra,20(sp) -bfc00620: afbe0010 sw s8,16(sp) -bfc00624: 03a0f021 move s8,sp -bfc00628: afc40008 sw a0,8(s8) -bfc0062c: 8fc20008 lw v0,8(s8) -bfc00630: 00000000 nop -bfc00634: afc20000 sw v0,0(s8) -bfc00638: 0bf0019c j bfc00670 -bfc0063c: 00000000 nop -bfc00640: 8fc20008 lw v0,8(s8) -bfc00644: 00000000 nop -bfc00648: 80420000 lb v0,0(v0) +bfc005f8 : +bfc005f8: 27bdffe8 addiu sp,sp,-24 +bfc005fc: afbf0014 sw ra,20(sp) +bfc00600: afbe0010 sw s8,16(sp) +bfc00604: 03a0f021 move s8,sp +bfc00608: afc40008 sw a0,8(s8) +bfc0060c: 8fc20008 lw v0,8(s8) +bfc00610: 00000000 nop +bfc00614: afc20000 sw v0,0(s8) +bfc00618: 0bf00194 j bfc00650 +bfc0061c: 00000000 nop +bfc00620: 8fc20008 lw v0,8(s8) +bfc00624: 00000000 nop +bfc00628: 80420000 lb v0,0(v0) +bfc0062c: 00000000 nop +bfc00630: 00401821 move v1,v0 +bfc00634: 8fc20008 lw v0,8(s8) +bfc00638: 00000000 nop +bfc0063c: 24420001 addiu v0,v0,1 +bfc00640: afc20008 sw v0,8(s8) +bfc00644: 00602021 move a0,v1 +bfc00648: 0ff0015f jal bfc0057c <_putchar> bfc0064c: 00000000 nop -bfc00650: 00401821 move v1,v0 -bfc00654: 8fc20008 lw v0,8(s8) -bfc00658: 00000000 nop -bfc0065c: 24420001 addiu v0,v0,1 -bfc00660: afc20008 sw v0,8(s8) -bfc00664: 00602021 move a0,v1 -bfc00668: 0ff00167 jal bfc0059c <_putchar> -bfc0066c: 00000000 nop -bfc00670: 8fc20008 lw v0,8(s8) -bfc00674: 00000000 nop -bfc00678: 80420000 lb v0,0(v0) -bfc0067c: 00000000 nop -bfc00680: 1440ffef bnez v0,bfc00640 -bfc00684: 00000000 nop -bfc00688: 8fc30008 lw v1,8(s8) -bfc0068c: 8fc20000 lw v0,0(s8) -bfc00690: 00000000 nop -bfc00694: 00621023 subu v0,v1,v0 -bfc00698: 03c0e821 move sp,s8 -bfc0069c: 8fbf0014 lw ra,20(sp) -bfc006a0: 8fbe0010 lw s8,16(sp) -bfc006a4: 27bd0018 addiu sp,sp,24 -bfc006a8: 03e00008 jr ra -bfc006ac: 00000000 nop +bfc00650: 8fc20008 lw v0,8(s8) +bfc00654: 00000000 nop +bfc00658: 80420000 lb v0,0(v0) +bfc0065c: 00000000 nop +bfc00660: 1440ffef bnez v0,bfc00620 +bfc00664: 00000000 nop +bfc00668: 8fc30008 lw v1,8(s8) +bfc0066c: 8fc20000 lw v0,0(s8) +bfc00670: 00000000 nop +bfc00674: 00621023 subu v0,v1,v0 +bfc00678: 03c0e821 move sp,s8 +bfc0067c: 8fbf0014 lw ra,20(sp) +bfc00680: 8fbe0010 lw s8,16(sp) +bfc00684: 27bd0018 addiu sp,sp,24 +bfc00688: 03e00008 jr ra +bfc0068c: 00000000 nop -bfc006b0 : -bfc006b0: 27bdffe8 addiu sp,sp,-24 -bfc006b4: afbf0014 sw ra,20(sp) -bfc006b8: afbe0010 sw s8,16(sp) -bfc006bc: 03a0f021 move s8,sp -bfc006c0: 00801021 move v0,a0 -bfc006c4: a3c20008 sb v0,8(s8) -bfc006c8: afc00004 sw zero,4(s8) -bfc006cc: 0bf001d5 j bfc00754 -bfc006d0: 00000000 nop -bfc006d4: 93c20008 lbu v0,8(s8) +bfc00690 : +bfc00690: 27bdffe8 addiu sp,sp,-24 +bfc00694: afbf0014 sw ra,20(sp) +bfc00698: afbe0010 sw s8,16(sp) +bfc0069c: 03a0f021 move s8,sp +bfc006a0: 00801021 move v0,a0 +bfc006a4: a3c20008 sb v0,8(s8) +bfc006a8: afc00004 sw zero,4(s8) +bfc006ac: 0bf001cd j bfc00734 +bfc006b0: 00000000 nop +bfc006b4: 93c20008 lbu v0,8(s8) +bfc006b8: 00000000 nop +bfc006bc: 00021102 srl v0,v0,0x4 +bfc006c0: a3c20000 sb v0,0(s8) +bfc006c4: 83c20008 lb v0,8(s8) +bfc006c8: 00000000 nop +bfc006cc: 00021100 sll v0,v0,0x4 +bfc006d0: a3c20008 sb v0,8(s8) +bfc006d4: 93c20000 lbu v0,0(s8) bfc006d8: 00000000 nop -bfc006dc: 00021102 srl v0,v0,0x4 -bfc006e0: a3c20000 sb v0,0(s8) -bfc006e4: 83c20008 lb v0,8(s8) -bfc006e8: 00000000 nop -bfc006ec: 00021100 sll v0,v0,0x4 -bfc006f0: a3c20008 sb v0,8(s8) -bfc006f4: 93c20000 lbu v0,0(s8) -bfc006f8: 00000000 nop -bfc006fc: 2c42000a sltiu v0,v0,10 -bfc00700: 10400007 beqz v0,bfc00720 +bfc006dc: 2c42000a sltiu v0,v0,10 +bfc006e0: 10400007 beqz v0,bfc00700 +bfc006e4: 00000000 nop +bfc006e8: 93c20000 lbu v0,0(s8) +bfc006ec: 00000000 nop +bfc006f0: 24420030 addiu v0,v0,48 +bfc006f4: a3c20001 sb v0,1(s8) +bfc006f8: 0bf001c4 j bfc00710 +bfc006fc: 00000000 nop +bfc00700: 93c20000 lbu v0,0(s8) bfc00704: 00000000 nop -bfc00708: 93c20000 lbu v0,0(s8) -bfc0070c: 00000000 nop -bfc00710: 24420030 addiu v0,v0,48 -bfc00714: a3c20001 sb v0,1(s8) -bfc00718: 0bf001cc j bfc00730 -bfc0071c: 00000000 nop -bfc00720: 93c20000 lbu v0,0(s8) -bfc00724: 00000000 nop -bfc00728: 24420037 addiu v0,v0,55 -bfc0072c: a3c20001 sb v0,1(s8) -bfc00730: 83c20001 lb v0,1(s8) -bfc00734: 00000000 nop -bfc00738: 00402021 move a0,v0 -bfc0073c: 0ff00149 jal bfc00524 -bfc00740: 00000000 nop -bfc00744: 8fc20004 lw v0,4(s8) -bfc00748: 00000000 nop -bfc0074c: 24420001 addiu v0,v0,1 -bfc00750: afc20004 sw v0,4(s8) -bfc00754: 8fc20004 lw v0,4(s8) -bfc00758: 00000000 nop -bfc0075c: 28420002 slti v0,v0,2 -bfc00760: 1440ffdc bnez v0,bfc006d4 -bfc00764: 00000000 nop -bfc00768: 03c0e821 move sp,s8 -bfc0076c: 8fbf0014 lw ra,20(sp) -bfc00770: 8fbe0010 lw s8,16(sp) -bfc00774: 27bd0018 addiu sp,sp,24 -bfc00778: 03e00008 jr ra +bfc00708: 24420037 addiu v0,v0,55 +bfc0070c: a3c20001 sb v0,1(s8) +bfc00710: 83c20001 lb v0,1(s8) +bfc00714: 00000000 nop +bfc00718: 00402021 move a0,v0 +bfc0071c: 0ff00145 jal bfc00514 +bfc00720: 00000000 nop +bfc00724: 8fc20004 lw v0,4(s8) +bfc00728: 00000000 nop +bfc0072c: 24420001 addiu v0,v0,1 +bfc00730: afc20004 sw v0,4(s8) +bfc00734: 8fc20004 lw v0,4(s8) +bfc00738: 00000000 nop +bfc0073c: 28420002 slti v0,v0,2 +bfc00740: 1440ffdc bnez v0,bfc006b4 +bfc00744: 00000000 nop +bfc00748: 03c0e821 move sp,s8 +bfc0074c: 8fbf0014 lw ra,20(sp) +bfc00750: 8fbe0010 lw s8,16(sp) +bfc00754: 27bd0018 addiu sp,sp,24 +bfc00758: 03e00008 jr ra +bfc0075c: 00000000 nop + +bfc00760 : +bfc00760: 27bdffe8 addiu sp,sp,-24 +bfc00764: afbf0014 sw ra,20(sp) +bfc00768: afbe0010 sw s8,16(sp) +bfc0076c: 03a0f021 move s8,sp +bfc00770: afc40008 sw a0,8(s8) +bfc00774: afc00004 sw zero,4(s8) +bfc00778: 0bf001f1 j bfc007c4 bfc0077c: 00000000 nop - -bfc00780 : -bfc00780: 27bdffe8 addiu sp,sp,-24 -bfc00784: afbf0014 sw ra,20(sp) -bfc00788: afbe0010 sw s8,16(sp) -bfc0078c: 03a0f021 move s8,sp -bfc00790: afc40008 sw a0,8(s8) -bfc00794: afc00004 sw zero,4(s8) -bfc00798: 0bf001f9 j bfc007e4 -bfc0079c: 00000000 nop -bfc007a0: 8fc20008 lw v0,8(s8) -bfc007a4: 00000000 nop -bfc007a8: 00021603 sra v0,v0,0x18 -bfc007ac: a3c20001 sb v0,1(s8) -bfc007b0: 83c20001 lb v0,1(s8) -bfc007b4: 00000000 nop -bfc007b8: 00402021 move a0,v0 -bfc007bc: 0ff001ac jal bfc006b0 -bfc007c0: 00000000 nop -bfc007c4: 8fc20008 lw v0,8(s8) +bfc00780: 8fc20008 lw v0,8(s8) +bfc00784: 00000000 nop +bfc00788: 00021603 sra v0,v0,0x18 +bfc0078c: a3c20001 sb v0,1(s8) +bfc00790: 83c20001 lb v0,1(s8) +bfc00794: 00000000 nop +bfc00798: 00402021 move a0,v0 +bfc0079c: 0ff001a4 jal bfc00690 +bfc007a0: 00000000 nop +bfc007a4: 8fc20008 lw v0,8(s8) +bfc007a8: 00000000 nop +bfc007ac: 00021200 sll v0,v0,0x8 +bfc007b0: afc20008 sw v0,8(s8) +bfc007b4: 8fc20004 lw v0,4(s8) +bfc007b8: 00000000 nop +bfc007bc: 24420001 addiu v0,v0,1 +bfc007c0: afc20004 sw v0,4(s8) +bfc007c4: 8fc20004 lw v0,4(s8) bfc007c8: 00000000 nop -bfc007cc: 00021200 sll v0,v0,0x8 -bfc007d0: afc20008 sw v0,8(s8) -bfc007d4: 8fc20004 lw v0,4(s8) -bfc007d8: 00000000 nop -bfc007dc: 24420001 addiu v0,v0,1 -bfc007e0: afc20004 sw v0,4(s8) -bfc007e4: 8fc20004 lw v0,4(s8) -bfc007e8: 00000000 nop -bfc007ec: 28420004 slti v0,v0,4 -bfc007f0: 1440ffeb bnez v0,bfc007a0 -bfc007f4: 00000000 nop -bfc007f8: 03c0e821 move sp,s8 -bfc007fc: 8fbf0014 lw ra,20(sp) -bfc00800: 8fbe0010 lw s8,16(sp) -bfc00804: 27bd0018 addiu sp,sp,24 -bfc00808: 03e00008 jr ra +bfc007cc: 28420004 slti v0,v0,4 +bfc007d0: 1440ffeb bnez v0,bfc00780 +bfc007d4: 00000000 nop +bfc007d8: 03c0e821 move sp,s8 +bfc007dc: 8fbf0014 lw ra,20(sp) +bfc007e0: 8fbe0010 lw s8,16(sp) +bfc007e4: 27bd0018 addiu sp,sp,24 +bfc007e8: 03e00008 jr ra +bfc007ec: 00000000 nop + +bfc007f0 : +bfc007f0: 27bdffe8 addiu sp,sp,-24 +bfc007f4: afbe0014 sw s8,20(sp) +bfc007f8: 03a0f021 move s8,sp +bfc007fc: afc40008 sw a0,8(s8) +bfc00800: a3c00000 sb zero,0(s8) +bfc00804: afc00004 sw zero,4(s8) +bfc00808: 0bf00229 j bfc008a4 bfc0080c: 00000000 nop - -bfc00810 : -bfc00810: 27bdffe8 addiu sp,sp,-24 -bfc00814: afbe0014 sw s8,20(sp) -bfc00818: 03a0f021 move s8,sp -bfc0081c: afc40008 sw a0,8(s8) -bfc00820: a3c00000 sb zero,0(s8) -bfc00824: afc00004 sw zero,4(s8) -bfc00828: 0bf00231 j bfc008c4 -bfc0082c: 00000000 nop -bfc00830: 8fc30004 lw v1,4(s8) -bfc00834: 8fc20008 lw v0,8(s8) -bfc00838: 00000000 nop -bfc0083c: 00431021 addu v0,v0,v1 -bfc00840: 90420000 lbu v0,0(v0) +bfc00810: 8fc30004 lw v1,4(s8) +bfc00814: 8fc20008 lw v0,8(s8) +bfc00818: 00000000 nop +bfc0081c: 00431021 addu v0,v0,v1 +bfc00820: 90420000 lbu v0,0(v0) +bfc00824: 00000000 nop +bfc00828: a3c20001 sb v0,1(s8) +bfc0082c: 93c20001 lbu v0,1(s8) +bfc00830: 00000000 nop +bfc00834: 2c420041 sltiu v0,v0,65 +bfc00838: 14400007 bnez v0,bfc00858 +bfc0083c: 00000000 nop +bfc00840: 93c20001 lbu v0,1(s8) bfc00844: 00000000 nop -bfc00848: a3c20001 sb v0,1(s8) -bfc0084c: 93c20001 lbu v0,1(s8) -bfc00850: 00000000 nop -bfc00854: 2c420041 sltiu v0,v0,65 -bfc00858: 14400007 bnez v0,bfc00878 +bfc00848: 2442ffc9 addiu v0,v0,-55 +bfc0084c: a3c20001 sb v0,1(s8) +bfc00850: 0bf0021a j bfc00868 +bfc00854: 00000000 nop +bfc00858: 93c20001 lbu v0,1(s8) bfc0085c: 00000000 nop -bfc00860: 93c20001 lbu v0,1(s8) -bfc00864: 00000000 nop -bfc00868: 2442ffc9 addiu v0,v0,-55 -bfc0086c: a3c20001 sb v0,1(s8) -bfc00870: 0bf00222 j bfc00888 -bfc00874: 00000000 nop -bfc00878: 93c20001 lbu v0,1(s8) -bfc0087c: 00000000 nop -bfc00880: 2442ffd0 addiu v0,v0,-48 -bfc00884: a3c20001 sb v0,1(s8) -bfc00888: 93c20000 lbu v0,0(s8) -bfc0088c: 00000000 nop -bfc00890: 00021100 sll v0,v0,0x4 -bfc00894: 00021e00 sll v1,v0,0x18 -bfc00898: 00031e03 sra v1,v1,0x18 -bfc0089c: 83c20001 lb v0,1(s8) -bfc008a0: 00000000 nop -bfc008a4: 00621025 or v0,v1,v0 -bfc008a8: 00021600 sll v0,v0,0x18 -bfc008ac: 00021603 sra v0,v0,0x18 -bfc008b0: a3c20000 sb v0,0(s8) -bfc008b4: 8fc20004 lw v0,4(s8) -bfc008b8: 00000000 nop -bfc008bc: 24420001 addiu v0,v0,1 -bfc008c0: afc20004 sw v0,4(s8) -bfc008c4: 8fc20004 lw v0,4(s8) -bfc008c8: 00000000 nop -bfc008cc: 28420002 slti v0,v0,2 -bfc008d0: 1440ffd7 bnez v0,bfc00830 -bfc008d4: 00000000 nop -bfc008d8: 93c20000 lbu v0,0(s8) -bfc008dc: 03c0e821 move sp,s8 -bfc008e0: 8fbe0014 lw s8,20(sp) -bfc008e4: 27bd0018 addiu sp,sp,24 -bfc008e8: 03e00008 jr ra -bfc008ec: 00000000 nop +bfc00860: 2442ffd0 addiu v0,v0,-48 +bfc00864: a3c20001 sb v0,1(s8) +bfc00868: 93c20000 lbu v0,0(s8) +bfc0086c: 00000000 nop +bfc00870: 00021100 sll v0,v0,0x4 +bfc00874: 00021e00 sll v1,v0,0x18 +bfc00878: 00031e03 sra v1,v1,0x18 +bfc0087c: 83c20001 lb v0,1(s8) +bfc00880: 00000000 nop +bfc00884: 00621025 or v0,v1,v0 +bfc00888: 00021600 sll v0,v0,0x18 +bfc0088c: 00021603 sra v0,v0,0x18 +bfc00890: a3c20000 sb v0,0(s8) +bfc00894: 8fc20004 lw v0,4(s8) +bfc00898: 00000000 nop +bfc0089c: 24420001 addiu v0,v0,1 +bfc008a0: afc20004 sw v0,4(s8) +bfc008a4: 8fc20004 lw v0,4(s8) +bfc008a8: 00000000 nop +bfc008ac: 28420002 slti v0,v0,2 +bfc008b0: 1440ffd7 bnez v0,bfc00810 +bfc008b4: 00000000 nop +bfc008b8: 93c20000 lbu v0,0(s8) +bfc008bc: 03c0e821 move sp,s8 +bfc008c0: 8fbe0014 lw s8,20(sp) +bfc008c4: 27bd0018 addiu sp,sp,24 +bfc008c8: 03e00008 jr ra +bfc008cc: 00000000 nop -bfc008f0 : -bfc008f0: 27bdffd8 addiu sp,sp,-40 -bfc008f4: afbf0024 sw ra,36(sp) -bfc008f8: afbe0020 sw s8,32(sp) -bfc008fc: 03a0f021 move s8,sp -bfc00900: afc40010 sw a0,16(s8) -bfc00904: afc50014 sw a1,20(s8) -bfc00908: afc60018 sw a2,24(s8) -bfc0090c: 8fc20018 lw v0,24(s8) -bfc00910: 00000000 nop -bfc00914: 14400004 bnez v0,bfc00928 -bfc00918: 00000000 nop -bfc0091c: afc0001c sw zero,28(s8) -bfc00920: 0bf00329 j bfc00ca4 -bfc00924: 00000000 nop -bfc00928: 8fc30010 lw v1,16(s8) -bfc0092c: 24020003 li v0,3 -bfc00930: ac620008 sw v0,8(v1) -bfc00934: afc00004 sw zero,4(s8) +bfc008d0 : +bfc008d0: 27bdffd8 addiu sp,sp,-40 +bfc008d4: afbf0024 sw ra,36(sp) +bfc008d8: afbe0020 sw s8,32(sp) +bfc008dc: 03a0f021 move s8,sp +bfc008e0: afc40010 sw a0,16(s8) +bfc008e4: afc50014 sw a1,20(s8) +bfc008e8: afc60018 sw a2,24(s8) +bfc008ec: 8fc20018 lw v0,24(s8) +bfc008f0: 00000000 nop +bfc008f4: 14400004 bnez v0,bfc00908 +bfc008f8: 00000000 nop +bfc008fc: afc0001c sw zero,28(s8) +bfc00900: 0bf00321 j bfc00c84 +bfc00904: 00000000 nop +bfc00908: 8fc30010 lw v1,16(s8) +bfc0090c: 24020003 li v0,3 +bfc00910: ac620008 sw v0,8(v1) +bfc00914: afc00004 sw zero,4(s8) +bfc00918: 8fc20014 lw v0,20(s8) +bfc0091c: 00000000 nop +bfc00920: 24420001 addiu v0,v0,1 +bfc00924: 90420000 lbu v0,0(v0) +bfc00928: 00000000 nop +bfc0092c: 2c420031 sltiu v0,v0,49 +bfc00930: 14400015 bnez v0,bfc00988 +bfc00934: 00000000 nop bfc00938: 8fc20014 lw v0,20(s8) bfc0093c: 00000000 nop bfc00940: 24420001 addiu v0,v0,1 bfc00944: 90420000 lbu v0,0(v0) bfc00948: 00000000 nop -bfc0094c: 2c420031 sltiu v0,v0,49 -bfc00950: 14400015 bnez v0,bfc009a8 +bfc0094c: 2c420034 sltiu v0,v0,52 +bfc00950: 1040000d beqz v0,bfc00988 bfc00954: 00000000 nop bfc00958: 8fc20014 lw v0,20(s8) bfc0095c: 00000000 nop bfc00960: 24420001 addiu v0,v0,1 bfc00964: 90420000 lbu v0,0(v0) bfc00968: 00000000 nop -bfc0096c: 2c420034 sltiu v0,v0,52 -bfc00970: 1040000d beqz v0,bfc009a8 -bfc00974: 00000000 nop -bfc00978: 8fc20014 lw v0,20(s8) -bfc0097c: 00000000 nop -bfc00980: 24420001 addiu v0,v0,1 -bfc00984: 90420000 lbu v0,0(v0) -bfc00988: 00000000 nop -bfc0098c: 2442ffd1 addiu v0,v0,-47 -bfc00990: afc20004 sw v0,4(s8) -bfc00994: 8fc30010 lw v1,16(s8) -bfc00998: 24020002 li v0,2 -bfc0099c: ac620008 sw v0,8(v1) -bfc009a0: 0bf00294 j bfc00a50 +bfc0096c: 2442ffd1 addiu v0,v0,-47 +bfc00970: afc20004 sw v0,4(s8) +bfc00974: 8fc30010 lw v1,16(s8) +bfc00978: 24020002 li v0,2 +bfc0097c: ac620008 sw v0,8(v1) +bfc00980: 0bf0028c j bfc00a30 +bfc00984: 00000000 nop +bfc00988: 8fc20014 lw v0,20(s8) +bfc0098c: 00000000 nop +bfc00990: 24420001 addiu v0,v0,1 +bfc00994: 90420000 lbu v0,0(v0) +bfc00998: 00000000 nop +bfc0099c: 2c420037 sltiu v0,v0,55 +bfc009a0: 14400017 bnez v0,bfc00a00 bfc009a4: 00000000 nop bfc009a8: 8fc20014 lw v0,20(s8) bfc009ac: 00000000 nop bfc009b0: 24420001 addiu v0,v0,1 bfc009b4: 90420000 lbu v0,0(v0) bfc009b8: 00000000 nop -bfc009bc: 2c420037 sltiu v0,v0,55 -bfc009c0: 14400017 bnez v0,bfc00a20 +bfc009bc: 2c42003a sltiu v0,v0,58 +bfc009c0: 1040000f beqz v0,bfc00a00 bfc009c4: 00000000 nop bfc009c8: 8fc20014 lw v0,20(s8) bfc009cc: 00000000 nop bfc009d0: 24420001 addiu v0,v0,1 bfc009d4: 90420000 lbu v0,0(v0) bfc009d8: 00000000 nop -bfc009dc: 2c42003a sltiu v0,v0,58 -bfc009e0: 1040000f beqz v0,bfc00a20 -bfc009e4: 00000000 nop -bfc009e8: 8fc20014 lw v0,20(s8) -bfc009ec: 00000000 nop -bfc009f0: 24420001 addiu v0,v0,1 -bfc009f4: 90420000 lbu v0,0(v0) -bfc009f8: 00000000 nop -bfc009fc: 00401821 move v1,v0 -bfc00a00: 2402003b li v0,59 -bfc00a04: 00431023 subu v0,v0,v1 -bfc00a08: afc20004 sw v0,4(s8) -bfc00a0c: 8fc30010 lw v1,16(s8) -bfc00a10: 24020004 li v0,4 -bfc00a14: ac620008 sw v0,8(v1) -bfc00a18: 0bf00294 j bfc00a50 -bfc00a1c: 00000000 nop -bfc00a20: 8fc20014 lw v0,20(s8) -bfc00a24: 00000000 nop -bfc00a28: 24420001 addiu v0,v0,1 -bfc00a2c: 90430000 lbu v1,0(v0) -bfc00a30: 24020030 li v0,48 -bfc00a34: 14620006 bne v1,v0,bfc00a50 -bfc00a38: 00000000 nop -bfc00a3c: 24020002 li v0,2 -bfc00a40: afc20004 sw v0,4(s8) -bfc00a44: 8fc30010 lw v1,16(s8) -bfc00a48: 24020001 li v0,1 -bfc00a4c: ac620008 sw v0,8(v1) -bfc00a50: 8fc20014 lw v0,20(s8) +bfc009dc: 00401821 move v1,v0 +bfc009e0: 2402003b li v0,59 +bfc009e4: 00431023 subu v0,v0,v1 +bfc009e8: afc20004 sw v0,4(s8) +bfc009ec: 8fc30010 lw v1,16(s8) +bfc009f0: 24020004 li v0,4 +bfc009f4: ac620008 sw v0,8(v1) +bfc009f8: 0bf0028c j bfc00a30 +bfc009fc: 00000000 nop +bfc00a00: 8fc20014 lw v0,20(s8) +bfc00a04: 00000000 nop +bfc00a08: 24420001 addiu v0,v0,1 +bfc00a0c: 90430000 lbu v1,0(v0) +bfc00a10: 24020030 li v0,48 +bfc00a14: 14620006 bne v1,v0,bfc00a30 +bfc00a18: 00000000 nop +bfc00a1c: 24020002 li v0,2 +bfc00a20: afc20004 sw v0,4(s8) +bfc00a24: 8fc30010 lw v1,16(s8) +bfc00a28: 24020001 li v0,1 +bfc00a2c: ac620008 sw v0,8(v1) +bfc00a30: 8fc20014 lw v0,20(s8) +bfc00a34: 00000000 nop +bfc00a38: 24420002 addiu v0,v0,2 +bfc00a3c: 00402021 move a0,v0 +bfc00a40: 0ff001fc jal bfc007f0 +bfc00a44: 00000000 nop +bfc00a48: a3c20008 sb v0,8(s8) +bfc00a4c: 93c30008 lbu v1,8(s8) +bfc00a50: 8fc20010 lw v0,16(s8) bfc00a54: 00000000 nop -bfc00a58: 24420002 addiu v0,v0,2 -bfc00a5c: 00402021 move a0,v0 -bfc00a60: 0ff00204 jal bfc00810 -bfc00a64: 00000000 nop -bfc00a68: a3c20008 sb v0,8(s8) -bfc00a6c: 93c30008 lbu v1,8(s8) -bfc00a70: 8fc20010 lw v0,16(s8) -bfc00a74: 00000000 nop -bfc00a78: ac430004 sw v1,4(v0) -bfc00a7c: 93c20008 lbu v0,8(s8) -bfc00a80: 00000000 nop -bfc00a84: a3c20009 sb v0,9(s8) -bfc00a88: 8fc20010 lw v0,16(s8) -bfc00a8c: 00000000 nop -bfc00a90: ac400000 sw zero,0(v0) -bfc00a94: afc00000 sw zero,0(s8) -bfc00a98: 0bf002c8 j bfc00b20 -bfc00a9c: 00000000 nop -bfc00aa0: 8fc20000 lw v0,0(s8) -bfc00aa4: 00000000 nop -bfc00aa8: 24420002 addiu v0,v0,2 -bfc00aac: 00021040 sll v0,v0,0x1 -bfc00ab0: 00401821 move v1,v0 -bfc00ab4: 8fc20014 lw v0,20(s8) -bfc00ab8: 00000000 nop -bfc00abc: 00431021 addu v0,v0,v1 -bfc00ac0: 00402021 move a0,v0 -bfc00ac4: 0ff00204 jal bfc00810 +bfc00a58: ac430004 sw v1,4(v0) +bfc00a5c: 93c20008 lbu v0,8(s8) +bfc00a60: 00000000 nop +bfc00a64: a3c20009 sb v0,9(s8) +bfc00a68: 8fc20010 lw v0,16(s8) +bfc00a6c: 00000000 nop +bfc00a70: ac400000 sw zero,0(v0) +bfc00a74: afc00000 sw zero,0(s8) +bfc00a78: 0bf002c0 j bfc00b00 +bfc00a7c: 00000000 nop +bfc00a80: 8fc20000 lw v0,0(s8) +bfc00a84: 00000000 nop +bfc00a88: 24420002 addiu v0,v0,2 +bfc00a8c: 00021040 sll v0,v0,0x1 +bfc00a90: 00401821 move v1,v0 +bfc00a94: 8fc20014 lw v0,20(s8) +bfc00a98: 00000000 nop +bfc00a9c: 00431021 addu v0,v0,v1 +bfc00aa0: 00402021 move a0,v0 +bfc00aa4: 0ff001fc jal bfc007f0 +bfc00aa8: 00000000 nop +bfc00aac: a3c20008 sb v0,8(s8) +bfc00ab0: 8fc20010 lw v0,16(s8) +bfc00ab4: 00000000 nop +bfc00ab8: 8c420000 lw v0,0(v0) +bfc00abc: 00000000 nop +bfc00ac0: 00021a00 sll v1,v0,0x8 +bfc00ac4: 93c20008 lbu v0,8(s8) bfc00ac8: 00000000 nop -bfc00acc: a3c20008 sb v0,8(s8) +bfc00acc: 00621825 or v1,v1,v0 bfc00ad0: 8fc20010 lw v0,16(s8) bfc00ad4: 00000000 nop -bfc00ad8: 8c420000 lw v0,0(v0) -bfc00adc: 00000000 nop -bfc00ae0: 00021a00 sll v1,v0,0x8 -bfc00ae4: 93c20008 lbu v0,8(s8) -bfc00ae8: 00000000 nop -bfc00aec: 00621825 or v1,v1,v0 -bfc00af0: 8fc20010 lw v0,16(s8) +bfc00ad8: ac430000 sw v1,0(v0) +bfc00adc: 93c30009 lbu v1,9(s8) +bfc00ae0: 93c20008 lbu v0,8(s8) +bfc00ae4: 00000000 nop +bfc00ae8: 00621021 addu v0,v1,v0 +bfc00aec: a3c20009 sb v0,9(s8) +bfc00af0: 8fc20000 lw v0,0(s8) bfc00af4: 00000000 nop -bfc00af8: ac430000 sw v1,0(v0) -bfc00afc: 93c30009 lbu v1,9(s8) -bfc00b00: 93c20008 lbu v0,8(s8) -bfc00b04: 00000000 nop -bfc00b08: 00621021 addu v0,v1,v0 -bfc00b0c: a3c20009 sb v0,9(s8) -bfc00b10: 8fc20000 lw v0,0(s8) +bfc00af8: 24420001 addiu v0,v0,1 +bfc00afc: afc20000 sw v0,0(s8) +bfc00b00: 8fc20000 lw v0,0(s8) +bfc00b04: 8fc30004 lw v1,4(s8) +bfc00b08: 00000000 nop +bfc00b0c: 0043102a slt v0,v0,v1 +bfc00b10: 1440ffdb bnez v0,bfc00a80 bfc00b14: 00000000 nop -bfc00b18: 24420001 addiu v0,v0,1 -bfc00b1c: afc20000 sw v0,0(s8) -bfc00b20: 8fc20000 lw v0,0(s8) -bfc00b24: 8fc30004 lw v1,4(s8) +bfc00b18: 8fc20010 lw v0,16(s8) +bfc00b1c: 00000000 nop +bfc00b20: 8c430004 lw v1,4(v0) +bfc00b24: 8fc20004 lw v0,4(s8) bfc00b28: 00000000 nop -bfc00b2c: 0043102a slt v0,v0,v1 -bfc00b30: 1440ffdb bnez v0,bfc00aa0 -bfc00b34: 00000000 nop -bfc00b38: 8fc20010 lw v0,16(s8) -bfc00b3c: 00000000 nop -bfc00b40: 8c430004 lw v1,4(v0) -bfc00b44: 8fc20004 lw v0,4(s8) -bfc00b48: 00000000 nop -bfc00b4c: 00021027 nor v0,zero,v0 -bfc00b50: 00621821 addu v1,v1,v0 -bfc00b54: 8fc20010 lw v0,16(s8) +bfc00b2c: 00021027 nor v0,zero,v0 +bfc00b30: 00621821 addu v1,v1,v0 +bfc00b34: 8fc20010 lw v0,16(s8) +bfc00b38: 00000000 nop +bfc00b3c: ac430004 sw v1,4(v0) +bfc00b40: 8fc20004 lw v0,4(s8) +bfc00b44: 00000000 nop +bfc00b48: 24420002 addiu v0,v0,2 +bfc00b4c: 00021040 sll v0,v0,0x1 +bfc00b50: 00401821 move v1,v0 +bfc00b54: 8fc20014 lw v0,20(s8) bfc00b58: 00000000 nop -bfc00b5c: ac430004 sw v1,4(v0) -bfc00b60: 8fc20004 lw v0,4(s8) +bfc00b5c: 00431821 addu v1,v0,v1 +bfc00b60: 8fc20010 lw v0,16(s8) bfc00b64: 00000000 nop -bfc00b68: 24420002 addiu v0,v0,2 -bfc00b6c: 00021040 sll v0,v0,0x1 -bfc00b70: 00401821 move v1,v0 -bfc00b74: 8fc20014 lw v0,20(s8) -bfc00b78: 00000000 nop -bfc00b7c: 00431821 addu v1,v0,v1 -bfc00b80: 8fc20010 lw v0,16(s8) -bfc00b84: 00000000 nop -bfc00b88: ac43000c sw v1,12(v0) -bfc00b8c: afc00000 sw zero,0(s8) -bfc00b90: 0bf00303 j bfc00c0c -bfc00b94: 00000000 nop -bfc00b98: 8fc20010 lw v0,16(s8) +bfc00b68: ac43000c sw v1,12(v0) +bfc00b6c: afc00000 sw zero,0(s8) +bfc00b70: 0bf002fb j bfc00bec +bfc00b74: 00000000 nop +bfc00b78: 8fc20010 lw v0,16(s8) +bfc00b7c: 00000000 nop +bfc00b80: 8c43000c lw v1,12(v0) +bfc00b84: 8fc20000 lw v0,0(s8) +bfc00b88: 00000000 nop +bfc00b8c: 00021040 sll v0,v0,0x1 +bfc00b90: 00621021 addu v0,v1,v0 +bfc00b94: 00402021 move a0,v0 +bfc00b98: 0ff001fc jal bfc007f0 bfc00b9c: 00000000 nop -bfc00ba0: 8c43000c lw v1,12(v0) -bfc00ba4: 8fc20000 lw v0,0(s8) +bfc00ba0: a3c20008 sb v0,8(s8) +bfc00ba4: 8fc20010 lw v0,16(s8) bfc00ba8: 00000000 nop -bfc00bac: 00021040 sll v0,v0,0x1 -bfc00bb0: 00621021 addu v0,v1,v0 -bfc00bb4: 00402021 move a0,v0 -bfc00bb8: 0ff00204 jal bfc00810 -bfc00bbc: 00000000 nop -bfc00bc0: a3c20008 sb v0,8(s8) -bfc00bc4: 8fc20010 lw v0,16(s8) -bfc00bc8: 00000000 nop -bfc00bcc: 8c43000c lw v1,12(v0) -bfc00bd0: 8fc20000 lw v0,0(s8) -bfc00bd4: 00000000 nop -bfc00bd8: 00621821 addu v1,v1,v0 -bfc00bdc: 93c20008 lbu v0,8(s8) +bfc00bac: 8c43000c lw v1,12(v0) +bfc00bb0: 8fc20000 lw v0,0(s8) +bfc00bb4: 00000000 nop +bfc00bb8: 00621821 addu v1,v1,v0 +bfc00bbc: 93c20008 lbu v0,8(s8) +bfc00bc0: 00000000 nop +bfc00bc4: a0620000 sb v0,0(v1) +bfc00bc8: 93c30009 lbu v1,9(s8) +bfc00bcc: 93c20008 lbu v0,8(s8) +bfc00bd0: 00000000 nop +bfc00bd4: 00621021 addu v0,v1,v0 +bfc00bd8: a3c20009 sb v0,9(s8) +bfc00bdc: 8fc20000 lw v0,0(s8) bfc00be0: 00000000 nop -bfc00be4: a0620000 sb v0,0(v1) -bfc00be8: 93c30009 lbu v1,9(s8) -bfc00bec: 93c20008 lbu v0,8(s8) +bfc00be4: 24420001 addiu v0,v0,1 +bfc00be8: afc20000 sw v0,0(s8) +bfc00bec: 8fc20010 lw v0,16(s8) bfc00bf0: 00000000 nop -bfc00bf4: 00621021 addu v0,v1,v0 -bfc00bf8: a3c20009 sb v0,9(s8) -bfc00bfc: 8fc20000 lw v0,0(s8) -bfc00c00: 00000000 nop -bfc00c04: 24420001 addiu v0,v0,1 -bfc00c08: afc20000 sw v0,0(s8) -bfc00c0c: 8fc20010 lw v0,16(s8) +bfc00bf4: 8c420004 lw v0,4(v0) +bfc00bf8: 00000000 nop +bfc00bfc: 00401821 move v1,v0 +bfc00c00: 8fc20000 lw v0,0(s8) +bfc00c04: 00000000 nop +bfc00c08: 0043102a slt v0,v0,v1 +bfc00c0c: 1440ffda bnez v0,bfc00b78 bfc00c10: 00000000 nop -bfc00c14: 8c420004 lw v0,4(v0) +bfc00c14: 93c20009 lbu v0,9(s8) bfc00c18: 00000000 nop -bfc00c1c: 00401821 move v1,v0 -bfc00c20: 8fc20000 lw v0,0(s8) -bfc00c24: 00000000 nop -bfc00c28: 0043102a slt v0,v0,v1 -bfc00c2c: 1440ffda bnez v0,bfc00b98 -bfc00c30: 00000000 nop -bfc00c34: 93c20009 lbu v0,9(s8) -bfc00c38: 00000000 nop -bfc00c3c: 00021027 nor v0,zero,v0 -bfc00c40: a3c20009 sb v0,9(s8) -bfc00c44: 8fc20010 lw v0,16(s8) +bfc00c1c: 00021027 nor v0,zero,v0 +bfc00c20: a3c20009 sb v0,9(s8) +bfc00c24: 8fc20010 lw v0,16(s8) +bfc00c28: 00000000 nop +bfc00c2c: 8c43000c lw v1,12(v0) +bfc00c30: 8fc20000 lw v0,0(s8) +bfc00c34: 00000000 nop +bfc00c38: 00021040 sll v0,v0,0x1 +bfc00c3c: 00621021 addu v0,v1,v0 +bfc00c40: 00402021 move a0,v0 +bfc00c44: 0ff001fc jal bfc007f0 bfc00c48: 00000000 nop -bfc00c4c: 8c43000c lw v1,12(v0) -bfc00c50: 8fc20000 lw v0,0(s8) -bfc00c54: 00000000 nop -bfc00c58: 00021040 sll v0,v0,0x1 -bfc00c5c: 00621021 addu v0,v1,v0 -bfc00c60: 00402021 move a0,v0 -bfc00c64: 0ff00204 jal bfc00810 -bfc00c68: 00000000 nop -bfc00c6c: a3c20008 sb v0,8(s8) -bfc00c70: 93c30009 lbu v1,9(s8) -bfc00c74: 93c20008 lbu v0,8(s8) -bfc00c78: 00000000 nop -bfc00c7c: 10620004 beq v1,v0,bfc00c90 -bfc00c80: 00000000 nop -bfc00c84: afc0001c sw zero,28(s8) -bfc00c88: 0bf00329 j bfc00ca4 -bfc00c8c: 00000000 nop -bfc00c90: 8fc20010 lw v0,16(s8) -bfc00c94: 00000000 nop -bfc00c98: 8c420008 lw v0,8(v0) +bfc00c4c: a3c20008 sb v0,8(s8) +bfc00c50: 93c30009 lbu v1,9(s8) +bfc00c54: 93c20008 lbu v0,8(s8) +bfc00c58: 00000000 nop +bfc00c5c: 10620004 beq v1,v0,bfc00c70 +bfc00c60: 00000000 nop +bfc00c64: afc0001c sw zero,28(s8) +bfc00c68: 0bf00321 j bfc00c84 +bfc00c6c: 00000000 nop +bfc00c70: 8fc20010 lw v0,16(s8) +bfc00c74: 00000000 nop +bfc00c78: 8c420008 lw v0,8(v0) +bfc00c7c: 00000000 nop +bfc00c80: afc2001c sw v0,28(s8) +bfc00c84: 8fc2001c lw v0,28(s8) +bfc00c88: 03c0e821 move sp,s8 +bfc00c8c: 8fbf0024 lw ra,36(sp) +bfc00c90: 8fbe0020 lw s8,32(sp) +bfc00c94: 27bd0028 addiu sp,sp,40 +bfc00c98: 03e00008 jr ra bfc00c9c: 00000000 nop -bfc00ca0: afc2001c sw v0,28(s8) -bfc00ca4: 8fc2001c lw v0,28(s8) -bfc00ca8: 03c0e821 move sp,s8 -bfc00cac: 8fbf0024 lw ra,36(sp) -bfc00cb0: 8fbe0020 lw s8,32(sp) -bfc00cb4: 27bd0028 addiu sp,sp,40 -bfc00cb8: 03e00008 jr ra + +bfc00ca0 : +bfc00ca0: 27bdffe8 addiu sp,sp,-24 +bfc00ca4: afbf0014 sw ra,20(sp) +bfc00ca8: afbe0010 sw s8,16(sp) +bfc00cac: 03a0f021 move s8,sp +bfc00cb0: afc40008 sw a0,8(s8) +bfc00cb4: afc00000 sw zero,0(s8) +bfc00cb8: 0ff0012b jal bfc004ac bfc00cbc: 00000000 nop - -bfc00cc0 : -bfc00cc0: 27bdffe8 addiu sp,sp,-24 -bfc00cc4: afbf0014 sw ra,20(sp) -bfc00cc8: afbe0010 sw s8,16(sp) -bfc00ccc: 03a0f021 move s8,sp -bfc00cd0: afc40008 sw a0,8(s8) -bfc00cd4: afc00000 sw zero,0(s8) -bfc00cd8: 0ff0012b jal bfc004ac -bfc00cdc: 00000000 nop -bfc00ce0: a3c20004 sb v0,4(s8) -bfc00ce4: 83c30004 lb v1,4(s8) -bfc00ce8: 24020073 li v0,115 -bfc00cec: 10620015 beq v1,v0,bfc00d44 -bfc00cf0: 00000000 nop -bfc00cf4: 83c30004 lb v1,4(s8) -bfc00cf8: 24020053 li v0,83 -bfc00cfc: 1462fff6 bne v1,v0,bfc00cd8 +bfc00cc0: a3c20004 sb v0,4(s8) +bfc00cc4: 83c30004 lb v1,4(s8) +bfc00cc8: 24020073 li v0,115 +bfc00ccc: 10620015 beq v1,v0,bfc00d24 +bfc00cd0: 00000000 nop +bfc00cd4: 83c30004 lb v1,4(s8) +bfc00cd8: 24020053 li v0,83 +bfc00cdc: 1462fff6 bne v1,v0,bfc00cb8 +bfc00ce0: 00000000 nop +bfc00ce4: 0bf00349 j bfc00d24 +bfc00ce8: 00000000 nop +bfc00cec: 8fc30000 lw v1,0(s8) +bfc00cf0: 8fc20008 lw v0,8(s8) +bfc00cf4: 00000000 nop +bfc00cf8: 00431821 addu v1,v0,v1 +bfc00cfc: 93c20004 lbu v0,4(s8) bfc00d00: 00000000 nop -bfc00d04: 0bf00351 j bfc00d44 -bfc00d08: 00000000 nop -bfc00d0c: 8fc30000 lw v1,0(s8) -bfc00d10: 8fc20008 lw v0,8(s8) -bfc00d14: 00000000 nop -bfc00d18: 00431821 addu v1,v0,v1 -bfc00d1c: 93c20004 lbu v0,4(s8) -bfc00d20: 00000000 nop -bfc00d24: a0620000 sb v0,0(v1) -bfc00d28: 8fc20000 lw v0,0(s8) -bfc00d2c: 00000000 nop -bfc00d30: 24420001 addiu v0,v0,1 -bfc00d34: afc20000 sw v0,0(s8) -bfc00d38: 0ff0012b jal bfc004ac -bfc00d3c: 00000000 nop -bfc00d40: a3c20004 sb v0,4(s8) -bfc00d44: 83c30004 lb v1,4(s8) -bfc00d48: 2402000d li v0,13 -bfc00d4c: 10620005 beq v1,v0,bfc00d64 -bfc00d50: 00000000 nop -bfc00d54: 83c30004 lb v1,4(s8) -bfc00d58: 2402000a li v0,10 -bfc00d5c: 1462ffeb bne v1,v0,bfc00d0c -bfc00d60: 00000000 nop -bfc00d64: 8fc20000 lw v0,0(s8) -bfc00d68: 03c0e821 move sp,s8 -bfc00d6c: 8fbf0014 lw ra,20(sp) -bfc00d70: 8fbe0010 lw s8,16(sp) -bfc00d74: 27bd0018 addiu sp,sp,24 -bfc00d78: 03e00008 jr ra -bfc00d7c: 00000000 nop +bfc00d04: a0620000 sb v0,0(v1) +bfc00d08: 8fc20000 lw v0,0(s8) +bfc00d0c: 00000000 nop +bfc00d10: 24420001 addiu v0,v0,1 +bfc00d14: afc20000 sw v0,0(s8) +bfc00d18: 0ff0012b jal bfc004ac +bfc00d1c: 00000000 nop +bfc00d20: a3c20004 sb v0,4(s8) +bfc00d24: 83c30004 lb v1,4(s8) +bfc00d28: 2402000d li v0,13 +bfc00d2c: 10620005 beq v1,v0,bfc00d44 +bfc00d30: 00000000 nop +bfc00d34: 83c30004 lb v1,4(s8) +bfc00d38: 2402000a li v0,10 +bfc00d3c: 1462ffeb bne v1,v0,bfc00cec +bfc00d40: 00000000 nop +bfc00d44: 8fc20000 lw v0,0(s8) +bfc00d48: 03c0e821 move sp,s8 +bfc00d4c: 8fbf0014 lw ra,20(sp) +bfc00d50: 8fbe0010 lw s8,16(sp) +bfc00d54: 27bd0018 addiu sp,sp,24 +bfc00d58: 03e00008 jr ra +bfc00d5c: 00000000 nop -bfc00d80 : -bfc00d80: 27bdfff0 addiu sp,sp,-16 -bfc00d84: afbe000c sw s8,12(sp) -bfc00d88: 03a0f021 move s8,sp -bfc00d8c: afc40000 sw a0,0(s8) -bfc00d90: 401a6000 mfc0 k0,$12 -bfc00d94: 3c1bffbf lui k1,0xffbf -bfc00d98: 377bffff ori k1,k1,0xffff -bfc00d9c: 035bd024 and k0,k0,k1 -bfc00da0: 409a6000 mtc0 k0,$12 -bfc00da4: 00800008 jr a0 -bfc00da8: 42000010 rfe -bfc00dac: 03c0e821 move sp,s8 -bfc00db0: 8fbe000c lw s8,12(sp) -bfc00db4: 03e00008 jr ra -bfc00db8: 27bd0010 addiu sp,sp,16 +bfc00d60 : +bfc00d60: 27bdfff0 addiu sp,sp,-16 +bfc00d64: afbe000c sw s8,12(sp) +bfc00d68: 03a0f021 move s8,sp +bfc00d6c: afc40000 sw a0,0(s8) +bfc00d70: 401a6000 mfc0 k0,$12 +bfc00d74: 3c1bffbf lui k1,0xffbf +bfc00d78: 377bffff ori k1,k1,0xffff +bfc00d7c: 035bd024 and k0,k0,k1 +bfc00d80: 409a6000 mtc0 k0,$12 +bfc00d84: 00800008 jr a0 +bfc00d88: 42000010 rfe +bfc00d8c: 03c0e821 move sp,s8 +bfc00d90: 8fbe000c lw s8,12(sp) +bfc00d94: 03e00008 jr ra +bfc00d98: 27bd0010 addiu sp,sp,16 -bfc00dbc : -bfc00dbc: 27bdffd0 addiu sp,sp,-48 -bfc00dc0: afbf002c sw ra,44(sp) -bfc00dc4: afbe0028 sw s8,40(sp) -bfc00dc8: 03a0f021 move s8,sp -bfc00dcc: 3c02bfc0 lui v0,0xbfc0 -bfc00dd0: 244215d0 addiu v0,v0,5584 -bfc00dd4: afc20008 sw v0,8(s8) -bfc00dd8: 3c02bfc0 lui v0,0xbfc0 -bfc00ddc: 244215d8 addiu v0,v0,5592 -bfc00de0: afc2000c sw v0,12(s8) -bfc00de4: 3c02bfc0 lui v0,0xbfc0 -bfc00de8: 244215e0 addiu v0,v0,5600 -bfc00dec: afc20010 sw v0,16(s8) -bfc00df0: 3c02bfc0 lui v0,0xbfc0 -bfc00df4: 244215e8 addiu v0,v0,5608 -bfc00df8: afc20014 sw v0,20(s8) -bfc00dfc: 3c02bfc0 lui v0,0xbfc0 -bfc00e00: 244215f0 addiu v0,v0,5616 -bfc00e04: afc20018 sw v0,24(s8) -bfc00e08: 3c02bfc0 lui v0,0xbfc0 -bfc00e0c: 244215f8 addiu v0,v0,5624 -bfc00e10: afc2001c sw v0,28(s8) -bfc00e14: 3c02bfc0 lui v0,0xbfc0 -bfc00e18: 24421604 addiu v0,v0,5636 -bfc00e1c: afc20020 sw v0,32(s8) -bfc00e20: 0ff0011b jal bfc0046c +bfc00d9c : +bfc00d9c: 27bdffd0 addiu sp,sp,-48 +bfc00da0: afbf002c sw ra,44(sp) +bfc00da4: afbe0028 sw s8,40(sp) +bfc00da8: 03a0f021 move s8,sp +bfc00dac: 3c02bfc0 lui v0,0xbfc0 +bfc00db0: 24421738 addiu v0,v0,5944 +bfc00db4: afc20008 sw v0,8(s8) +bfc00db8: 3c02bfc0 lui v0,0xbfc0 +bfc00dbc: 24421740 addiu v0,v0,5952 +bfc00dc0: afc2000c sw v0,12(s8) +bfc00dc4: 3c02bfc0 lui v0,0xbfc0 +bfc00dc8: 24421748 addiu v0,v0,5960 +bfc00dcc: afc20010 sw v0,16(s8) +bfc00dd0: 3c02bfc0 lui v0,0xbfc0 +bfc00dd4: 24421750 addiu v0,v0,5968 +bfc00dd8: afc20014 sw v0,20(s8) +bfc00ddc: 3c02bfc0 lui v0,0xbfc0 +bfc00de0: 24421758 addiu v0,v0,5976 +bfc00de4: afc20018 sw v0,24(s8) +bfc00de8: 3c02bfc0 lui v0,0xbfc0 +bfc00dec: 24421760 addiu v0,v0,5984 +bfc00df0: afc2001c sw v0,28(s8) +bfc00df4: 3c02bfc0 lui v0,0xbfc0 +bfc00df8: 2442176c addiu v0,v0,5996 +bfc00dfc: afc20020 sw v0,32(s8) +bfc00e00: 0ff0011b jal bfc0046c +bfc00e04: 00000000 nop +bfc00e08: afc20004 sw v0,4(s8) +bfc00e0c: 3c02bfc0 lui v0,0xbfc0 +bfc00e10: 24441774 addiu a0,v0,6004 +bfc00e14: 0ff0017e jal bfc005f8 +bfc00e18: 00000000 nop +bfc00e1c: 8fc40004 lw a0,4(s8) +bfc00e20: 0ff001d8 jal bfc00760 bfc00e24: 00000000 nop -bfc00e28: afc20004 sw v0,4(s8) -bfc00e2c: 3c02bfc0 lui v0,0xbfc0 -bfc00e30: 2444160c addiu a0,v0,5644 -bfc00e34: 0ff00186 jal bfc00618 -bfc00e38: 00000000 nop -bfc00e3c: 8fc40004 lw a0,4(s8) -bfc00e40: 0ff001e0 jal bfc00780 -bfc00e44: 00000000 nop -bfc00e48: 3c02bfc0 lui v0,0xbfc0 -bfc00e4c: 24441618 addiu a0,v0,5656 -bfc00e50: 0ff00186 jal bfc00618 -bfc00e54: 00000000 nop -bfc00e58: 0ff00123 jal bfc0048c -bfc00e5c: 00000000 nop -bfc00e60: afc20004 sw v0,4(s8) -bfc00e64: 8fc20004 lw v0,4(s8) -bfc00e68: 00000000 nop -bfc00e6c: 00021203 sra v0,v0,0x8 -bfc00e70: 304200ff andi v0,v0,0xff -bfc00e74: afc20000 sw v0,0(s8) -bfc00e78: 3c02bfc0 lui v0,0xbfc0 -bfc00e7c: 2444161c addiu a0,v0,5660 -bfc00e80: 0ff00186 jal bfc00618 -bfc00e84: 00000000 nop -bfc00e88: 8fc20000 lw v0,0(s8) -bfc00e8c: 00000000 nop -bfc00e90: 18400020 blez v0,bfc00f14 -bfc00e94: 00000000 nop -bfc00e98: 8fc20000 lw v0,0(s8) -bfc00e9c: 00000000 nop -bfc00ea0: 28420007 slti v0,v0,7 -bfc00ea4: 1040001b beqz v0,bfc00f14 -bfc00ea8: 00000000 nop -bfc00eac: 8fc20000 lw v0,0(s8) -bfc00eb0: 00000000 nop -bfc00eb4: 00021080 sll v0,v0,0x2 -bfc00eb8: 03c21021 addu v0,s8,v0 -bfc00ebc: 8c420008 lw v0,8(v0) -bfc00ec0: 00000000 nop -bfc00ec4: 00402021 move a0,v0 -bfc00ec8: 0ff00186 jal bfc00618 -bfc00ecc: 00000000 nop -bfc00ed0: 3c02bfc0 lui v0,0xbfc0 -bfc00ed4: 24441628 addiu a0,v0,5672 -bfc00ed8: 0ff00186 jal bfc00618 -bfc00edc: 00000000 nop -bfc00ee0: 8fc20004 lw v0,4(s8) -bfc00ee4: 00000000 nop -bfc00ee8: 304200ff andi v0,v0,0xff -bfc00eec: afc20000 sw v0,0(s8) -bfc00ef0: 8fc20000 lw v0,0(s8) -bfc00ef4: 00000000 nop -bfc00ef8: 00021600 sll v0,v0,0x18 -bfc00efc: 00021603 sra v0,v0,0x18 -bfc00f00: 00402021 move a0,v0 -bfc00f04: 0ff001ac jal bfc006b0 -bfc00f08: 00000000 nop -bfc00f0c: 0bf003c9 j bfc00f24 +bfc00e28: 3c02bfc0 lui v0,0xbfc0 +bfc00e2c: 24441780 addiu a0,v0,6016 +bfc00e30: 0ff0017e jal bfc005f8 +bfc00e34: 00000000 nop +bfc00e38: 0ff00123 jal bfc0048c +bfc00e3c: 00000000 nop +bfc00e40: afc20004 sw v0,4(s8) +bfc00e44: 8fc20004 lw v0,4(s8) +bfc00e48: 00000000 nop +bfc00e4c: 00021203 sra v0,v0,0x8 +bfc00e50: 304200ff andi v0,v0,0xff +bfc00e54: afc20000 sw v0,0(s8) +bfc00e58: 3c02bfc0 lui v0,0xbfc0 +bfc00e5c: 24441784 addiu a0,v0,6020 +bfc00e60: 0ff0017e jal bfc005f8 +bfc00e64: 00000000 nop +bfc00e68: 8fc20000 lw v0,0(s8) +bfc00e6c: 00000000 nop +bfc00e70: 18400020 blez v0,bfc00ef4 +bfc00e74: 00000000 nop +bfc00e78: 8fc20000 lw v0,0(s8) +bfc00e7c: 00000000 nop +bfc00e80: 28420007 slti v0,v0,7 +bfc00e84: 1040001b beqz v0,bfc00ef4 +bfc00e88: 00000000 nop +bfc00e8c: 8fc20000 lw v0,0(s8) +bfc00e90: 00000000 nop +bfc00e94: 00021080 sll v0,v0,0x2 +bfc00e98: 03c21021 addu v0,s8,v0 +bfc00e9c: 8c420008 lw v0,8(v0) +bfc00ea0: 00000000 nop +bfc00ea4: 00402021 move a0,v0 +bfc00ea8: 0ff0017e jal bfc005f8 +bfc00eac: 00000000 nop +bfc00eb0: 3c02bfc0 lui v0,0xbfc0 +bfc00eb4: 24441790 addiu a0,v0,6032 +bfc00eb8: 0ff0017e jal bfc005f8 +bfc00ebc: 00000000 nop +bfc00ec0: 8fc20004 lw v0,4(s8) +bfc00ec4: 00000000 nop +bfc00ec8: 304200ff andi v0,v0,0xff +bfc00ecc: afc20000 sw v0,0(s8) +bfc00ed0: 8fc20000 lw v0,0(s8) +bfc00ed4: 00000000 nop +bfc00ed8: 00021600 sll v0,v0,0x18 +bfc00edc: 00021603 sra v0,v0,0x18 +bfc00ee0: 00402021 move a0,v0 +bfc00ee4: 0ff001a4 jal bfc00690 +bfc00ee8: 00000000 nop +bfc00eec: 0bf003c1 j bfc00f04 +bfc00ef0: 00000000 nop +bfc00ef4: 3c02bfc0 lui v0,0xbfc0 +bfc00ef8: 24441798 addiu a0,v0,6040 +bfc00efc: 0ff0017e jal bfc005f8 +bfc00f00: 00000000 nop +bfc00f04: 3c02bfc0 lui v0,0xbfc0 +bfc00f08: 24441780 addiu a0,v0,6016 +bfc00f0c: 0ff0017e jal bfc005f8 bfc00f10: 00000000 nop -bfc00f14: 3c02bfc0 lui v0,0xbfc0 -bfc00f18: 24441630 addiu a0,v0,5680 -bfc00f1c: 0ff00186 jal bfc00618 -bfc00f20: 00000000 nop -bfc00f24: 3c02bfc0 lui v0,0xbfc0 -bfc00f28: 24441618 addiu a0,v0,5656 -bfc00f2c: 0ff00186 jal bfc00618 -bfc00f30: 00000000 nop -bfc00f34: 03c0e821 move sp,s8 -bfc00f38: 8fbf002c lw ra,44(sp) -bfc00f3c: 8fbe0028 lw s8,40(sp) -bfc00f40: 27bd0030 addiu sp,sp,48 -bfc00f44: 03e00008 jr ra -bfc00f48: 00000000 nop +bfc00f14: 03c0e821 move sp,s8 +bfc00f18: 8fbf002c lw ra,44(sp) +bfc00f1c: 8fbe0028 lw s8,40(sp) +bfc00f20: 27bd0030 addiu sp,sp,48 +bfc00f24: 03e00008 jr ra +bfc00f28: 00000000 nop -bfc00f4c
: -bfc00f4c: 27bdfea8 addiu sp,sp,-344 -bfc00f50: afbf0154 sw ra,340(sp) -bfc00f54: afbe0150 sw s8,336(sp) -bfc00f58: 03a0f021 move s8,sp -bfc00f5c: afc40140 sw a0,320(s8) -bfc00f60: afc50144 sw a1,324(s8) -bfc00f64: 3c02a000 lui v0,0xa000 -bfc00f68: afc2001c sw v0,28(s8) +bfc00f2c
: +bfc00f2c: 27bdfea0 addiu sp,sp,-352 +bfc00f30: afbf015c sw ra,348(sp) +bfc00f34: afbe0158 sw s8,344(sp) +bfc00f38: 03a0f021 move s8,sp +bfc00f3c: afc40148 sw a0,328(s8) +bfc00f40: afc5014c sw a1,332(s8) +bfc00f44: 3c02a000 lui v0,0xa000 +bfc00f48: afc20024 sw v0,36(s8) +bfc00f4c: 3c02a400 lui v0,0xa400 +bfc00f50: afc20014 sw v0,20(s8) +bfc00f54: 3c02a002 lui v0,0xa002 +bfc00f58: afc20010 sw v0,16(s8) +bfc00f5c: 3c024000 lui v0,0x4000 +bfc00f60: afc2000c sw v0,12(s8) +bfc00f64: 3c024000 lui v0,0x4000 +bfc00f68: afc20008 sw v0,8(s8) bfc00f6c: 3c024000 lui v0,0x4000 -bfc00f70: afc2000c sw v0,12(s8) -bfc00f74: 3c024000 lui v0,0x4000 -bfc00f78: afc20008 sw v0,8(s8) -bfc00f7c: 3c024000 lui v0,0x4000 -bfc00f80: afc20004 sw v0,4(s8) -bfc00f84: 3c02bfc0 lui v0,0xbfc0 -bfc00f88: 24421638 addiu v0,v0,5688 -bfc00f8c: afc20000 sw v0,0(s8) -bfc00f90: 8fc2001c lw v0,28(s8) +bfc00f70: afc20004 sw v0,4(s8) +bfc00f74: 3c02bfc0 lui v0,0xbfc0 +bfc00f78: 244217a0 addiu v0,v0,6048 +bfc00f7c: afc20000 sw v0,0(s8) +bfc00f80: 8fc20024 lw v0,36(s8) +bfc00f84: 00000000 nop +bfc00f88: ac400000 sw zero,0(v0) +bfc00f8c: afc00028 sw zero,40(s8) +bfc00f90: 0ff00367 jal bfc00d9c bfc00f94: 00000000 nop -bfc00f98: ac400000 sw zero,0(v0) -bfc00f9c: afc00020 sw zero,32(s8) -bfc00fa0: 0ff0036f jal bfc00dbc -bfc00fa4: 00000000 nop -bfc00fa8: 3c024000 lui v0,0x4000 -bfc00fac: afc20010 sw v0,16(s8) -bfc00fb0: afc00014 sw zero,20(s8) -bfc00fb4: afc00024 sw zero,36(s8) -bfc00fb8: 0bf00402 j bfc01008 -bfc00fbc: 00000000 nop +bfc00f98: 8fc30014 lw v1,20(s8) +bfc00f9c: 3c021234 lui v0,0x1234 +bfc00fa0: 34425678 ori v0,v0,0x5678 +bfc00fa4: ac620000 sw v0,0(v1) +bfc00fa8: 8fc20014 lw v0,20(s8) +bfc00fac: 00000000 nop +bfc00fb0: 24430004 addiu v1,v0,4 +bfc00fb4: 3c02aaaa lui v0,0xaaaa +bfc00fb8: 34425555 ori v0,v0,0x5555 +bfc00fbc: ac620000 sw v0,0(v1) bfc00fc0: 8fc20014 lw v0,20(s8) bfc00fc4: 00000000 nop -bfc00fc8: 8c430000 lw v1,0(v0) -bfc00fcc: 8fc20010 lw v0,16(s8) -bfc00fd0: 00000000 nop -bfc00fd4: ac430000 sw v1,0(v0) -bfc00fd8: 8fc20010 lw v0,16(s8) -bfc00fdc: 00000000 nop -bfc00fe0: 24420004 addiu v0,v0,4 -bfc00fe4: afc20010 sw v0,16(s8) +bfc00fc8: 24430008 addiu v1,v0,8 +bfc00fcc: 3c02ffff lui v0,0xffff +bfc00fd0: ac620000 sw v0,0(v1) +bfc00fd4: 8fc20014 lw v0,20(s8) +bfc00fd8: 00000000 nop +bfc00fdc: 2443000c addiu v1,v0,12 +bfc00fe0: 3402ffff li v0,0xffff +bfc00fe4: ac620000 sw v0,0(v1) bfc00fe8: 8fc20014 lw v0,20(s8) bfc00fec: 00000000 nop -bfc00ff0: 24420004 addiu v0,v0,4 -bfc00ff4: afc20014 sw v0,20(s8) -bfc00ff8: 8fc20024 lw v0,36(s8) -bfc00ffc: 00000000 nop -bfc01000: 24420004 addiu v0,v0,4 -bfc01004: afc20024 sw v0,36(s8) -bfc01008: 8fc20024 lw v0,36(s8) -bfc0100c: 00000000 nop -bfc01010: 28421c00 slti v0,v0,7168 -bfc01014: 1440ffea bnez v0,bfc00fc0 -bfc01018: 00000000 nop -bfc0101c: 3c044000 lui a0,0x4000 -bfc01020: 0ff00360 jal bfc00d80 -bfc01024: 00000000 nop -bfc01028: 3c02bfc0 lui v0,0xbfc0 -bfc0102c: 24441644 addiu a0,v0,5700 -bfc01030: 0ff00186 jal bfc00618 -bfc01034: 00000000 nop -bfc01038: 3c02bfc0 lui v0,0xbfc0 -bfc0103c: 24441658 addiu a0,v0,5720 -bfc01040: 0ff00186 jal bfc00618 -bfc01044: 00000000 nop -bfc01048: afc00024 sw zero,36(s8) -bfc0104c: 0bf00421 j bfc01084 -bfc01050: 00000000 nop -bfc01054: 8fc30024 lw v1,36(s8) -bfc01058: 8fc2000c lw v0,12(s8) -bfc0105c: 00000000 nop -bfc01060: 00431821 addu v1,v0,v1 -bfc01064: 8fc20024 lw v0,36(s8) +bfc00ff0: 8c430000 lw v1,0(v0) +bfc00ff4: 8fc20024 lw v0,36(s8) +bfc00ff8: 00000000 nop +bfc00ffc: ac430000 sw v1,0(v0) +bfc01000: 8fc20014 lw v0,20(s8) +bfc01004: 00000000 nop +bfc01008: 24420004 addiu v0,v0,4 +bfc0100c: 8c430000 lw v1,0(v0) +bfc01010: 8fc20024 lw v0,36(s8) +bfc01014: 00000000 nop +bfc01018: ac430000 sw v1,0(v0) +bfc0101c: 8fc20014 lw v0,20(s8) +bfc01020: 00000000 nop +bfc01024: 24420008 addiu v0,v0,8 +bfc01028: 8c430000 lw v1,0(v0) +bfc0102c: 8fc20024 lw v0,36(s8) +bfc01030: 00000000 nop +bfc01034: ac430000 sw v1,0(v0) +bfc01038: 8fc20014 lw v0,20(s8) +bfc0103c: 00000000 nop +bfc01040: 2442000c addiu v0,v0,12 +bfc01044: 8c430000 lw v1,0(v0) +bfc01048: 8fc20024 lw v0,36(s8) +bfc0104c: 00000000 nop +bfc01050: ac430000 sw v1,0(v0) +bfc01054: 8fc30010 lw v1,16(s8) +bfc01058: 3c021234 lui v0,0x1234 +bfc0105c: 34425678 ori v0,v0,0x5678 +bfc01060: ac620000 sw v0,0(v1) +bfc01064: 8fc20010 lw v0,16(s8) bfc01068: 00000000 nop -bfc0106c: 304200ff andi v0,v0,0xff -bfc01070: a0620000 sb v0,0(v1) -bfc01074: 8fc20024 lw v0,36(s8) -bfc01078: 00000000 nop -bfc0107c: 24420001 addiu v0,v0,1 -bfc01080: afc20024 sw v0,36(s8) -bfc01084: 8fc20024 lw v0,36(s8) -bfc01088: 3c030040 lui v1,0x40 -bfc0108c: 0043102a slt v0,v0,v1 -bfc01090: 1440fff0 bnez v0,bfc01054 +bfc0106c: 24430004 addiu v1,v0,4 +bfc01070: 3c02aaaa lui v0,0xaaaa +bfc01074: 34425555 ori v0,v0,0x5555 +bfc01078: ac620000 sw v0,0(v1) +bfc0107c: 8fc20010 lw v0,16(s8) +bfc01080: 00000000 nop +bfc01084: 24430008 addiu v1,v0,8 +bfc01088: 3c02ffff lui v0,0xffff +bfc0108c: ac620000 sw v0,0(v1) +bfc01090: 8fc20010 lw v0,16(s8) bfc01094: 00000000 nop -bfc01098: 3c02bfc0 lui v0,0xbfc0 -bfc0109c: 24441670 addiu a0,v0,5744 -bfc010a0: 0ff00186 jal bfc00618 -bfc010a4: 00000000 nop -bfc010a8: 3c02bfc0 lui v0,0xbfc0 -bfc010ac: 24441678 addiu a0,v0,5752 -bfc010b0: 0ff00186 jal bfc00618 +bfc01098: 2443000c addiu v1,v0,12 +bfc0109c: 3402ffff li v0,0xffff +bfc010a0: ac620000 sw v0,0(v1) +bfc010a4: 8fc20010 lw v0,16(s8) +bfc010a8: 00000000 nop +bfc010ac: 8c430000 lw v1,0(v0) +bfc010b0: 8fc20024 lw v0,36(s8) bfc010b4: 00000000 nop -bfc010b8: 3c02003f lui v0,0x3f -bfc010bc: 3442ffff ori v0,v0,0xffff -bfc010c0: afc20024 sw v0,36(s8) -bfc010c4: 0bf00441 j bfc01104 -bfc010c8: 00000000 nop -bfc010cc: 8fc30024 lw v1,36(s8) -bfc010d0: 8fc2000c lw v0,12(s8) -bfc010d4: 00000000 nop -bfc010d8: 00431021 addu v0,v0,v1 -bfc010dc: 90430000 lbu v1,0(v0) -bfc010e0: 8fc20024 lw v0,36(s8) -bfc010e4: 00000000 nop -bfc010e8: 304200ff andi v0,v0,0xff -bfc010ec: 14620009 bne v1,v0,bfc01114 -bfc010f0: 00000000 nop -bfc010f4: 8fc20024 lw v0,36(s8) +bfc010b8: ac430000 sw v1,0(v0) +bfc010bc: 8fc20010 lw v0,16(s8) +bfc010c0: 00000000 nop +bfc010c4: 24420004 addiu v0,v0,4 +bfc010c8: 8c430000 lw v1,0(v0) +bfc010cc: 8fc20024 lw v0,36(s8) +bfc010d0: 00000000 nop +bfc010d4: ac430000 sw v1,0(v0) +bfc010d8: 8fc20010 lw v0,16(s8) +bfc010dc: 00000000 nop +bfc010e0: 24420008 addiu v0,v0,8 +bfc010e4: 8c430000 lw v1,0(v0) +bfc010e8: 8fc20024 lw v0,36(s8) +bfc010ec: 00000000 nop +bfc010f0: ac430000 sw v1,0(v0) +bfc010f4: 8fc20010 lw v0,16(s8) bfc010f8: 00000000 nop -bfc010fc: 2442ffff addiu v0,v0,-1 -bfc01100: afc20024 sw v0,36(s8) +bfc010fc: 2442000c addiu v0,v0,12 +bfc01100: 8c430000 lw v1,0(v0) bfc01104: 8fc20024 lw v0,36(s8) bfc01108: 00000000 nop -bfc0110c: 0441ffef bgez v0,bfc010cc -bfc01110: 00000000 nop -bfc01114: 8fc20024 lw v0,36(s8) -bfc01118: 00000000 nop -bfc0111c: 24420001 addiu v0,v0,1 -bfc01120: afc20024 sw v0,36(s8) -bfc01124: 8fc20024 lw v0,36(s8) -bfc01128: 00000000 nop -bfc0112c: 10400007 beqz v0,bfc0114c -bfc01130: 00000000 nop -bfc01134: 3c02bfc0 lui v0,0xbfc0 -bfc01138: 24441694 addiu a0,v0,5780 -bfc0113c: 0ff00186 jal bfc00618 -bfc01140: 00000000 nop -bfc01144: 0bf00457 j bfc0115c -bfc01148: 00000000 nop -bfc0114c: 3c02bfc0 lui v0,0xbfc0 -bfc01150: 244416a0 addiu a0,v0,5792 -bfc01154: 0ff00186 jal bfc00618 -bfc01158: 00000000 nop -bfc0115c: 3c02bfc0 lui v0,0xbfc0 -bfc01160: 244416ac addiu a0,v0,5804 -bfc01164: 0ff00186 jal bfc00618 -bfc01168: 00000000 nop -bfc0116c: afc00024 sw zero,36(s8) -bfc01170: 0bf0046c j bfc011b0 +bfc0110c: ac430000 sw v1,0(v0) +bfc01110: 3c024000 lui v0,0x4000 +bfc01114: afc20018 sw v0,24(s8) +bfc01118: afc0001c sw zero,28(s8) +bfc0111c: afc0002c sw zero,44(s8) +bfc01120: 0bf0045c j bfc01170 +bfc01124: 00000000 nop +bfc01128: 8fc2001c lw v0,28(s8) +bfc0112c: 00000000 nop +bfc01130: 8c430000 lw v1,0(v0) +bfc01134: 8fc20018 lw v0,24(s8) +bfc01138: 00000000 nop +bfc0113c: ac430000 sw v1,0(v0) +bfc01140: 8fc20018 lw v0,24(s8) +bfc01144: 00000000 nop +bfc01148: 24420004 addiu v0,v0,4 +bfc0114c: afc20018 sw v0,24(s8) +bfc01150: 8fc2001c lw v0,28(s8) +bfc01154: 00000000 nop +bfc01158: 24420004 addiu v0,v0,4 +bfc0115c: afc2001c sw v0,28(s8) +bfc01160: 8fc2002c lw v0,44(s8) +bfc01164: 00000000 nop +bfc01168: 24420004 addiu v0,v0,4 +bfc0116c: afc2002c sw v0,44(s8) +bfc01170: 8fc2002c lw v0,44(s8) bfc01174: 00000000 nop -bfc01178: 8fc20024 lw v0,36(s8) -bfc0117c: 00000000 nop -bfc01180: 00021840 sll v1,v0,0x1 -bfc01184: 8fc20008 lw v0,8(s8) -bfc01188: 00000000 nop -bfc0118c: 00431821 addu v1,v0,v1 -bfc01190: 8fc20024 lw v0,36(s8) -bfc01194: 00000000 nop -bfc01198: 3042ffff andi v0,v0,0xffff -bfc0119c: a4620000 sh v0,0(v1) -bfc011a0: 8fc20024 lw v0,36(s8) -bfc011a4: 00000000 nop -bfc011a8: 24420001 addiu v0,v0,1 -bfc011ac: afc20024 sw v0,36(s8) -bfc011b0: 8fc20024 lw v0,36(s8) -bfc011b4: 3c030020 lui v1,0x20 -bfc011b8: 0043102a slt v0,v0,v1 -bfc011bc: 1440ffee bnez v0,bfc01178 -bfc011c0: 00000000 nop -bfc011c4: 3c02bfc0 lui v0,0xbfc0 -bfc011c8: 24441670 addiu a0,v0,5744 -bfc011cc: 0ff00186 jal bfc00618 +bfc01178: 28421c00 slti v0,v0,7168 +bfc0117c: 1440ffea bnez v0,bfc01128 +bfc01180: 00000000 nop +bfc01184: 3c044000 lui a0,0x4000 +bfc01188: 0ff00358 jal bfc00d60 +bfc0118c: 00000000 nop +bfc01190: 3c02bfc0 lui v0,0xbfc0 +bfc01194: 244417ac addiu a0,v0,6060 +bfc01198: 0ff0017e jal bfc005f8 +bfc0119c: 00000000 nop +bfc011a0: 3c02bfc0 lui v0,0xbfc0 +bfc011a4: 244417c0 addiu a0,v0,6080 +bfc011a8: 0ff0017e jal bfc005f8 +bfc011ac: 00000000 nop +bfc011b0: afc0002c sw zero,44(s8) +bfc011b4: 0bf0047b j bfc011ec +bfc011b8: 00000000 nop +bfc011bc: 8fc3002c lw v1,44(s8) +bfc011c0: 8fc2000c lw v0,12(s8) +bfc011c4: 00000000 nop +bfc011c8: 00431821 addu v1,v0,v1 +bfc011cc: 8fc2002c lw v0,44(s8) bfc011d0: 00000000 nop -bfc011d4: 3c02bfc0 lui v0,0xbfc0 -bfc011d8: 244416c8 addiu a0,v0,5832 -bfc011dc: 0ff00186 jal bfc00618 +bfc011d4: 304200ff andi v0,v0,0xff +bfc011d8: a0620000 sb v0,0(v1) +bfc011dc: 8fc2002c lw v0,44(s8) bfc011e0: 00000000 nop -bfc011e4: 3c02001f lui v0,0x1f -bfc011e8: 3442ffff ori v0,v0,0xffff -bfc011ec: afc20024 sw v0,36(s8) -bfc011f0: 0bf0048e j bfc01238 -bfc011f4: 00000000 nop -bfc011f8: 8fc20024 lw v0,36(s8) +bfc011e4: 24420001 addiu v0,v0,1 +bfc011e8: afc2002c sw v0,44(s8) +bfc011ec: 8fc2002c lw v0,44(s8) +bfc011f0: 3c030040 lui v1,0x40 +bfc011f4: 0043102a slt v0,v0,v1 +bfc011f8: 1440fff0 bnez v0,bfc011bc bfc011fc: 00000000 nop -bfc01200: 00021840 sll v1,v0,0x1 -bfc01204: 8fc20008 lw v0,8(s8) -bfc01208: 00000000 nop -bfc0120c: 00431021 addu v0,v0,v1 -bfc01210: 94430000 lhu v1,0(v0) -bfc01214: 8fc20024 lw v0,36(s8) -bfc01218: 00000000 nop -bfc0121c: 3042ffff andi v0,v0,0xffff -bfc01220: 14620009 bne v1,v0,bfc01248 -bfc01224: 00000000 nop -bfc01228: 8fc20024 lw v0,36(s8) -bfc0122c: 00000000 nop -bfc01230: 2442ffff addiu v0,v0,-1 -bfc01234: afc20024 sw v0,36(s8) -bfc01238: 8fc20024 lw v0,36(s8) +bfc01200: 3c02bfc0 lui v0,0xbfc0 +bfc01204: 244417d8 addiu a0,v0,6104 +bfc01208: 0ff0017e jal bfc005f8 +bfc0120c: 00000000 nop +bfc01210: 3c02bfc0 lui v0,0xbfc0 +bfc01214: 244417e0 addiu a0,v0,6112 +bfc01218: 0ff0017e jal bfc005f8 +bfc0121c: 00000000 nop +bfc01220: 3c02003f lui v0,0x3f +bfc01224: 3442ffff ori v0,v0,0xffff +bfc01228: afc2002c sw v0,44(s8) +bfc0122c: 0bf0049b j bfc0126c +bfc01230: 00000000 nop +bfc01234: 8fc3002c lw v1,44(s8) +bfc01238: 8fc2000c lw v0,12(s8) bfc0123c: 00000000 nop -bfc01240: 0441ffed bgez v0,bfc011f8 -bfc01244: 00000000 nop -bfc01248: 8fc20024 lw v0,36(s8) +bfc01240: 00431021 addu v0,v0,v1 +bfc01244: 90430000 lbu v1,0(v0) +bfc01248: 8fc2002c lw v0,44(s8) bfc0124c: 00000000 nop -bfc01250: 24420001 addiu v0,v0,1 -bfc01254: afc20024 sw v0,36(s8) -bfc01258: 8fc20024 lw v0,36(s8) -bfc0125c: 00000000 nop -bfc01260: 10400007 beqz v0,bfc01280 -bfc01264: 00000000 nop -bfc01268: 3c02bfc0 lui v0,0xbfc0 -bfc0126c: 24441694 addiu a0,v0,5780 -bfc01270: 0ff00186 jal bfc00618 -bfc01274: 00000000 nop -bfc01278: 0bf004a4 j bfc01290 -bfc0127c: 00000000 nop -bfc01280: 3c02bfc0 lui v0,0xbfc0 -bfc01284: 244416a0 addiu a0,v0,5792 -bfc01288: 0ff00186 jal bfc00618 -bfc0128c: 00000000 nop -bfc01290: 3c02bfc0 lui v0,0xbfc0 -bfc01294: 244416e4 addiu a0,v0,5860 -bfc01298: 0ff00186 jal bfc00618 -bfc0129c: 00000000 nop -bfc012a0: afc00024 sw zero,36(s8) -bfc012a4: 0bf004b8 j bfc012e0 +bfc01250: 304200ff andi v0,v0,0xff +bfc01254: 14620009 bne v1,v0,bfc0127c +bfc01258: 00000000 nop +bfc0125c: 8fc2002c lw v0,44(s8) +bfc01260: 00000000 nop +bfc01264: 2442ffff addiu v0,v0,-1 +bfc01268: afc2002c sw v0,44(s8) +bfc0126c: 8fc2002c lw v0,44(s8) +bfc01270: 00000000 nop +bfc01274: 0441ffef bgez v0,bfc01234 +bfc01278: 00000000 nop +bfc0127c: 8fc2002c lw v0,44(s8) +bfc01280: 00000000 nop +bfc01284: 24420001 addiu v0,v0,1 +bfc01288: afc2002c sw v0,44(s8) +bfc0128c: 8fc2002c lw v0,44(s8) +bfc01290: 00000000 nop +bfc01294: 10400007 beqz v0,bfc012b4 +bfc01298: 00000000 nop +bfc0129c: 3c02bfc0 lui v0,0xbfc0 +bfc012a0: 244417fc addiu a0,v0,6140 +bfc012a4: 0ff0017e jal bfc005f8 bfc012a8: 00000000 nop -bfc012ac: 8fc20024 lw v0,36(s8) +bfc012ac: 0bf004b1 j bfc012c4 bfc012b0: 00000000 nop -bfc012b4: 00021880 sll v1,v0,0x2 -bfc012b8: 8fc20004 lw v0,4(s8) -bfc012bc: 00000000 nop -bfc012c0: 00431821 addu v1,v0,v1 -bfc012c4: 8fc20024 lw v0,36(s8) -bfc012c8: 00000000 nop -bfc012cc: ac620000 sw v0,0(v1) -bfc012d0: 8fc20024 lw v0,36(s8) -bfc012d4: 00000000 nop -bfc012d8: 24420001 addiu v0,v0,1 -bfc012dc: afc20024 sw v0,36(s8) -bfc012e0: 8fc20024 lw v0,36(s8) -bfc012e4: 3c030010 lui v1,0x10 -bfc012e8: 0043102a slt v0,v0,v1 -bfc012ec: 1440ffef bnez v0,bfc012ac +bfc012b4: 3c02bfc0 lui v0,0xbfc0 +bfc012b8: 24441808 addiu a0,v0,6152 +bfc012bc: 0ff0017e jal bfc005f8 +bfc012c0: 00000000 nop +bfc012c4: 3c02bfc0 lui v0,0xbfc0 +bfc012c8: 24441814 addiu a0,v0,6164 +bfc012cc: 0ff0017e jal bfc005f8 +bfc012d0: 00000000 nop +bfc012d4: afc0002c sw zero,44(s8) +bfc012d8: 0bf004c6 j bfc01318 +bfc012dc: 00000000 nop +bfc012e0: 8fc2002c lw v0,44(s8) +bfc012e4: 00000000 nop +bfc012e8: 00021840 sll v1,v0,0x1 +bfc012ec: 8fc20008 lw v0,8(s8) bfc012f0: 00000000 nop -bfc012f4: 3c02bfc0 lui v0,0xbfc0 -bfc012f8: 24441670 addiu a0,v0,5744 -bfc012fc: 0ff00186 jal bfc00618 -bfc01300: 00000000 nop -bfc01304: 3c02bfc0 lui v0,0xbfc0 -bfc01308: 24441700 addiu a0,v0,5888 -bfc0130c: 0ff00186 jal bfc00618 -bfc01310: 00000000 nop -bfc01314: 3c02000f lui v0,0xf -bfc01318: 3442ffff ori v0,v0,0xffff -bfc0131c: afc20024 sw v0,36(s8) -bfc01320: 0bf004d9 j bfc01364 -bfc01324: 00000000 nop -bfc01328: 8fc20024 lw v0,36(s8) -bfc0132c: 00000000 nop -bfc01330: 00021880 sll v1,v0,0x2 -bfc01334: 8fc20004 lw v0,4(s8) +bfc012f4: 00431821 addu v1,v0,v1 +bfc012f8: 8fc2002c lw v0,44(s8) +bfc012fc: 00000000 nop +bfc01300: 3042ffff andi v0,v0,0xffff +bfc01304: a4620000 sh v0,0(v1) +bfc01308: 8fc2002c lw v0,44(s8) +bfc0130c: 00000000 nop +bfc01310: 24420001 addiu v0,v0,1 +bfc01314: afc2002c sw v0,44(s8) +bfc01318: 8fc2002c lw v0,44(s8) +bfc0131c: 3c030020 lui v1,0x20 +bfc01320: 0043102a slt v0,v0,v1 +bfc01324: 1440ffee bnez v0,bfc012e0 +bfc01328: 00000000 nop +bfc0132c: 3c02bfc0 lui v0,0xbfc0 +bfc01330: 244417d8 addiu a0,v0,6104 +bfc01334: 0ff0017e jal bfc005f8 bfc01338: 00000000 nop -bfc0133c: 00431021 addu v0,v0,v1 -bfc01340: 8c430000 lw v1,0(v0) -bfc01344: 8fc20024 lw v0,36(s8) +bfc0133c: 3c02bfc0 lui v0,0xbfc0 +bfc01340: 24441830 addiu a0,v0,6192 +bfc01344: 0ff0017e jal bfc005f8 bfc01348: 00000000 nop -bfc0134c: 14620009 bne v1,v0,bfc01374 -bfc01350: 00000000 nop -bfc01354: 8fc20024 lw v0,36(s8) -bfc01358: 00000000 nop -bfc0135c: 2442ffff addiu v0,v0,-1 -bfc01360: afc20024 sw v0,36(s8) -bfc01364: 8fc20024 lw v0,36(s8) -bfc01368: 00000000 nop -bfc0136c: 0441ffee bgez v0,bfc01328 +bfc0134c: 3c02001f lui v0,0x1f +bfc01350: 3442ffff ori v0,v0,0xffff +bfc01354: afc2002c sw v0,44(s8) +bfc01358: 0bf004e8 j bfc013a0 +bfc0135c: 00000000 nop +bfc01360: 8fc2002c lw v0,44(s8) +bfc01364: 00000000 nop +bfc01368: 00021840 sll v1,v0,0x1 +bfc0136c: 8fc20008 lw v0,8(s8) bfc01370: 00000000 nop -bfc01374: 8fc20024 lw v0,36(s8) -bfc01378: 00000000 nop -bfc0137c: 24420001 addiu v0,v0,1 -bfc01380: afc20024 sw v0,36(s8) -bfc01384: 8fc20024 lw v0,36(s8) -bfc01388: 00000000 nop -bfc0138c: 10400007 beqz v0,bfc013ac -bfc01390: 00000000 nop -bfc01394: 3c02bfc0 lui v0,0xbfc0 -bfc01398: 24441694 addiu a0,v0,5780 -bfc0139c: 0ff00186 jal bfc00618 -bfc013a0: 00000000 nop -bfc013a4: 0bf004ef j bfc013bc -bfc013a8: 00000000 nop -bfc013ac: 3c02bfc0 lui v0,0xbfc0 -bfc013b0: 244416a0 addiu a0,v0,5792 -bfc013b4: 0ff00186 jal bfc00618 -bfc013b8: 00000000 nop -bfc013bc: afc00024 sw zero,36(s8) -bfc013c0: 0bf004fd j bfc013f4 +bfc01374: 00431021 addu v0,v0,v1 +bfc01378: 94430000 lhu v1,0(v0) +bfc0137c: 8fc2002c lw v0,44(s8) +bfc01380: 00000000 nop +bfc01384: 3042ffff andi v0,v0,0xffff +bfc01388: 14620009 bne v1,v0,bfc013b0 +bfc0138c: 00000000 nop +bfc01390: 8fc2002c lw v0,44(s8) +bfc01394: 00000000 nop +bfc01398: 2442ffff addiu v0,v0,-1 +bfc0139c: afc2002c sw v0,44(s8) +bfc013a0: 8fc2002c lw v0,44(s8) +bfc013a4: 00000000 nop +bfc013a8: 0441ffed bgez v0,bfc01360 +bfc013ac: 00000000 nop +bfc013b0: 8fc2002c lw v0,44(s8) +bfc013b4: 00000000 nop +bfc013b8: 24420001 addiu v0,v0,1 +bfc013bc: afc2002c sw v0,44(s8) +bfc013c0: 8fc2002c lw v0,44(s8) bfc013c4: 00000000 nop -bfc013c8: 8fc20024 lw v0,36(s8) +bfc013c8: 10400007 beqz v0,bfc013e8 bfc013cc: 00000000 nop -bfc013d0: 00021880 sll v1,v0,0x2 -bfc013d4: 8fc20004 lw v0,4(s8) -bfc013d8: 00000000 nop -bfc013dc: 00431021 addu v0,v0,v1 -bfc013e0: ac400000 sw zero,0(v0) -bfc013e4: 8fc20024 lw v0,36(s8) -bfc013e8: 00000000 nop -bfc013ec: 24420001 addiu v0,v0,1 -bfc013f0: afc20024 sw v0,36(s8) -bfc013f4: 8fc20024 lw v0,36(s8) -bfc013f8: 3c030010 lui v1,0x10 -bfc013fc: 0043102a slt v0,v0,v1 -bfc01400: 1440fff1 bnez v0,bfc013c8 +bfc013d0: 3c02bfc0 lui v0,0xbfc0 +bfc013d4: 244417fc addiu a0,v0,6140 +bfc013d8: 0ff0017e jal bfc005f8 +bfc013dc: 00000000 nop +bfc013e0: 0bf004fe j bfc013f8 +bfc013e4: 00000000 nop +bfc013e8: 3c02bfc0 lui v0,0xbfc0 +bfc013ec: 24441808 addiu a0,v0,6152 +bfc013f0: 0ff0017e jal bfc005f8 +bfc013f4: 00000000 nop +bfc013f8: 3c02bfc0 lui v0,0xbfc0 +bfc013fc: 2444184c addiu a0,v0,6220 +bfc01400: 0ff0017e jal bfc005f8 bfc01404: 00000000 nop -bfc01408: 8fc40000 lw a0,0(s8) -bfc0140c: 0ff00186 jal bfc00618 +bfc01408: afc0002c sw zero,44(s8) +bfc0140c: 0bf00512 j bfc01448 bfc01410: 00000000 nop -bfc01414: 27c2002c addiu v0,s8,44 -bfc01418: 00402021 move a0,v0 -bfc0141c: 0ff00330 jal bfc00cc0 -bfc01420: 00000000 nop -bfc01424: afc20028 sw v0,40(s8) -bfc01428: 27c2012c addiu v0,s8,300 -bfc0142c: 27c3002c addiu v1,s8,44 -bfc01430: 00402021 move a0,v0 -bfc01434: 00602821 move a1,v1 -bfc01438: 8fc60028 lw a2,40(s8) -bfc0143c: 0ff0023c jal bfc008f0 -bfc01440: 00000000 nop -bfc01444: afc20028 sw v0,40(s8) -bfc01448: 8fc2001c lw v0,28(s8) -bfc0144c: 00000000 nop -bfc01450: ac400000 sw zero,0(v0) -bfc01454: 8fc20028 lw v0,40(s8) +bfc01414: 8fc2002c lw v0,44(s8) +bfc01418: 00000000 nop +bfc0141c: 00021880 sll v1,v0,0x2 +bfc01420: 8fc20004 lw v0,4(s8) +bfc01424: 00000000 nop +bfc01428: 00431821 addu v1,v0,v1 +bfc0142c: 8fc2002c lw v0,44(s8) +bfc01430: 00000000 nop +bfc01434: ac620000 sw v0,0(v1) +bfc01438: 8fc2002c lw v0,44(s8) +bfc0143c: 00000000 nop +bfc01440: 24420001 addiu v0,v0,1 +bfc01444: afc2002c sw v0,44(s8) +bfc01448: 8fc2002c lw v0,44(s8) +bfc0144c: 3c030010 lui v1,0x10 +bfc01450: 0043102a slt v0,v0,v1 +bfc01454: 1440ffef bnez v0,bfc01414 bfc01458: 00000000 nop -bfc0145c: afc20148 sw v0,328(s8) -bfc01460: 24020002 li v0,2 -bfc01464: 8fc30148 lw v1,328(s8) +bfc0145c: 3c02bfc0 lui v0,0xbfc0 +bfc01460: 244417d8 addiu a0,v0,6104 +bfc01464: 0ff0017e jal bfc005f8 bfc01468: 00000000 nop -bfc0146c: 10620008 beq v1,v0,bfc01490 -bfc01470: 00000000 nop -bfc01474: 24020004 li v0,4 -bfc01478: 8fc30148 lw v1,328(s8) -bfc0147c: 00000000 nop -bfc01480: 1062002f beq v1,v0,bfc01540 -bfc01484: 00000000 nop -bfc01488: 0bf0056b j bfc015ac +bfc0146c: 3c02bfc0 lui v0,0xbfc0 +bfc01470: 24441868 addiu a0,v0,6248 +bfc01474: 0ff0017e jal bfc005f8 +bfc01478: 00000000 nop +bfc0147c: 3c02000f lui v0,0xf +bfc01480: 3442ffff ori v0,v0,0xffff +bfc01484: afc2002c sw v0,44(s8) +bfc01488: 0bf00533 j bfc014cc bfc0148c: 00000000 nop -bfc01490: 8fc3012c lw v1,300(s8) -bfc01494: 8fc20130 lw v0,304(s8) -bfc01498: 00000000 nop -bfc0149c: 00621821 addu v1,v1,v0 -bfc014a0: 8fc20020 lw v0,32(s8) -bfc014a4: 00000000 nop -bfc014a8: 0043102b sltu v0,v0,v1 -bfc014ac: 10400006 beqz v0,bfc014c8 +bfc01490: 8fc2002c lw v0,44(s8) +bfc01494: 00000000 nop +bfc01498: 00021880 sll v1,v0,0x2 +bfc0149c: 8fc20004 lw v0,4(s8) +bfc014a0: 00000000 nop +bfc014a4: 00431021 addu v0,v0,v1 +bfc014a8: 8c430000 lw v1,0(v0) +bfc014ac: 8fc2002c lw v0,44(s8) bfc014b0: 00000000 nop -bfc014b4: 8fc2012c lw v0,300(s8) -bfc014b8: 8fc30130 lw v1,304(s8) -bfc014bc: 00000000 nop -bfc014c0: 00431021 addu v0,v0,v1 -bfc014c4: afc20020 sw v0,32(s8) -bfc014c8: 8fc2012c lw v0,300(s8) -bfc014cc: 00000000 nop -bfc014d0: afc20018 sw v0,24(s8) -bfc014d4: afc00024 sw zero,36(s8) -bfc014d8: 0bf00548 j bfc01520 -bfc014dc: 00000000 nop -bfc014e0: 8fc30138 lw v1,312(s8) -bfc014e4: 8fc20024 lw v0,36(s8) -bfc014e8: 00000000 nop -bfc014ec: 00621021 addu v0,v1,v0 -bfc014f0: 90430000 lbu v1,0(v0) -bfc014f4: 8fc20018 lw v0,24(s8) +bfc014b4: 14620009 bne v1,v0,bfc014dc +bfc014b8: 00000000 nop +bfc014bc: 8fc2002c lw v0,44(s8) +bfc014c0: 00000000 nop +bfc014c4: 2442ffff addiu v0,v0,-1 +bfc014c8: afc2002c sw v0,44(s8) +bfc014cc: 8fc2002c lw v0,44(s8) +bfc014d0: 00000000 nop +bfc014d4: 0441ffee bgez v0,bfc01490 +bfc014d8: 00000000 nop +bfc014dc: 8fc2002c lw v0,44(s8) +bfc014e0: 00000000 nop +bfc014e4: 24420001 addiu v0,v0,1 +bfc014e8: afc2002c sw v0,44(s8) +bfc014ec: 8fc2002c lw v0,44(s8) +bfc014f0: 00000000 nop +bfc014f4: 10400007 beqz v0,bfc01514 bfc014f8: 00000000 nop -bfc014fc: a0430000 sb v1,0(v0) -bfc01500: 8fc20018 lw v0,24(s8) -bfc01504: 00000000 nop -bfc01508: 24420001 addiu v0,v0,1 -bfc0150c: afc20018 sw v0,24(s8) -bfc01510: 8fc20024 lw v0,36(s8) -bfc01514: 00000000 nop -bfc01518: 24420001 addiu v0,v0,1 -bfc0151c: afc20024 sw v0,36(s8) -bfc01520: 8fc20024 lw v0,36(s8) -bfc01524: 8fc30130 lw v1,304(s8) -bfc01528: 00000000 nop -bfc0152c: 0043102b sltu v0,v0,v1 -bfc01530: 1440ffeb bnez v0,bfc014e0 +bfc014fc: 3c02bfc0 lui v0,0xbfc0 +bfc01500: 244417fc addiu a0,v0,6140 +bfc01504: 0ff0017e jal bfc005f8 +bfc01508: 00000000 nop +bfc0150c: 0bf00549 j bfc01524 +bfc01510: 00000000 nop +bfc01514: 3c02bfc0 lui v0,0xbfc0 +bfc01518: 24441808 addiu a0,v0,6152 +bfc0151c: 0ff0017e jal bfc005f8 +bfc01520: 00000000 nop +bfc01524: afc0002c sw zero,44(s8) +bfc01528: 0bf00557 j bfc0155c +bfc0152c: 00000000 nop +bfc01530: 8fc2002c lw v0,44(s8) bfc01534: 00000000 nop -bfc01538: 0bf0056b j bfc015ac -bfc0153c: 00000000 nop -bfc01540: 8fc3001c lw v1,28(s8) -bfc01544: 24020001 li v0,1 -bfc01548: ac620000 sw v0,0(v1) -bfc0154c: 8fc2012c lw v0,300(s8) +bfc01538: 00021880 sll v1,v0,0x2 +bfc0153c: 8fc20004 lw v0,4(s8) +bfc01540: 00000000 nop +bfc01544: 00431021 addu v0,v0,v1 +bfc01548: ac400000 sw zero,0(v0) +bfc0154c: 8fc2002c lw v0,44(s8) bfc01550: 00000000 nop -bfc01554: 00402021 move a0,v0 -bfc01558: 0ff001e0 jal bfc00780 -bfc0155c: 00000000 nop -bfc01560: 3c02bfc0 lui v0,0xbfc0 -bfc01564: 2444171c addiu a0,v0,5916 -bfc01568: 0ff00186 jal bfc00618 +bfc01554: 24420001 addiu v0,v0,1 +bfc01558: afc2002c sw v0,44(s8) +bfc0155c: 8fc2002c lw v0,44(s8) +bfc01560: 3c030010 lui v1,0x10 +bfc01564: 0043102a slt v0,v0,v1 +bfc01568: 1440fff1 bnez v0,bfc01530 bfc0156c: 00000000 nop -bfc01570: 8fc20020 lw v0,32(s8) -bfc01574: 00000000 nop -bfc01578: 2442fffc addiu v0,v0,-4 -bfc0157c: 00402021 move a0,v0 -bfc01580: 0ff001e0 jal bfc00780 -bfc01584: 00000000 nop -bfc01588: 3c02bfc0 lui v0,0xbfc0 -bfc0158c: 24441724 addiu a0,v0,5924 -bfc01590: 0ff00186 jal bfc00618 -bfc01594: 00000000 nop -bfc01598: 8fc2012c lw v0,300(s8) -bfc0159c: 00000000 nop -bfc015a0: 00402021 move a0,v0 -bfc015a4: 0ff00360 jal bfc00d80 +bfc01570: 8fc40000 lw a0,0(s8) +bfc01574: 0ff0017e jal bfc005f8 +bfc01578: 00000000 nop +bfc0157c: 27c20034 addiu v0,s8,52 +bfc01580: 00402021 move a0,v0 +bfc01584: 0ff00328 jal bfc00ca0 +bfc01588: 00000000 nop +bfc0158c: afc20030 sw v0,48(s8) +bfc01590: 27c20134 addiu v0,s8,308 +bfc01594: 27c30034 addiu v1,s8,52 +bfc01598: 00402021 move a0,v0 +bfc0159c: 00602821 move a1,v1 +bfc015a0: 8fc60030 lw a2,48(s8) +bfc015a4: 0ff00234 jal bfc008d0 bfc015a8: 00000000 nop -bfc015ac: 8fc20028 lw v0,40(s8) -bfc015b0: 00000000 nop -bfc015b4: 1440ff97 bnez v0,bfc01414 -bfc015b8: 00000000 nop -bfc015bc: 8fc3001c lw v1,28(s8) -bfc015c0: 3c024000 lui v0,0x4000 -bfc015c4: ac620000 sw v0,0(v1) -bfc015c8: 0bf00502 j bfc01408 -bfc015cc: 00000000 nop +bfc015ac: afc20030 sw v0,48(s8) +bfc015b0: 8fc20024 lw v0,36(s8) +bfc015b4: 00000000 nop +bfc015b8: ac400000 sw zero,0(v0) +bfc015bc: 8fc20030 lw v0,48(s8) +bfc015c0: 00000000 nop +bfc015c4: afc20150 sw v0,336(s8) +bfc015c8: 24020002 li v0,2 +bfc015cc: 8fc30150 lw v1,336(s8) +bfc015d0: 00000000 nop +bfc015d4: 10620008 beq v1,v0,bfc015f8 +bfc015d8: 00000000 nop +bfc015dc: 24020004 li v0,4 +bfc015e0: 8fc30150 lw v1,336(s8) +bfc015e4: 00000000 nop +bfc015e8: 1062002f beq v1,v0,bfc016a8 +bfc015ec: 00000000 nop +bfc015f0: 0bf005c5 j bfc01714 +bfc015f4: 00000000 nop +bfc015f8: 8fc30134 lw v1,308(s8) +bfc015fc: 8fc20138 lw v0,312(s8) +bfc01600: 00000000 nop +bfc01604: 00621821 addu v1,v1,v0 +bfc01608: 8fc20028 lw v0,40(s8) +bfc0160c: 00000000 nop +bfc01610: 0043102b sltu v0,v0,v1 +bfc01614: 10400006 beqz v0,bfc01630 +bfc01618: 00000000 nop +bfc0161c: 8fc20134 lw v0,308(s8) +bfc01620: 8fc30138 lw v1,312(s8) +bfc01624: 00000000 nop +bfc01628: 00431021 addu v0,v0,v1 +bfc0162c: afc20028 sw v0,40(s8) +bfc01630: 8fc20134 lw v0,308(s8) +bfc01634: 00000000 nop +bfc01638: afc20020 sw v0,32(s8) +bfc0163c: afc0002c sw zero,44(s8) +bfc01640: 0bf005a2 j bfc01688 +bfc01644: 00000000 nop +bfc01648: 8fc30140 lw v1,320(s8) +bfc0164c: 8fc2002c lw v0,44(s8) +bfc01650: 00000000 nop +bfc01654: 00621021 addu v0,v1,v0 +bfc01658: 90430000 lbu v1,0(v0) +bfc0165c: 8fc20020 lw v0,32(s8) +bfc01660: 00000000 nop +bfc01664: a0430000 sb v1,0(v0) +bfc01668: 8fc20020 lw v0,32(s8) +bfc0166c: 00000000 nop +bfc01670: 24420001 addiu v0,v0,1 +bfc01674: afc20020 sw v0,32(s8) +bfc01678: 8fc2002c lw v0,44(s8) +bfc0167c: 00000000 nop +bfc01680: 24420001 addiu v0,v0,1 +bfc01684: afc2002c sw v0,44(s8) +bfc01688: 8fc2002c lw v0,44(s8) +bfc0168c: 8fc30138 lw v1,312(s8) +bfc01690: 00000000 nop +bfc01694: 0043102b sltu v0,v0,v1 +bfc01698: 1440ffeb bnez v0,bfc01648 +bfc0169c: 00000000 nop +bfc016a0: 0bf005c5 j bfc01714 +bfc016a4: 00000000 nop +bfc016a8: 8fc30024 lw v1,36(s8) +bfc016ac: 24020001 li v0,1 +bfc016b0: ac620000 sw v0,0(v1) +bfc016b4: 8fc20134 lw v0,308(s8) +bfc016b8: 00000000 nop +bfc016bc: 00402021 move a0,v0 +bfc016c0: 0ff001d8 jal bfc00760 +bfc016c4: 00000000 nop +bfc016c8: 3c02bfc0 lui v0,0xbfc0 +bfc016cc: 24441884 addiu a0,v0,6276 +bfc016d0: 0ff0017e jal bfc005f8 +bfc016d4: 00000000 nop +bfc016d8: 8fc20028 lw v0,40(s8) +bfc016dc: 00000000 nop +bfc016e0: 2442fffc addiu v0,v0,-4 +bfc016e4: 00402021 move a0,v0 +bfc016e8: 0ff001d8 jal bfc00760 +bfc016ec: 00000000 nop +bfc016f0: 3c02bfc0 lui v0,0xbfc0 +bfc016f4: 2444188c addiu a0,v0,6284 +bfc016f8: 0ff0017e jal bfc005f8 +bfc016fc: 00000000 nop +bfc01700: 8fc20134 lw v0,308(s8) +bfc01704: 00000000 nop +bfc01708: 00402021 move a0,v0 +bfc0170c: 0ff00358 jal bfc00d60 +bfc01710: 00000000 nop +bfc01714: 8fc20030 lw v0,48(s8) +bfc01718: 00000000 nop +bfc0171c: 1440ff97 bnez v0,bfc0157c +bfc01720: 00000000 nop +bfc01724: 8fc30024 lw v1,36(s8) +bfc01728: 3c024000 lui v0,0x4000 +bfc0172c: ac620000 sw v0,0(v1) +bfc01730: 0bf0055c j bfc01570 +bfc01734: 00000000 nop diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index 222160a..51a320c 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -35,6 +35,8 @@ use work.mips_types.all; --use work.fifo_ctrl_pkg.all; use work.sdram_config.all; use work.sdram_types.all; +use work.sys_types.all; + ENTITY mips_sys IS GENERIC @@ -88,6 +90,21 @@ PORT -- sys_vga_vsync : out std_logic; -- sys_vga_clk : out std_logic; + sys_usb_d : inout unsigned(15 downto 0); + sys_usb_a : out unsigned(1 downto 0); + sys_usb_csn : out std_logic; + sys_usb_wrn : out std_logic; + sys_usb_rdn : out std_logic; + sys_usb_rstn : out std_logic; + sys_usb_int : in std_logic; + + sys_flash_d : inout unsigned(31 downto 0); + sys_flash_a : out unsigned(24 downto 0); + sys_flash_ce : out std_logic; + sys_flash_wrn : out std_logic; + sys_flash_rdn : out std_logic; + sys_flash_rstn : out std_logic; + sys_flash_byten : out std_logic; sys_error : out unsigned(1 downto 0) -- indicates Errors ); @@ -102,580 +119,562 @@ ARCHITECTURE behavior OF mips_sys IS COMPONENT mips_top Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - int : in unsigned(5 downto 0); - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_re : out STD_LOGIC; - mem_en : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_din : in word_t; - mem_dout : out word_t; - mem_addr : out word_t + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + DAT_O : out word_t; + WE_O : out STD_LOGIC; + SEL_O : out unsigned(3 downto 0); + CYC_O : out STD_LOGIC; + STB_O : out STD_LOGIC; + MRDY_O : out STD_LOGIC; + INT : in unsigned (5 downto 0) ); END COMPONENT; - signal int : unsigned(5 downto 0); - signal mem_din : word_t; - signal mem_dout : word_t; - signal mem_addr : word_t; - signal mem_re : std_logic; - signal mem_en : std_logic; - signal mem_we : unsigned(3 downto 0); - signal mem_valid : std_logic; - signal mem_rdy : std_logic; - COMPONENT rom - Port + COMPONENT rom_wb + PORT ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in word_t; - dout : out word_t + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + SRDY_O : out STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0) ); END COMPONENT; - signal rom_data : word_t; - COMPONENT ram - PORT - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); + COMPONENT ram_wb + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0) + ); END COMPONENT; - signal ram_data : word_t; COMPONENT lcd_port - PORT ( - rst : in std_logic; - clk : in std_logic; - we : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - lcd_d : inout unsigned(3 downto 0); - lcd_e : out std_logic; - lcd_rs : out std_logic; - lcd_rw : out std_logic - ); - END COMPONENT; - - COMPONENT uart_tx - Port - ( - data_in : in std_logic_vector(7 downto 0); - write_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic - ); - END COMPONENT; - - COMPONENT uart_rx - Port + PORT ( - serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - read_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - buffer_data_present : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic + rst : in std_logic; + clk : in std_logic; + we : in std_logic; + din : in unsigned(7 downto 0); + dout : out unsigned(7 downto 0); + lcd_d : inout unsigned(3 downto 0); + lcd_e : out std_logic; + lcd_rs : out std_logic; + lcd_rw : out std_logic ); END COMPONENT; - signal rst : std_logic; - signal rst_in : std_logic; - signal started_up : std_logic := '1'; - signal clk : std_logic; + COMPONENT async_port_wb + GENERIC + ( + addr_width : natural := 32; + data_width : natural := 32; + async_timespec : async_timespec_t + ); + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + async_a : out unsigned(addr_width-1 downto 0); + async_d : inout unsigned(data_width-1 downto 0); + async_cs : out std_logic; + async_wr : out std_logic; + async_rd : out std_logic; + async_rst : out std_logic + ); + END COMPONENT; + COMPONENT uart_wb + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + INT_RX_O : out STD_LOGIC; + INT_TX_O : out STD_LOGIC; + ser_rx : in std_logic; + ser_tx : out std_logic + ); + END COMPONENT; - signal led_reg : unsigned(7 downto 0); - signal cpu_lcd_out_reg, cpu_lcd_in_reg, reg_uart_tx: unsigned(7 downto 0); - signal cpu_lcd_we : std_logic; - signal err_led_reg : unsigned(1 downto 0); - signal btn_ps2_reg : unsigned(7 downto 0); - - -- Signals to form an timer generating an interrupt every microsecond - subtype tick_usec_t is natural range 0 to 99; - signal tick_usec : tick_usec_t; - signal cnt_usec : word_t; - signal cnt_sec : word_t; - signal cnt_usec_preset : word_t; - signal cnt_sec_preset : word_t; - signal cnt_usec_en : std_logic; - signal cnt_usec_we : std_logic; - signal cnt_sec_en : std_logic; - signal cnt_sec_we : std_logic; - - -- Signals for UART connections - signal baud_count : unsigned(7 downto 0); - signal en_16_x_baud : std_logic; - signal reg_we_uart_tx : std_logic; - signal tx_full : std_logic; - signal tx_half_full : std_logic; - signal reg_re_uart_rx : std_logic; - signal reg_uart_rx : std_logic_vector(7 downto 0); - signal rx_data_present : std_logic; - signal rx_full : std_logic; - signal rx_half_full : std_logic; - signal uart_status_port : unsigned(7 downto 0); - signal reg_uart_ctrl : unsigned(7 downto 0); - signal reg_uart_baud : unsigned(7 downto 0); + COMPONENT gpio_wb + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + + sys_gpo0 : out unsigned(31 downto 0); + sys_gpo1 : out unsigned(31 downto 0); + sys_gpi0 : in unsigned(31 downto 0); + sys_gpi1 : in unsigned(31 downto 0) + ); + END COMPONENT; + + signal rst : std_logic; + signal clk : std_logic; + signal clk270 : std_logic; + signal clk270var : std_logic; + signal rst_in : std_logic; + signal int_uart_rx : std_logic; + signal locked : std_logic; + signal usb_addr : unsigned(31 downto 0); + signal flash_addr : unsigned(31 downto 0); + + -- J-Bus signals + signal INT : unsigned(5 downto 0); + signal DAT_I : word_t; + signal DAT_O : word_t; + signal ADDR_O : word_t; + signal SEL_O : unsigned(3 downto 0); + signal WE_O : std_logic; + signal CYC_O : std_logic; + signal STB_O : std_logic; + signal ACK_I : std_logic; + signal SRDY_I : std_logic; + signal MRDY_O : std_logic; + + signal CYC_O_flash : std_logic; + signal ACK_I_flash : std_logic; + signal SRDY_I_flash : std_logic; + signal DAT_I_flash : unsigned(31 downto 0); + + signal CYC_O_usb : std_logic; + signal ACK_I_usb : std_logic; + signal SRDY_I_usb : std_logic; + signal DAT_I_usb : unsigned(31 downto 0); + + signal CYC_O_sdram : std_logic; + signal ACK_I_sdram : std_logic; + signal SRDY_I_sdram : std_logic; + signal DAT_I_sdram : unsigned(31 downto 0); + + signal CYC_O_ram : std_logic; + signal ACK_I_ram : std_logic; + signal SRDY_I_ram : std_logic; + signal DAT_I_ram : unsigned(31 downto 0); + + signal CYC_O_rom : std_logic; + signal ACK_I_rom : std_logic; + signal SRDY_I_rom : std_logic; + signal DAT_I_rom : unsigned(31 downto 0); + + signal CYC_O_gpio : std_logic; + signal ACK_I_gpio : std_logic; + signal SRDY_I_gpio : std_logic; + signal DAT_I_gpio : unsigned(31 downto 0); + + signal CYC_O_urom : std_logic; + signal ACK_I_urom : std_logic; + signal SRDY_I_urom : std_logic; + signal DAT_I_urom : unsigned(31 downto 0); + + signal CYC_O_uart : std_logic; + signal ACK_I_uart : std_logic; + signal SRDY_I_uart : std_logic; + signal DAT_I_uart : unsigned(31 downto 0); + + signal gpo0 : unsigned(31 downto 0); + signal gpo1 : unsigned(31 downto 0); + signal gpi0 : unsigned(31 downto 0); + signal gpi1 : unsigned(31 downto 0); -- DDR SDRAM constant BURST_LEN : natural := 2; - signal sdr_addr : user_addr_t; - signal sdr_busy_q : std_logic; - signal sdr_udata_in : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal sdr_udata_out_q : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal sdr_udata_vld_q : std_logic; - signal sdr_be : unsigned(SDR_DM_WIDTH-1 downto 0) := "00000000"; - signal sdr_read : std_logic; - signal sdr_en : std_logic; - - signal reg_data : word_t; - signal reg_data_vld : std_logic; - signal reg_en : std_logic; - signal rom_en : std_logic; - signal rom_data_vld : std_logic; - signal ram_en : std_logic; - signal ram_data_vld : std_logic; - signal sdram_en : std_logic; - signal sd_counter : word_t; - signal mem_re_r : std_logic; - signal mem_we_r : unsigned(3 downto 0); - signal mem_dout_r : word_t; - signal mem_addr_r : word_t; -- attribute rom_style: string; -- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; + type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram); + signal mem_area : mem_area_t; + BEGIN - int <= "0000" & rx_data_present & btn_ps2_reg(4); - rst_in <= not (started_up and sys_rst_n_in); + gpi0(4 downto 0) <= sys_btn; + gpi1(7 downto 0) <= sys_dip; + sys_led <= gpo0(8 downto 0); + sys_error <= gpo0(31 downto 30); + int <= "000" & sys_usb_int & int_uart_rx & sys_btn(4); + rst_in <= not sys_rst_n_in; + rst <= not locked; + sys_usb_rstn <= not gpo1(0); + sys_flash_byten <= '1'; + usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2); + flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0'; + -en_mux: - process(clk) +mem_mux: + process(ADDR_O) begin - if rising_edge(clk) then - if rst = '1' then - sdram_en <= '0'; - else - reg_en <= '0'; - rom_en <= '0'; - ram_en <= '0'; --- sdram_en <= '0'; - - if mem_en = '1' then - mem_re_r <= mem_re; - mem_we_r <= mem_we; - mem_dout_r <= mem_dout; - mem_addr_r <= mem_addr; - if mem_addr(31 downto 28) = X"A" then - reg_en <= '1'; - elsif (mem_addr(31 downto 28) = X"B" and mem_addr(15) = '0') then - rom_en <= '1'; - elsif (mem_addr(31 downto 28) = X"B" and mem_addr(15) = '1') then - ram_en <= '1'; - elsif (mem_addr(31 downto 28) = X"8" or mem_addr(30) = '1') then - sdram_en <= '1'; - end if; - elsif sdr_busy_q = '0' then - sdram_en <= '0'; - end if; - end if; - end if; - end process; - - sdr_addr <= mem_addr_r(24 downto 2) & "0"; - sdr_udata_in <= mem_dout_r & mem_dout_r; - sdr_be <= mem_we_r & mem_we_r; - - sdr_read <= '1'; - sdr_en <= sdram_en and not sdr_busy_q; - ------------------------------------------------------------------- -led_out: - process(rst, clk) - begin - if rst = '1' then - sys_led <= (others => '0'); - sys_error <= (others => '0'); - elsif rising_edge(clk) then - sys_led <= not mem_rdy & led_reg; - sys_error <= err_led_reg; - end if; - end process; - ------------------------------------------------------------------- -btn_ps2_register: - process(clk) - begin - if rising_edge(clk) then - btn_ps2_reg <= "000" & unsigned(sys_btn); - end if; - end process; - -proc_sd_counter: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - sd_counter <= (others => '0'); - elsif sdr_udata_vld_q = '1' then - sd_counter <= sd_counter + 1; - end if; - end if; - end process; - - mem_valid <= sdr_udata_vld_q or reg_data_vld or rom_data_vld or ram_data_vld; - mem_din <= reg_data when reg_data_vld = '1' else - rom_data when rom_data_vld = '1' else - ram_data when ram_data_vld = '1' else - sdr_udata_out_q(mem_din'left downto mem_din'right); - ------------------------------------------------------------------- -inst_rom: rom - PORT MAP - ( - clk => clk, - ce => rom_en, - addr => mem_addr_r, - dout => rom_data - ); - -inst_ram: ram - PORT MAP - ( - clk => clk, - ce => ram_en, - we => mem_we_r, - addr => mem_addr_r, - din => mem_dout_r, - dout => ram_data - ); - - -ram_read: - process(clk) - begin - if rising_edge(clk) then - ram_data_vld <= '0'; - if ram_en = '1' and mem_re_r = '1' then - ram_data_vld <= '1'; - end if; - end if; - end process; - -rom_read: - process(clk) - begin - if rising_edge(clk) then - rom_data_vld <= '0'; - if rom_en = '1' and mem_re_r = '1' then - rom_data_vld <= '1'; - end if; - end if; - end process; - -registers_read: - process(clk) - begin - if rising_edge(clk) then - reg_data_vld <= '0'; - reg_re_uart_rx <= '0'; - if reg_en = '1' and mem_re_r = '1' then - reg_data_vld <= '1'; - reg_data <= (others => '0'); - case mem_addr_r(5 downto 2) is - - when "0000" => null; - - when "0001" => - reg_re_uart_rx <= mem_re_r; - reg_data(7 downto 0) <= unsigned(reg_uart_rx); - - when "0010" => - reg_data(7 downto 0) <= uart_status_port; - reg_data(15 downto 8) <= reg_uart_baud; - reg_data(23 downto 16) <= btn_ps2_reg; - reg_data(31 downto 24) <= cpu_lcd_in_reg; - - when "0100" => - reg_data <= cnt_usec; - - when "0101" => - reg_data <= cnt_sec; - - when others => null; - end case; - end if; - end if; - end process; - ------------------------------------------------------------------- -registers_write: - process(clk) - begin - if rising_edge(clk) then - cpu_lcd_we <= '0'; - reg_we_uart_tx <= '0'; - cnt_usec_we <= '0'; - cnt_sec_we <= '0'; - if rst = '1' then - led_reg <= (others => '0'); - err_led_reg <= (others => '0'); - cpu_lcd_out_reg <= (others => '0'); - reg_uart_baud <= to_unsigned(53, 8); - reg_uart_ctrl <= to_unsigned(0, 8); - elsif reg_en = '1' then - case mem_addr_r(5 downto 2) is - - when "0000" => - if mem_we_r(0) = '1' then - led_reg(7 downto 0) <= mem_dout_r(7 downto 0); - end if; - if mem_we_r(3) = '1' then - err_led_reg <= mem_dout_r(31 downto 30); - end if; - - when "0001" => - if mem_we_r(0) = '1' then - reg_we_uart_tx <= '1'; - reg_uart_tx <= mem_dout_r(7 downto 0); - end if; - - when "0010" => - if mem_we_r(0) = '1' then - reg_uart_ctrl <= mem_dout_r(7 downto 0); - end if; - if mem_we_r(1) = '1' then - reg_uart_baud <= mem_dout_r(15 downto 8); - end if; - if mem_we_r(3) = '1' then - cpu_lcd_we <= '1'; - cpu_lcd_out_reg <= mem_dout_r(31 downto 24); - end if; - - when "0100" => - if mem_we_r(3) = '1' then - cnt_usec_we <= '1'; - cnt_usec_preset <= mem_dout_r; - end if; - - when "0101" => - if mem_we_r(3) = '1' then - cnt_sec_we <= '1'; - cnt_sec_preset <= mem_dout_r; - end if; - - when others => null; - end case; + mem_area <= mem_dead; + if ADDR_O(31 downto 28) = X"0" then + mem_area <= mem_urom; + elsif ADDR_O(31 downto 28) = X"A" then + if ADDR_O(26) = '1' then + mem_area <= mem_flash; + elsif ADDR_O(17 downto 16) = "00" then + mem_area <= mem_gpio; + elsif ADDR_O(17 downto 16) = "01" then + mem_area <= mem_uart; + elsif ADDR_O(17 downto 16) = "10" then + mem_area <= mem_usb; end if; - end if; + elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then + mem_area <= mem_rom; + elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then + mem_area <= mem_ram; + elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then + mem_area <= mem_sdram; + end if; + end process; + +signal_mux: + process(mem_area, CYC_O) + begin + + CYC_O_urom <= '0'; + CYC_O_uart <= '0'; + CYC_O_gpio <= '0'; + CYC_O_flash <= '0'; + CYC_O_usb <= '0'; + CYC_O_rom <= '0'; + CYC_O_ram <= '0'; + CYC_O_sdram <= '0'; + + case mem_area is + + when mem_urom => + CYC_O_urom <= CYC_O; + + when mem_gpio => + CYC_O_gpio <= CYC_O; + + when mem_uart => + CYC_O_uart <= CYC_O; + + when mem_flash => + CYC_O_flash <= CYC_O; + + when mem_usb => + CYC_O_usb <= CYC_O; + + when mem_rom => + CYC_O_rom <= CYC_O; + + when mem_ram => + CYC_O_ram <= CYC_O; + + when mem_sdram => + CYC_O_sdram <= CYC_O; + + when others => null; + + end case; + + end process; + +-- sys_user_rom_addr <= ADDR_O; +-- sys_user_rom_clk <= clk; +-- sys_user_rom_en <= CYC_O_urom and STB_O; +-- DAT_I_urom <= sys_user_rom_din; + SRDY_I_urom <= CYC_O_urom; + +urom_ack_register: + process(clk) + begin + if rising_edge(clk) then + ACK_I_urom <= CYC_O_urom and STB_O; + end if; end process; ------------------------------------------------------------------ - mem_rdy <= not sdr_busy_q; + SRDY_I <= SRDY_I_flash or SRDY_I_usb or SRDY_I_sdram or SRDY_I_ram or SRDY_I_rom or SRDY_I_urom or SRDY_I_uart or SRDY_I_gpio; + ACK_I <= ACK_I_flash or ACK_I_usb or ACK_I_sdram or ACK_I_ram or ACK_I_rom or ACK_I_urom or ACK_I_uart or ACK_I_gpio; + DAT_I <= DAT_I_sdram when CYC_O_sdram = '1' else + DAT_I_ram when CYC_O_ram = '1' else + DAT_I_rom when CYC_O_rom = '1' else + DAT_I_urom when CYC_O_urom = '1' else + DAT_I_flash when CYC_O_flash = '1' else + DAT_I_usb when CYC_O_usb = '1' else + DAT_I_uart when CYC_O_uart = '1' else + DAT_I_gpio when CYC_O_gpio = '1' else X"DEADBEEF"; ------------------------------------------------------------------ inst_mips_top: mips_top PORT MAP ( - rst => rst, - clk => clk, - int => int, - mem_valid => mem_valid, - mem_rdy => mem_rdy, - mem_en => mem_en, - mem_re => mem_re, - mem_we => mem_we, - mem_din => mem_din, - mem_dout => mem_dout, - mem_addr => mem_addr + RST_I => rst, + CLK_I => clk, + ACK_I => ACK_I, + SRDY_I => SRDY_I, + MRDY_O => MRDY_O, + CYC_O => CYC_O, + STB_O => STB_O, + WE_O => WE_O, + SEL_O => SEL_O, + DAT_I => DAT_I, + DAT_O => DAT_O, + ADDR_O => ADDR_O, + INT => INT ); +inst_ram_wb : ram_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_ram, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I_ram, + SRDY_O => SRDY_I_ram, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I_ram + ); + +inst_rom_wb : rom_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_rom, + STB_I => STB_O, + ACK_O => ACK_I_rom, + MRDY_I => MRDY_O, + SRDY_O => SRDY_I_rom, + ADDR_I => ADDR_O, + DAT_O => DAT_I_rom + ); + + inst_lcd_port: lcd_port PORT MAP ( - rst => rst, clk => clk, - we => cpu_lcd_we, - din => cpu_lcd_out_reg, - dout => cpu_lcd_in_reg, + rst => rst, + we => '0', + din => X"00", + dout => open, lcd_d => sys_lcd_d, lcd_e => sys_lcd_e, lcd_rs => sys_lcd_rs, lcd_rw => sys_lcd_rw ); -inst_uart_tx: uart_tx - port map +inst_gpio_wb : gpio_wb + PORT MAP ( - data_in => std_logic_vector(reg_uart_tx), - write_buffer => reg_we_uart_tx, - reset_buffer => rst, - en_16_x_baud => en_16_x_baud, - serial_out => sys_tx, - buffer_full => tx_full, - buffer_half_full => tx_half_full, - clk => clk + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_gpio, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I_gpio, + SRDY_O => SRDY_I_gpio, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I_gpio, + + sys_gpo0 => gpo0, + sys_gpo1 => gpo1, + sys_gpi0 => gpi0, + sys_gpi1 => gpi1 ); - -inst_uart_rx: uart_rx - port map + + +inst_flash_port : async_port_wb + GENERIC MAP ( - serial_in => sys_rx, - data_out => reg_uart_rx, - read_buffer => reg_re_uart_rx, - reset_buffer => rst, - en_16_x_baud => en_16_x_baud, - buffer_data_present => rx_data_present, - buffer_full => rx_full, - buffer_half_full => rx_half_full, - clk => clk - ); - - uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; - -tick_usec_timer: - process(clk) - begin - if clk'event and clk='1' then - cnt_usec_en <= '0'; - if rst = '1' then - tick_usec <= 0; - cnt_usec_en <= '0'; - elsif tick_usec = tick_usec_t'high then - tick_usec <= 0; - cnt_usec_en <= '1'; - else - tick_usec <= tick_usec + 1; - end if; - end if; - end process; - -cnt_usec_timer: - process(clk) - begin - if clk'event and clk='1' then - cnt_sec_en <= '0'; - if rst = '1' then - cnt_usec <= (others => '0'); - cnt_sec_en <= '0'; - elsif cnt_usec_we = '1' then - cnt_usec <= cnt_usec_preset; - elsif cnt_usec_en = '1' then - if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then - cnt_usec <= (others => '0'); - cnt_sec_en <= '1'; - else - cnt_usec <= cnt_usec + 1; - end if; - end if; - end if; - end process; - -cnt_sec_timer: - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - cnt_sec <= (others => '0'); - elsif cnt_sec_we = '1' then - cnt_sec <= cnt_sec_preset; - elsif cnt_sec_en = '1' then - cnt_sec <= cnt_sec + 1; - end if; - end if; - end process; - -baud_timer: - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - baud_count <= (others => '0'); - elsif baud_count = reg_uart_baud then - baud_count <= (others => '0'); - en_16_x_baud <= '1'; - else - baud_count <= baud_count + 1; - en_16_x_baud <= '0'; - end if; - end if; - end process; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend - Generic map - ( - BL => BURST_LEN, - read_phaseshift => ddr_phaseshift, - f_sysclk => ddr_frequency_hz, - fifo_depth => 4 + addr_width => 25, + data_width => 32, + async_timespec => ts_flash ) - Port map + PORT MAP ( - - sys_rst_in => rst_in, - sys_clk_in => sys_clk_in, + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_flash, + STB_I => STB_O, + WE_I => WE_O, + ACK_O => ACK_I_flash, + SRDY_O => SRDY_I_flash, + MRDY_I => MRDY_O, + ADDR_I => flash_addr, + DAT_I => DAT_O, + DAT_O => DAT_I_flash, + async_a => sys_flash_a, + async_d => sys_flash_d, + async_cs => sys_flash_ce, + async_wr => sys_flash_wrn, + async_rd => sys_flash_rdn, + async_rst => sys_flash_rstn + ); - sys_rst_out => rst, - sys_clk_out => clk, - sys_clk_fb => sys_sdr_clk_fb, - - busy => sdr_busy_q, - en => sdr_en, - r_wn => mem_re_r, - be => sdr_be, - addr => sdr_addr, - din => sdr_udata_in, - dout => sdr_udata_out_q, - dout_re => sdr_read, - dout_vld => sdr_udata_vld_q, +inst_usb_port : async_port_wb + GENERIC MAP + ( + addr_width => 2, + data_width => 16, + async_timespec => ts_usb + ) + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_usb, + STB_I => STB_O, + WE_I => WE_O, + ACK_O => ACK_I_usb, + SRDY_O => SRDY_I_usb, + MRDY_I => MRDY_O, + ADDR_I => usb_addr, + DAT_I => DAT_O, + DAT_O => DAT_I_usb, + async_a => sys_usb_a, + async_d => sys_usb_d, + async_cs => sys_usb_csn, + async_wr => sys_usb_wrn, + async_rd => sys_usb_rdn, + async_rst => open + ); + +inst_uart_wb : uart_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_uart, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I_uart, + SRDY_O => SRDY_I_uart, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I_uart, + INT_RX_O => int_uart_rx, + INT_TX_O => open, + ser_rx => sys_rx, + ser_tx => sys_tx + ); + + +inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb + GENERIC MAP + ( + BL => BURST_LEN, + f_sysclk => ddr_frequency_hz, + fifo_depth => 4 + ) + PORT MAP + ( + RST_I => rst, + CLK_I => clk, + CLK270_I => clk270, + CLK270VAR_I => clk270var, + CYC_I => CYC_O_sdram, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I_sdram, + MRDY_I => MRDY_O, + SRDY_O => SRDY_I_sdram, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I_sdram, + -- SDRAM signals - sd_clk_p => sys_sdr_clk_p, - sd_clk_n => sys_sdr_clk_n, - sd_cke => sys_sdr_cke_q, - sd_cs_n => sys_sdr_cs_qn, - sd_cas_n => sys_sdr_cas_qn, - sd_ras_n => sys_sdr_ras_qn, - sd_we_n => sys_sdr_we_qn, - sd_addr => sys_sdr_a_q, - sd_ba => sys_sdr_ba_q, - sd_dm => sys_sdr_dm_q, - sd_dqs => sys_sdr_dqs_q, - sd_data => sys_sdr_data + sd_clk_p => sys_sdr_clk_p, + sd_clk_n => sys_sdr_clk_n, + sd_cke => sys_sdr_cke_q, + sd_cs_n => sys_sdr_cs_qn, + sd_cas_n => sys_sdr_cas_qn, + sd_ras_n => sys_sdr_ras_qn, + sd_we_n => sys_sdr_we_qn, + sd_addr => sys_sdr_a_q, + sd_ba => sys_sdr_ba_q, + sd_dm => sys_sdr_dm_q, + sd_dqs => sys_sdr_dqs_q, + sd_data => sys_sdr_data ); - STARTUP_VIRTEX4_inst : STARTUP_VIRTEX4 - port map ( - EOS => started_up, -- End of Startup 1-bit output - CLK => open, -- Clock input for start-up sequence - GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name) - GTS => '0', -- Global 3-state input (GTS cannot be used for the port name) - USRCCLKO => '0', -- USRCCLKO 1-bit input - USRCCLKTS => '0', -- USRCCLKTS 1-bit input - USRDONEO => '0', -- USRDONEO 1-bit input - USRDONETS => '0' -- USRDONETS 1-bit input +inst_clockgen : entity work.clockgen + GENERIC MAP + ( + sys1_phaseshift => 0, + frequency_hz => 100E6 + ) + PORT MAP + ( + -- Clocks and Reset + rst => rst_in, -- external async reset, low active + clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board + clk_fb_in => sys_sdr_clk_fb, -- feedback clock + sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° + sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° + sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0° + sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270° + locked_out => locked, -- DCM locked status + error_out => open ); - + ------------------------------------------------------------------ END; diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index 32e3976..bf7d752 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -35,6 +35,8 @@ use work.mips_types.all; --use work.fifo_ctrl_pkg.all; use work.sdram_config.all; use work.sdram_types.all; +use work.sys_types.all; + ENTITY mips_sys IS GENERIC @@ -94,6 +96,21 @@ PORT -- sys_vga_vsync : out std_logic; -- sys_vga_clk : out std_logic; + sys_usb_d : inout unsigned(15 downto 0); + sys_usb_a : out unsigned(1 downto 0); + sys_usb_csn : out std_logic; + sys_usb_wrn : out std_logic; + sys_usb_rdn : out std_logic; + sys_usb_rstn : out std_logic; + sys_usb_int : in std_logic; + + sys_flash_d : inout unsigned(31 downto 0); + sys_flash_a : out unsigned(24 downto 0); + sys_flash_ce : out std_logic; + sys_flash_wrn : out std_logic; + sys_flash_rdn : out std_logic; + sys_flash_rstn : out std_logic; + sys_flash_byten : out std_logic; sys_error : out unsigned(1 downto 0) -- indicates Errors ); @@ -108,608 +125,561 @@ ARCHITECTURE behavior OF mips_sys IS COMPONENT mips_top Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - int : in unsigned(5 downto 0); - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_re : out STD_LOGIC; - mem_en : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_din : in word_t; - mem_dout : out word_t; - mem_addr : out word_t + RST_I : in STD_LOGIC; + CLK_I : in STD_LOGIC; + ACK_I : in STD_LOGIC; + SRDY_I : in STD_LOGIC; + ADDR_O : out word_t; + DAT_I : in word_t; + DAT_O : out word_t; + WE_O : out STD_LOGIC; + SEL_O : out unsigned(3 downto 0); + CYC_O : out STD_LOGIC; + STB_O : out STD_LOGIC; + MRDY_O : out STD_LOGIC; + INT : in unsigned (5 downto 0) ); END COMPONENT; - signal int : unsigned(5 downto 0); - signal mem_din : word_t; - signal mem_dout : word_t; - signal mem_addr : word_t; - signal mem_re : std_logic; - signal mem_en : std_logic; - signal mem_we : unsigned(3 downto 0); - signal mem_valid : std_logic; - signal mem_rdy : std_logic; - COMPONENT rom - Port + COMPONENT rom_wb + PORT ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in word_t; - dout : out word_t + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + SRDY_O : out STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0) ); END COMPONENT; - signal rom_data : word_t; - COMPONENT ram - PORT - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); + COMPONENT ram_wb + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0) + ); END COMPONENT; - signal ram_data : word_t; COMPONENT lcd_port - PORT ( - rst : in std_logic; - clk : in std_logic; - we : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - lcd_d : inout unsigned(3 downto 0); - lcd_e : out std_logic; - lcd_rs : out std_logic; - lcd_rw : out std_logic - ); - END COMPONENT; - - COMPONENT uart_tx - Port - ( - data_in : in std_logic_vector(7 downto 0); - write_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic - ); - END COMPONENT; - - COMPONENT uart_rx - Port + PORT ( - serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - read_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - buffer_data_present : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic + rst : in std_logic; + clk : in std_logic; + we : in std_logic; + din : in unsigned(7 downto 0); + dout : out unsigned(7 downto 0); + lcd_d : inout unsigned(3 downto 0); + lcd_e : out std_logic; + lcd_rs : out std_logic; + lcd_rw : out std_logic ); END COMPONENT; - signal rst : std_logic; - signal rst_in : std_logic; - signal started_up : std_logic := '1'; - signal clk : std_logic; + COMPONENT async_port_wb + GENERIC + ( + addr_width : natural := 32; + data_width : natural := 32; + async_timespec : async_timespec_t + ); + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + async_a : out unsigned(addr_width-1 downto 0); + async_d : inout unsigned(data_width-1 downto 0); + async_cs : out std_logic; + async_wr : out std_logic; + async_rd : out std_logic; + async_rst : out std_logic + ); + END COMPONENT; + COMPONENT uart_wb + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + INT_RX_O : out STD_LOGIC; + INT_TX_O : out STD_LOGIC; + ser_rx : in std_logic; + ser_tx : out std_logic + ); + END COMPONENT; - signal led_reg : unsigned(7 downto 0); - signal cpu_lcd_out_reg, cpu_lcd_in_reg, reg_uart_tx: unsigned(7 downto 0); - signal cpu_lcd_we : std_logic; - signal err_led_reg : unsigned(1 downto 0); - signal btn_ps2_reg : unsigned(7 downto 0); - - -- Signals to form an timer generating an interrupt every microsecond - subtype tick_usec_t is natural range 0 to 99; - signal tick_usec : tick_usec_t; - signal cnt_usec : word_t; - signal cnt_sec : word_t; - signal cnt_usec_preset : word_t; - signal cnt_sec_preset : word_t; - signal cnt_usec_en : std_logic; - signal cnt_usec_we : std_logic; - signal cnt_sec_en : std_logic; - signal cnt_sec_we : std_logic; - - -- Signals for UART connections - signal baud_count : unsigned(7 downto 0); - signal en_16_x_baud : std_logic; - signal reg_we_uart_tx : std_logic; - signal tx_full : std_logic; - signal tx_half_full : std_logic; - signal reg_re_uart_rx : std_logic; - signal reg_uart_rx : std_logic_vector(7 downto 0); - signal rx_data_present : std_logic; - signal rx_full : std_logic; - signal rx_half_full : std_logic; - signal uart_status_port : unsigned(7 downto 0); - signal reg_uart_ctrl : unsigned(7 downto 0); - signal reg_uart_baud : unsigned(7 downto 0); + COMPONENT gpio_wb + PORT + ( + CLK_I : in STD_LOGIC; + RST_I : in STD_LOGIC; + CYC_I : in STD_LOGIC; + STB_I : in STD_LOGIC; + SEL_I : in unsigned(3 downto 0); + WE_I : in STD_LOGIC; + ACK_O : out STD_LOGIC; + SRDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + ADDR_I : in unsigned(31 downto 0); + DAT_I : in unsigned(31 downto 0); + DAT_O : out unsigned(31 downto 0); + + sys_gpo0 : out unsigned(31 downto 0); + sys_gpo1 : out unsigned(31 downto 0); + sys_gpi0 : in unsigned(31 downto 0); + sys_gpi1 : in unsigned(31 downto 0) + ); + END COMPONENT; + + signal rst : std_logic; + signal clk : std_logic; + signal clk270 : std_logic; + signal clk270var : std_logic; + signal rst_in : std_logic; + signal int_uart_rx : std_logic; + signal locked : std_logic; + signal usb_addr : unsigned(31 downto 0); + signal flash_addr : unsigned(31 downto 0); + + -- J-Bus signals + signal INT : unsigned(5 downto 0); + signal DAT_I : word_t; + signal DAT_O : word_t; + signal ADDR_O : word_t; + signal SEL_O : unsigned(3 downto 0); + signal WE_O : std_logic; + signal CYC_O : std_logic; + signal STB_O : std_logic; + signal ACK_I : std_logic; + signal SRDY_I : std_logic; + signal MRDY_O : std_logic; + + signal CYC_O_flash : std_logic; + signal ACK_I_flash : std_logic; + signal SRDY_I_flash : std_logic; + signal DAT_I_flash : unsigned(31 downto 0); + + signal CYC_O_usb : std_logic; + signal ACK_I_usb : std_logic; + signal SRDY_I_usb : std_logic; + signal DAT_I_usb : unsigned(31 downto 0); + + signal CYC_O_sdram : std_logic; + signal ACK_I_sdram : std_logic; + signal SRDY_I_sdram : std_logic; + signal DAT_I_sdram : unsigned(31 downto 0); + + signal CYC_O_ram : std_logic; + signal ACK_I_ram : std_logic; + signal SRDY_I_ram : std_logic; + signal DAT_I_ram : unsigned(31 downto 0); + + signal CYC_O_rom : std_logic; + signal ACK_I_rom : std_logic; + signal SRDY_I_rom : std_logic; + signal DAT_I_rom : unsigned(31 downto 0); + + signal CYC_O_gpio : std_logic; + signal ACK_I_gpio : std_logic; + signal SRDY_I_gpio : std_logic; + signal DAT_I_gpio : unsigned(31 downto 0); + + signal CYC_O_urom : std_logic; + signal ACK_I_urom : std_logic; + signal SRDY_I_urom : std_logic; + signal DAT_I_urom : unsigned(31 downto 0); + + signal CYC_O_uart : std_logic; + signal ACK_I_uart : std_logic; + signal SRDY_I_uart : std_logic; + signal DAT_I_uart : unsigned(31 downto 0); + + signal gpo0 : unsigned(31 downto 0); + signal gpo1 : unsigned(31 downto 0); + signal gpi0 : unsigned(31 downto 0); + signal gpi1 : unsigned(31 downto 0); -- DDR SDRAM constant BURST_LEN : natural := 2; - subtype sdr_buf_t is unsigned(SDR_DATA_WIDTH-1 downto 0); - signal sdr_buf_in, sdr_vga_data : sdr_buf_t := (others => '0'); - signal sdr_addr : user_addr_t; - signal sdr_busy_q : std_logic; - signal sdr_udata_in : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal sdr_udata_req_wr : std_logic; - signal sdr_udata_out_q : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal sdr_udata_vld_q : std_logic; - signal sdr_be : unsigned(SDR_DM_WIDTH-1 downto 0) := "00000000"; - signal sdr_read : std_logic; - signal sdr_en : std_logic; - - signal reg_data : word_t; - signal reg_data_vld : std_logic; - signal reg_en : std_logic; - signal rom_en : std_logic; - signal rom_data_vld : std_logic; - signal ram_en : std_logic; - signal ram_data_vld : std_logic; - signal urom_en : std_logic; - signal urom_data_vld : std_logic; - signal sdram_en : std_logic; - signal sd_counter : word_t; - signal mem_re_r : std_logic; - signal mem_we_r : unsigned(3 downto 0); - signal mem_dout_r : word_t; - signal mem_addr_r : word_t; -- attribute rom_style: string; -- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; -- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; - type sd_ctrl_state_t is (s_sd_idle, s_sd_cpu_read, s_sd_cpu_read_fin, s_sd_cpu_write, s_sd_cpu_write_fin); - signal st, stn : sd_ctrl_state_t; + type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram); + signal mem_area : mem_area_t; BEGIN - int <= "0000" & rx_data_present & btn_ps2_reg(4); - rst_in <= not (started_up and sys_rst_n_in); + gpi0(4 downto 0) <= sys_btn; + gpi1(7 downto 0) <= sys_dip; + sys_led <= gpo0(8 downto 0); + sys_error <= gpo0(31 downto 30); + int <= "000" & sys_usb_int & int_uart_rx & sys_btn(4); + rst_in <= not sys_rst_n_in; + rst <= not locked; + sys_usb_rstn <= not gpo1(0); + sys_flash_byten <= '1'; + usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2); + flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0'; + -en_mux: - process(clk) +mem_mux: + process(ADDR_O) begin - if rising_edge(clk) then - if rst = '1' then - sdram_en <= '0'; - else - urom_en <= '0'; - reg_en <= '0'; - rom_en <= '0'; - ram_en <= '0'; --- sdram_en <= '0'; - - if mem_en = '1' then - mem_re_r <= mem_re; - mem_we_r <= mem_we; - mem_dout_r <= mem_dout; - mem_addr_r <= mem_addr; - - if mem_addr(31 downto 28) = X"0" then - urom_en <= '1'; - elsif mem_addr(31 downto 28) = X"A" then - reg_en <= '1'; - elsif (mem_addr(31 downto 28) = X"B" and mem_addr(15) = '0') then - rom_en <= '1'; - elsif (mem_addr(31 downto 28) = X"B" and mem_addr(15) = '1') then - ram_en <= '1'; - elsif (mem_addr(31 downto 28) = X"8" or mem_addr(30) = '1') then - sdram_en <= '1'; - end if; - elsif sdr_en = '1' then - sdram_en <= '0'; - end if; - end if; - end if; - end process; - - sys_user_rom_addr <= mem_addr_r; - sys_user_rom_clk <= clk; - sys_user_rom_en <= urom_en; - - sdr_addr <= mem_addr_r(24 downto 2) & "0"; - - sdr_udata_in <= mem_dout_r & mem_dout_r; - sdr_be <= mem_we_r & mem_we_r; - - sdr_read <= '1'; - sdr_en <= sdram_en and not sdr_busy_q; - ------------------------------------------------------------------- -led_out: - process(rst, clk) - begin - if rst = '1' then - sys_led <= (others => '0'); - sys_error <= (others => '0'); - elsif rising_edge(clk) then - sys_led <= not mem_rdy & led_reg; - sys_error <= err_led_reg; - end if; - end process; - ------------------------------------------------------------------- -btn_ps2_register: - process(clk) - begin - if rising_edge(clk) then - btn_ps2_reg <= "000" & unsigned(sys_btn); - end if; - end process; - -proc_sd_counter: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - sd_counter <= (others => '0'); - elsif sdr_udata_vld_q = '1' then - sd_counter <= sd_counter + 1; - end if; - end if; - end process; - - mem_valid <= sdr_udata_vld_q or reg_data_vld or rom_data_vld or urom_data_vld or ram_data_vld; - mem_din <= sdr_udata_out_q(mem_din'left downto mem_din'right) when sdr_udata_vld_q = '1' else - reg_data when reg_data_vld = '1' else - rom_data when rom_data_vld = '1' else - sys_user_rom_din when urom_data_vld = '1' else - ram_data when ram_data_vld = '1'; - ------------------------------------------------------------------- -inst_rom: rom - PORT MAP - ( - clk => clk, - ce => rom_en, - addr => mem_addr_r, - dout => rom_data - ); - -inst_ram: ram - PORT MAP - ( - clk => clk, - ce => ram_en, - we => mem_we_r, - addr => mem_addr_r, - din => mem_dout_r, - dout => ram_data - ); - - -ram_read: - process(clk) - begin - if rising_edge(clk) then - ram_data_vld <= '0'; - if ram_en = '1' and mem_re_r = '1' then - ram_data_vld <= '1'; - end if; - end if; - end process; - -rom_read: - process(clk) - begin - if rising_edge(clk) then - rom_data_vld <= '0'; - if rom_en = '1' and mem_re_r = '1' then - rom_data_vld <= '1'; - end if; - end if; - end process; - -urom_read: - process(clk) - begin - if rising_edge(clk) then - urom_data_vld <= '0'; - if urom_en = '1' then - urom_data_vld <= '1'; - end if; - end if; - end process; - -registers_read: - process(clk) - begin - if rising_edge(clk) then - reg_data_vld <= '0'; - reg_re_uart_rx <= '0'; - if reg_en = '1' and mem_re_r = '1' then - reg_data_vld <= '1'; - reg_data <= (others => '0'); - case mem_addr_r(5 downto 2) is - - when "0000" => null; - - when "0001" => - reg_re_uart_rx <= mem_re_r; - reg_data(7 downto 0) <= unsigned(reg_uart_rx); - - when "0010" => - reg_data(7 downto 0) <= uart_status_port; - reg_data(15 downto 8) <= reg_uart_baud; - reg_data(23 downto 16) <= btn_ps2_reg; - reg_data(31 downto 24) <= cpu_lcd_in_reg; - - when "0100" => - reg_data <= cnt_usec; - - when "0101" => - reg_data <= cnt_sec; - - when others => null; - end case; - end if; - end if; - end process; - ------------------------------------------------------------------- -registers_write: - process(clk) - begin - if rising_edge(clk) then - cpu_lcd_we <= '0'; - reg_we_uart_tx <= '0'; - cnt_usec_we <= '0'; - cnt_sec_we <= '0'; - if rst = '1' then - led_reg <= (others => '0'); - err_led_reg <= (others => '0'); - cpu_lcd_out_reg <= (others => '0'); - reg_uart_baud <= to_unsigned(53, 8); - reg_uart_ctrl <= to_unsigned(0, 8); - elsif reg_en = '1' then - case mem_addr_r(5 downto 2) is - - when "0000" => - if mem_we_r(0) = '1' then - led_reg(7 downto 0) <= mem_dout_r(7 downto 0); - end if; - if mem_we_r(3) = '1' then - err_led_reg <= mem_dout_r(31 downto 30); - end if; - - when "0001" => - if mem_we_r(0) = '1' then - reg_we_uart_tx <= '1'; - reg_uart_tx <= mem_dout_r(7 downto 0); - end if; - - when "0010" => - if mem_we_r(0) = '1' then - reg_uart_ctrl <= mem_dout_r(7 downto 0); - end if; - if mem_we_r(1) = '1' then - reg_uart_baud <= mem_dout_r(15 downto 8); - end if; - if mem_we_r(3) = '1' then - cpu_lcd_we <= '1'; - cpu_lcd_out_reg <= mem_dout_r(31 downto 24); - end if; - - when "0100" => - if mem_we_r(3) = '1' then - cnt_usec_we <= '1'; - cnt_usec_preset <= mem_dout_r; - end if; - - when "0101" => - if mem_we_r(3) = '1' then - cnt_sec_we <= '1'; - cnt_sec_preset <= mem_dout_r; - end if; - - when others => null; - end case; + mem_area <= mem_dead; + if ADDR_O(31 downto 28) = X"0" then + mem_area <= mem_urom; + elsif ADDR_O(31 downto 28) = X"A" then + if ADDR_O(26) = '1' then + mem_area <= mem_flash; + elsif ADDR_O(17 downto 16) = "00" then + mem_area <= mem_gpio; + elsif ADDR_O(17 downto 16) = "01" then + mem_area <= mem_uart; + elsif ADDR_O(17 downto 16) = "10" then + mem_area <= mem_usb; end if; - end if; + elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then + mem_area <= mem_rom; + elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then + mem_area <= mem_ram; + elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then + mem_area <= mem_sdram; + end if; + end process; + +signal_mux: + process(mem_area, CYC_O) + begin + + CYC_O_urom <= '0'; + CYC_O_uart <= '0'; + CYC_O_gpio <= '0'; + CYC_O_flash <= '0'; + CYC_O_usb <= '0'; + CYC_O_rom <= '0'; + CYC_O_ram <= '0'; + CYC_O_sdram <= '0'; + + case mem_area is + + when mem_urom => + CYC_O_urom <= CYC_O; + + when mem_gpio => + CYC_O_gpio <= CYC_O; + + when mem_uart => + CYC_O_uart <= CYC_O; + + when mem_flash => + CYC_O_flash <= CYC_O; + + when mem_usb => + CYC_O_usb <= CYC_O; + + when mem_rom => + CYC_O_rom <= CYC_O; + + when mem_ram => + CYC_O_ram <= CYC_O; + + when mem_sdram => + CYC_O_sdram <= CYC_O; + + when others => null; + + end case; + + end process; + + sys_user_rom_addr <= ADDR_O; + sys_user_rom_clk <= clk; + sys_user_rom_en <= CYC_O_urom and STB_O; + DAT_I_urom <= sys_user_rom_din; + SRDY_I_urom <= CYC_O_urom; + +urom_ack_register: + process(clk) + begin + if rising_edge(clk) then + ACK_I_urom <= CYC_O_urom and STB_O; + end if; end process; ------------------------------------------------------------------ - mem_rdy <= not sdr_busy_q; + SRDY_I <= SRDY_I_flash or SRDY_I_usb or SRDY_I_sdram or SRDY_I_ram or SRDY_I_rom or SRDY_I_urom or SRDY_I_uart or SRDY_I_gpio; + ACK_I <= ACK_I_flash or ACK_I_usb or ACK_I_sdram or ACK_I_ram or ACK_I_rom or ACK_I_urom or ACK_I_uart or ACK_I_gpio; + DAT_I <= DAT_I_sdram when CYC_O_sdram = '1' else + DAT_I_ram when CYC_O_ram = '1' else + DAT_I_rom when CYC_O_rom = '1' else + DAT_I_urom when CYC_O_urom = '1' else + DAT_I_flash when CYC_O_flash = '1' else + DAT_I_usb when CYC_O_usb = '1' else + DAT_I_uart when CYC_O_uart = '1' else + DAT_I_gpio when CYC_O_gpio = '1' else X"DEADBEEF"; ------------------------------------------------------------------ inst_mips_top: mips_top PORT MAP ( - rst => rst, - clk => clk, - int => int, - mem_valid => mem_valid, - mem_rdy => mem_rdy, - mem_en => mem_en, - mem_re => mem_re, - mem_we => mem_we, - mem_din => mem_din, - mem_dout => mem_dout, - mem_addr => mem_addr + RST_I => rst, + CLK_I => clk, + ACK_I => ACK_I, + SRDY_I => SRDY_I, + MRDY_O => MRDY_O, + CYC_O => CYC_O, + STB_O => STB_O, + WE_O => WE_O, + SEL_O => SEL_O, + DAT_I => DAT_I, + DAT_O => DAT_O, + ADDR_O => ADDR_O, + INT => INT ); +inst_ram_wb : ram_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_ram, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I_ram, + SRDY_O => SRDY_I_ram, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I_ram + ); + +inst_rom_wb : rom_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_rom, + STB_I => STB_O, + ACK_O => ACK_I_rom, + MRDY_I => MRDY_O, + SRDY_O => SRDY_I_rom, + ADDR_I => ADDR_O, + DAT_O => DAT_I_rom + ); + + inst_lcd_port: lcd_port PORT MAP ( - rst => rst, clk => clk, - we => cpu_lcd_we, - din => cpu_lcd_out_reg, - dout => cpu_lcd_in_reg, + rst => rst, + we => '0', + din => X"00", + dout => open, lcd_d => sys_lcd_d, lcd_e => sys_lcd_e, lcd_rs => sys_lcd_rs, lcd_rw => sys_lcd_rw ); -inst_uart_tx: uart_tx - port map +inst_gpio_wb : gpio_wb + PORT MAP ( - data_in => std_logic_vector(reg_uart_tx), - write_buffer => reg_we_uart_tx, - reset_buffer => rst, - en_16_x_baud => en_16_x_baud, - serial_out => sys_tx, - buffer_full => tx_full, - buffer_half_full => tx_half_full, - clk => clk + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_gpio, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I_gpio, + SRDY_O => SRDY_I_gpio, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I_gpio, + + sys_gpo0 => gpo0, + sys_gpo1 => gpo1, + sys_gpi0 => gpi0, + sys_gpi1 => gpi1 ); - -inst_uart_rx: uart_rx - port map + + +inst_flash_port : async_port_wb + GENERIC MAP ( - serial_in => sys_rx, - data_out => reg_uart_rx, - read_buffer => reg_re_uart_rx, - reset_buffer => rst, - en_16_x_baud => en_16_x_baud, - buffer_data_present => rx_data_present, - buffer_full => rx_full, - buffer_half_full => rx_half_full, - clk => clk - ); - - uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; - -tick_usec_timer: - process(clk) - begin - if clk'event and clk='1' then - cnt_usec_en <= '0'; - if rst = '1' then - tick_usec <= 0; - cnt_usec_en <= '0'; - elsif tick_usec = tick_usec_t'high then - tick_usec <= 0; - cnt_usec_en <= '1'; - else - tick_usec <= tick_usec + 1; - end if; - end if; - end process; - -cnt_usec_timer: - process(clk) - begin - if clk'event and clk='1' then - cnt_sec_en <= '0'; - if rst = '1' then - cnt_usec <= (others => '0'); - cnt_sec_en <= '0'; - elsif cnt_usec_we = '1' then - cnt_usec <= cnt_usec_preset; - elsif cnt_usec_en = '1' then - if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then - cnt_usec <= (others => '0'); - cnt_sec_en <= '1'; - else - cnt_usec <= cnt_usec + 1; - end if; - end if; - end if; - end process; - -cnt_sec_timer: - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - cnt_sec <= (others => '0'); - elsif cnt_sec_we = '1' then - cnt_sec <= cnt_sec_preset; - elsif cnt_sec_en = '1' then - cnt_sec <= cnt_sec + 1; - end if; - end if; - end process; - -baud_timer: - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - baud_count <= (others => '0'); - elsif baud_count = reg_uart_baud then - baud_count <= (others => '0'); - en_16_x_baud <= '1'; - else - baud_count <= baud_count + 1; - en_16_x_baud <= '0'; - end if; - end if; - end process; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend - Generic map - ( - BL => BURST_LEN, - read_phaseshift => ddr_phaseshift, - f_sysclk => ddr_frequency_hz, - fifo_depth => 4 + addr_width => 25, + data_width => 32, + async_timespec => ts_flash ) - Port map + PORT MAP ( - - sys_rst_in => rst_in, - sys_clk_in => sys_clk_in, + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_flash, + STB_I => STB_O, + WE_I => WE_O, + ACK_O => ACK_I_flash, + SRDY_O => SRDY_I_flash, + MRDY_I => MRDY_O, + ADDR_I => flash_addr, + DAT_I => DAT_O, + DAT_O => DAT_I_flash, + async_a => sys_flash_a, + async_d => sys_flash_d, + async_cs => sys_flash_ce, + async_wr => sys_flash_wrn, + async_rd => sys_flash_rdn, + async_rst => sys_flash_rstn + ); - sys_rst_out => rst, - sys_clk_out => clk, - sys_clk_fb => sys_sdr_clk_fb, - - busy => sdr_busy_q, - en => sdr_en, - r_wn => mem_re_r, - be => sdr_be, - addr => sdr_addr, - din => sdr_udata_in, - dout => sdr_udata_out_q, - dout_re => sdr_read, - dout_vld => sdr_udata_vld_q, +inst_usb_port : async_port_wb + GENERIC MAP + ( + addr_width => 2, + data_width => 16, + async_timespec => ts_usb + ) + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_usb, + STB_I => STB_O, + WE_I => WE_O, + ACK_O => ACK_I_usb, + SRDY_O => SRDY_I_usb, + MRDY_I => MRDY_O, + ADDR_I => usb_addr, + DAT_I => DAT_O, + DAT_O => DAT_I_usb, + async_a => sys_usb_a, + async_d => sys_usb_d, + async_cs => sys_usb_csn, + async_wr => sys_usb_wrn, + async_rd => sys_usb_rdn, + async_rst => open + ); + +inst_uart_wb : uart_wb + PORT MAP + ( + CLK_I => clk, + RST_I => rst, + CYC_I => CYC_O_uart, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I_uart, + SRDY_O => SRDY_I_uart, + MRDY_I => MRDY_O, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I_uart, + INT_RX_O => int_uart_rx, + INT_TX_O => open, + ser_rx => sys_rx, + ser_tx => sys_tx + ); + + +inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb + GENERIC MAP + ( + BL => BURST_LEN, + f_sysclk => ddr_frequency_hz, + fifo_depth => 4 + ) + PORT MAP + ( + RST_I => rst, + CLK_I => clk, + CLK270_I => clk270, + CLK270VAR_I => clk270var, + CYC_I => CYC_O_sdram, + STB_I => STB_O, + SEL_I => SEL_O, + WE_I => WE_O, + ACK_O => ACK_I_sdram, + MRDY_I => MRDY_O, + SRDY_O => SRDY_I_sdram, + ADDR_I => ADDR_O, + DAT_I => DAT_O, + DAT_O => DAT_I_sdram, + -- SDRAM signals - sd_clk_p => sys_sdr_clk_p, - sd_clk_n => sys_sdr_clk_n, - sd_cke => sys_sdr_cke_q, - sd_cs_n => sys_sdr_cs_qn, - sd_cas_n => sys_sdr_cas_qn, - sd_ras_n => sys_sdr_ras_qn, - sd_we_n => sys_sdr_we_qn, - sd_addr => sys_sdr_a_q, - sd_ba => sys_sdr_ba_q, - sd_dm => sys_sdr_dm_q, - sd_dqs => sys_sdr_dqs_q, - sd_data => sys_sdr_data + sd_clk_p => sys_sdr_clk_p, + sd_clk_n => sys_sdr_clk_n, + sd_cke => sys_sdr_cke_q, + sd_cs_n => sys_sdr_cs_qn, + sd_cas_n => sys_sdr_cas_qn, + sd_ras_n => sys_sdr_ras_qn, + sd_we_n => sys_sdr_we_qn, + sd_addr => sys_sdr_a_q, + sd_ba => sys_sdr_ba_q, + sd_dm => sys_sdr_dm_q, + sd_dqs => sys_sdr_dqs_q, + sd_data => sys_sdr_data ); - STARTUP_VIRTEX4_inst : STARTUP_VIRTEX4 - port map ( - EOS => started_up, -- End of Startup 1-bit output - CLK => open, -- Clock input for start-up sequence - GSR => '0', -- Global Set/Reset input (GSR cannot be used for the port name) - GTS => '0', -- Global 3-state input (GTS cannot be used for the port name) - USRCCLKO => '0', -- USRCCLKO 1-bit input - USRCCLKTS => '0', -- USRCCLKTS 1-bit input - USRDONEO => '0', -- USRDONEO 1-bit input - USRDONETS => '0' -- USRDONETS 1-bit input +inst_clockgen : entity work.clockgen + GENERIC MAP + ( + sys1_phaseshift => 0, + frequency_hz => 100E6 + ) + PORT MAP + ( + -- Clocks and Reset + rst => rst_in, -- external async reset, low active + clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board + clk_fb_in => sys_sdr_clk_fb, -- feedback clock + sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° + sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° + sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0° + sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270° + locked_out => locked, -- DCM locked status + error_out => open ); ------------------------------------------------------------------ diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd index 0fa4602..092a632 100644 --- a/projects/mips_sys/src/tb_mips_sys.vhd +++ b/projects/mips_sys/src/tb_mips_sys.vhd @@ -74,7 +74,24 @@ ARCHITECTURE behavior OF tb_mips_sys IS signal sys_user_rom_en : std_logic; signal sys_user_rom_din : word_t; signal sys_user_rom_addr : word_t; + + signal sys_usb_d : unsigned(15 downto 0) := (others => '0'); + signal sys_usb_a : unsigned(1 downto 0); + signal sys_usb_csn : std_logic; + signal sys_usb_wrn : std_logic; + signal sys_usb_rdn : std_logic; + signal sys_usb_rstn : std_logic; + signal sys_usb_int : std_logic := '0'; + signal sys_flash_d : word_t; + signal sys_flash_a : unsigned(24 downto 0); + signal sys_flash_ce : std_logic; + signal sys_flash_wrn : std_logic; + signal sys_flash_rdn : std_logic; + signal sys_flash_rstn : std_logic; + signal sys_flash_byten : std_logic; + signal flash_reg : word_t; + type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t; signal urom_data : urom_data_t; @@ -120,6 +137,23 @@ uut: entity work.mips_sys sys_sdr_ba_q => sys_sdr_ba_q, sys_sdr_a_q => sys_sdr_a_q, sys_sdr_data => sys_sdr_data, + + sys_usb_d => sys_usb_d, + sys_usb_a => sys_usb_a, + sys_usb_csn => sys_usb_csn, + sys_usb_wrn => sys_usb_wrn, + sys_usb_rdn => sys_usb_rdn, + sys_usb_rstn => sys_usb_rstn, + sys_usb_int => sys_usb_int, + + sys_flash_d => sys_flash_d, + sys_flash_a => sys_flash_a, + sys_flash_ce => sys_flash_ce, + sys_flash_wrn => sys_flash_wrn, + sys_flash_rdn => sys_flash_rdn, + sys_flash_rstn => sys_flash_rstn, + sys_flash_byten => sys_flash_byten, + sys_error => sys_error ); @@ -160,6 +194,7 @@ uut: entity work.mips_sys sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps; refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false; + sys_usb_d <= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns; CLK_GEN: process begin wait for CLK_PERIOD/2; @@ -187,6 +222,21 @@ UROM_READ: process(sys_rst_n_in, sys_user_rom_clk) end if; end process; +FLASH_WRITE: process(sys_flash_ce, sys_flash_wrn, sys_flash_d) + begin + if rising_edge(sys_flash_wrn) and sys_flash_ce = '1' then + flash_reg <= sys_flash_d; + end if; + end process; + +FLASH_READ: process(sys_flash_ce, sys_flash_rdn, flash_reg) + begin + sys_flash_d <= (others => 'Z') after 10 ns; + if sys_flash_rdn = '0' and sys_flash_ce = '1' then + sys_flash_d <= flash_reg after 10 ns; + end if; + end process; + STIMULUS: process begin