Introduced J-Bus

git-svn-id: http://moon:8086/svn/vhdl/trunk@27 cc03376c-175c-47c8-b038-4cd826a8556b

projects/mips_sys/src/tb_mips_sys.vhd

@@ -74,7 +74,24 @@ ARCHITECTURE behavior OF tb_mips_sys IS
 	signal sys_user_rom_en		: std_logic;   
 	signal sys_user_rom_din		: word_t;  
 	signal sys_user_rom_addr	: word_t;   
+
+	signal sys_usb_d			: unsigned(15 downto 0) := (others => '0');
+	signal sys_usb_a			: unsigned(1 downto 0);
+	signal sys_usb_csn			: std_logic;
+	signal sys_usb_wrn			: std_logic;
+	signal sys_usb_rdn			: std_logic;
+	signal sys_usb_rstn			: std_logic;
+	signal sys_usb_int			: std_logic := '0';
 	
+	signal sys_flash_d			: word_t;
+	signal sys_flash_a			: unsigned(24 downto 0);
+	signal sys_flash_ce			: std_logic;
+	signal sys_flash_wrn		: std_logic;
+	signal sys_flash_rdn		: std_logic;
+	signal sys_flash_rstn		: std_logic;
+	signal sys_flash_byten		: std_logic;
+	signal flash_reg			: word_t;
+
 	type urom_data_t is array (natural range 0 to 2**(UROM_ADDR_WIDTH-2)-1) of word_t;
 	signal urom_data : urom_data_t;
 	
@@ -120,6 +137,23 @@ uut: entity work.mips_sys
 		sys_sdr_ba_q => sys_sdr_ba_q,
 		sys_sdr_a_q => sys_sdr_a_q,
 		sys_sdr_data => sys_sdr_data,
+
+		sys_usb_d		=> sys_usb_d,
+		sys_usb_a		=> sys_usb_a,
+		sys_usb_csn		=> sys_usb_csn,
+		sys_usb_wrn		=> sys_usb_wrn,
+		sys_usb_rdn		=> sys_usb_rdn,
+		sys_usb_rstn	=> sys_usb_rstn,
+		sys_usb_int		=> sys_usb_int,
+
+		sys_flash_d		=> sys_flash_d,
+		sys_flash_a		=> sys_flash_a,
+		sys_flash_ce	=> sys_flash_ce,
+		sys_flash_wrn	=> sys_flash_wrn,
+		sys_flash_rdn	=> sys_flash_rdn,
+		sys_flash_rstn	=> sys_flash_rstn,
+		sys_flash_byten	=> sys_flash_byten,
+
 		sys_error => sys_error
 	);
 
@@ -160,6 +194,7 @@ uut: entity work.mips_sys
 	sys_sdr_clk_fb   <= sys_sdr_clk_p after 2300 ps;
 	refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
 
+	sys_usb_d	<= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
 CLK_GEN: process
 	begin
 		wait for CLK_PERIOD/2;
@@ -187,6 +222,21 @@ UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
 		end if;	
 	end process;
 
+FLASH_WRITE: process(sys_flash_ce, sys_flash_wrn, sys_flash_d)
+	begin
+		if rising_edge(sys_flash_wrn) and sys_flash_ce = '1' then
+			flash_reg <= sys_flash_d;
+		end if;
+	end process;
+		
+FLASH_READ: process(sys_flash_ce, sys_flash_rdn, flash_reg)
+	begin
+		sys_flash_d <= (others => 'Z') after 10 ns;
+		if sys_flash_rdn = '0' and sys_flash_ce = '1' then
+			sys_flash_d <= flash_reg after 10 ns;
+		end if;
+	end process;
+
 STIMULUS: process
 
 	begin