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git-svn-id: http://moon:8086/svn/vhdl/trunk@27 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-07 17:26:27 +00:00
parent 3ecd76f185
commit dd38d30198
14 changed files with 4720 additions and 4523 deletions
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projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
+20 -14
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@@ -6,14 +6,16 @@ vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
@@ -23,17 +25,21 @@ vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\rom_wb.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_wb.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\gpio_wb.vhd"
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_frontend.vhd"
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"