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git-svn-id: http://moon:8086/svn/vhdl/trunk@27 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-07 17:26:27 +00:00
parent 3ecd76f185
commit dd38d30198
14 changed files with 4720 additions and 4523 deletions
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lib/CPUs/MIPS/src/core/icache.vhd
+42 -42
View File
@@ -14,20 +14,19 @@ ENTITY icache IS
);
Port
(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC;
ADDR_O : out word_t;
DAT_I : in word_t;
STB_O : out STD_LOGIC;
CYC_O : out STD_LOGIC;
en : in STD_LOGIC;
cpu_en : in STD_LOGIC;
cpu_addr : in word_t;
cpu_dout : out word_t;
cpu_busy : out STD_LOGIC;
mem_req : out STD_LOGIC;
mem_gnt : in STD_LOGIC;
mem_en : out STD_LOGIC;
mem_addr : out word_t;
mem_din : in word_t;
mem_valid : in STD_LOGIC;
mem_rdy : in STD_LOGIC
cpu_busy : out STD_LOGIC
);
END icache;
@@ -143,10 +142,10 @@ begin
cpu_index_reg:
process(clk)
process(CLK_I)
begin
if rising_edge(clk) then
if rst = '1' then
if rising_edge(CLK_I) then
if RST_I = '1' then
cache_index_reg <= (others => '0');
tag_index_reg <= (others => '0');
elsif cpu_reg_en = '1' then
@@ -163,8 +162,8 @@ inst_tag_ram : dpram_1w1r
data_width => tag_ram_data_width
)
PORT MAP (
clka => clk,
clkb => clk,
clka => CLK_I,
clkb => CLK_I,
en_a => '1',
en_b => tag_ram_re,
we_a => tag_ram_we,
@@ -180,8 +179,8 @@ inst_data_ram : dpram_1w1r
data_width => word_t'length
)
PORT MAP (
clka => clk,
clkb => clk,
clka => CLK_I,
clkb => CLK_I,
en_a => '1',
en_b => data_ram_re,
we_a => data_ram_we,
@@ -193,10 +192,10 @@ inst_data_ram : dpram_1w1r
cache_state_next:
process(clk)
process(CLK_I)
begin
if rising_edge(clk) then
if rst = '1' then
if rising_edge(CLK_I) then
if RST_I = '1' then
s <= init;
else
s <= sn;
@@ -213,13 +212,13 @@ cache_state_next:
tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
cache_entry_out <= to_icache_entry(tag_ram_data_rd);
data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg);
mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
data_ram_addr_wr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
data_ram_data_wr <= mem_din;
data_ram_we <= data_write and mem_valid;
data_ram_data_wr <= DAT_I;
data_ram_we <= data_write and ACK_I;
cache_state:
process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, mem_gnt, mem_rdy, en)
process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, en)
begin
cpu_reg_en <= '0';
cache_busy <= '1';
@@ -228,8 +227,8 @@ cache_state:
ram_index_count_rst <= '0';
mem_index_count_en <= '0';
mem_index_count_rst <= '0';
mem_req <= '0';
mem_en <= '0';
CYC_O <= '0';
STB_O <= '0';
data_ram_re <= '0';
tag_ram_re <= '0';
was_miss <= '0';
@@ -250,6 +249,7 @@ cache_state:
sn <= mem_request;
cpu_reg_en <= '0';
cache_busy <= '1';
CYC_O <= '1';
elsif cpu_en = '1' then
cpu_reg_en <= '1';
data_ram_re <= '1';
@@ -273,37 +273,37 @@ cache_state:
when mem_request =>
ram_index_count_rst <= '1';
mem_index_count_rst <= '1';
mem_req <= '1';
if mem_gnt = '1' then
CYC_O <= '1';
if SRDY_I = '1' then
sn <= mem_access;
end if;
when mem_access =>
data_write <= '1';
mem_req <= '1';
if mem_rdy = '1' then
CYC_O <= '1';
if SRDY_I = '1' then
mem_index_count_en <= '1';
mem_en <= '1';
STB_O <= '1';
if mem_index_count = 2**word_index_width-1 then
sn <= mem_data;
end if;
end if;
when mem_data =>
mem_req <= '1';
CYC_O <= '1';
data_write <= '1';
if ram_index_count = 2**word_index_width-1 then
if mem_valid = '1' then
if ACK_I = '1' then
sn <= upd_cache;
end if;
end if;
when upd_cache =>
mem_req <= '1';
CYC_O <= '1';
tag_ram_addr_wr <= cache_index_reg;
tag_ram_we <= '1';
cache_entry_in.valid <= '1';
sn <= rd_cache;
when rd_cache =>
-- mem_req <= '1';
-- CYC_O <= '1';
tag_ram_re <= '1';
data_ram_re <= '1';
was_miss <= '1';
@@ -314,9 +314,9 @@ cache_state:
end process;
cache_index_counter:
process(clk)
process(CLK_I)
begin
if rising_edge(clk) then
if rising_edge(CLK_I) then
if cache_index_count_en = '0' then
cache_index_count <= 2**cache_index_width-1;
elsif cache_index_count /= 0 then
@@ -326,12 +326,12 @@ cache_index_counter:
end process;
ram_index_counter:
process(clk)
process(CLK_I)
begin
if rising_edge(clk) then
if rising_edge(CLK_I) then
if ram_index_count_rst = '1' then
ram_index_count <= 0;
elsif data_write = '1' and mem_valid = '1' then
elsif data_write = '1' and ACK_I = '1' then
if ram_index_count /= 2**word_index_width-1 then
ram_index_count <= ram_index_count + 1;
end if;
@@ -340,9 +340,9 @@ ram_index_counter:
end process;
mem_index_counter:
process(clk)
process(CLK_I)
begin
if rising_edge(clk) then
if rising_edge(CLK_I) then
if mem_index_count_rst = '1' then
mem_index_count <= 0;
elsif mem_index_count_en = '1' then