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- Quick and dirty hack:

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avoid buscycle to finish even if data available,
  caused by latency of async-FIFO empty flag

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git-svn-id: http://moon:8086/svn/vhdl/trunk@996 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-04 17:58:37 +00:00
parent daeae0edba
commit dcea9c36b7
1 changed files with 60 additions and 9 deletions
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lib/JBUS/src/busmaster_async.vhd
+60 -9
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@@ -1,5 +1,5 @@
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.1 2013-07-21 09:21:30 jens Exp $ -- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013-08-04 17:58:37 jens Exp $
----------------------------------------------------------------------- -----------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
@@ -78,6 +78,10 @@ architecture Behavioral of busmaster_async is
signal jbus_cycle_busy : std_logic; signal jbus_cycle_busy : std_logic;
type jbus_state_t is (init, ready, start, wait_finish, finish1, finish2, finish3);
signal jbus_state : jbus_state_t;
signal jbus_state_next : jbus_state_t;
begin begin
cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full; cmd_en <= cmd_cycle_en and cmd_we and not cmd_fifo_full;
@@ -138,22 +142,69 @@ proc_bus_read_counter:
end if; end if;
end process; end process;
proc_cycle_busy: jbus_state_fsm_next:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
cycle_busy <= '0'; jbus_state <= init;
elsif cmd_cycle_en = '1' then else
if cmd_we = '1' then jbus_state <= jbus_state_next;
cycle_busy <= '1';
end if;
elsif read_cnt = 0 and cmd_fifo_empty = '1' then
cycle_busy <= '0';
end if; end if;
end if; end if;
end process; end process;
jbus_state_fsm:
process(jbus_state, cmd_we, cmd_fifo_empty, write_fifo_empty, read_cnt)
begin
cycle_busy <= '0';
jbus_state_next <= jbus_state;
case jbus_state is
when init =>
jbus_state_next <= ready;
when ready =>
if cmd_we = '1' or cmd_fifo_empty = '0' then
jbus_state_next <= start;
end if;
when start =>
cycle_busy <= '1';
if cmd_fifo_empty = '0' then
jbus_state_next <= wait_finish;
end if;
when wait_finish =>
cycle_busy <= '1';
if read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
jbus_state_next <= finish1;
end if;
-- Quick and dirty hack
-- avoid buscycle to finish even if data available,
-- caused by latency of async-FIFO empty flag
when finish1 =>
jbus_state_next <= finish2;
when finish2 =>
jbus_state_next <= finish3;
when finish3 =>
jbus_state_next <= ready;
if cmd_fifo_empty = '0' then
jbus_state_next <= wait_finish;
end if;
-- Quick and dirty hack
when others =>
jbus_state_next <= ready;
end case;
end process;
-- Bus READ FIFO -- Bus READ FIFO
inst_BM_READ_FIFO: entity work.fifo_async inst_BM_READ_FIFO: entity work.fifo_async
GENERIC MAP GENERIC MAP