From dcea9c36b79e914dd1dae7ca1ffb88e73494fd10 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sun, 4 Aug 2013 17:58:37 +0000
Subject: [PATCH] - Quick and dirty hack:   avoid buscycle to finish even if
 data available,   caused by latency of async-FIFO empty flag

Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@996 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/JBUS/src/busmaster_async.vhd | 69 +++++++++++++++++++++++++++-----
 1 file changed, 60 insertions(+), 9 deletions(-)

diff --git a/lib/JBUS/src/busmaster_async.vhd b/lib/JBUS/src/busmaster_async.vhd
index d3ffc5a..3c5a90b 100644
--- a/lib/JBUS/src/busmaster_async.vhd
+++ b/lib/JBUS/src/busmaster_async.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.1 2013-07-21 09:21:30 jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013-08-04 17:58:37 jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -78,6 +78,10 @@ architecture Behavioral of busmaster_async is
 
 	signal jbus_cycle_busy	: std_logic;
 
+	type jbus_state_t is (init, ready, start, wait_finish, finish1, finish2, finish3);
+	signal jbus_state		: jbus_state_t;
+	signal jbus_state_next	: jbus_state_t;
+	
 begin
 
 	cmd_en				<= cmd_cycle_en and cmd_we and not cmd_fifo_full;
@@ -138,22 +142,69 @@ proc_bus_read_counter:
 		end if;
 	end process;	
 
-proc_cycle_busy:
+jbus_state_fsm_next:
 	process(clk)
 	begin
 		if rising_edge(clk) then
 			if rst = '1' then
-				cycle_busy	 <= '0';
-			elsif cmd_cycle_en = '1' then
-				if cmd_we = '1' then
-					cycle_busy	 <= '1';
-				end if;
-			elsif read_cnt = 0 and cmd_fifo_empty = '1' then
-				cycle_busy	 <= '0';
+				jbus_state	 <= init;
+			else
+				jbus_state	 <= jbus_state_next;
 			end if;
 		end if;
 	end process;	
 
+jbus_state_fsm:
+	process(jbus_state, cmd_we, cmd_fifo_empty, write_fifo_empty, read_cnt)
+	begin
+
+		cycle_busy	 		<= '0';
+		jbus_state_next		<= jbus_state;
+		
+		case jbus_state is 
+		
+		when init =>
+			jbus_state_next		<= ready;
+		
+		when ready =>
+			if cmd_we = '1' or cmd_fifo_empty = '0' then
+				jbus_state_next		<= start;
+			end if;
+				
+		when start =>
+			cycle_busy	 <= '1';
+			if cmd_fifo_empty = '0' then
+				jbus_state_next		<= wait_finish;
+			end if;
+
+		when wait_finish =>
+			cycle_busy	 <= '1';
+			if read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
+				jbus_state_next		<= finish1;
+			end if;
+			
+		-- Quick and dirty hack
+		-- avoid buscycle to finish even if data available,
+		-- caused by latency of async-FIFO empty flag
+		when finish1 =>
+			jbus_state_next		<= finish2;
+		
+		when finish2 =>
+			jbus_state_next		<= finish3;
+
+		when finish3 =>
+			jbus_state_next		<= ready;
+			if cmd_fifo_empty = '0' then
+				jbus_state_next		<= wait_finish;
+			end if;
+		-- Quick and dirty hack
+
+		when others =>
+		jbus_state_next		<= ready;
+		
+		end case;
+	end process;	
+
 -- Bus READ FIFO
 inst_BM_READ_FIFO: entity work.fifo_async
 	GENERIC MAP