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git-svn-id: http://moon:8086/svn/vhdl/trunk@995 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-03 19:31:19 +00:00
parent 802ac54fdc
commit daeae0edba
1 changed files with 2 additions and 2 deletions
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lib/JBUS/src/busmaster_sync.vhd
+2 -2
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@@ -1,5 +1,5 @@
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.5 2013-07-21 09:21:17 jens Exp $ -- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013-08-03 19:31:19 jens Exp $
----------------------------------------------------------------------- -----------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
@@ -141,7 +141,7 @@ proc_cycle_busy:
if cmd_we = '1' then if cmd_we = '1' then
cycle_busy <= '1'; cycle_busy <= '1';
end if; end if;
elsif read_cnt = 0 and cmd_fifo_empty = '1' then elsif read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
cycle_busy <= '0'; cycle_busy <= '0';
end if; end if;
end if; end if;