diff --git a/lib/JBUS/src/busmaster_sync.vhd b/lib/JBUS/src/busmaster_sync.vhd
index 692f636..406e1d3 100644
--- a/lib/JBUS/src/busmaster_sync.vhd
+++ b/lib/JBUS/src/busmaster_sync.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.5 2013-07-21 09:21:17 jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013-08-03 19:31:19 jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -141,7 +141,7 @@ proc_cycle_busy:
 				if cmd_we = '1' then
 					cycle_busy	 <= '1';
 				end if;
-			elsif read_cnt = 0 and cmd_fifo_empty = '1' then
+			elsif read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
 				cycle_busy	 <= '0';
 			end if;
 		end if;