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- fixed write latency, which shall be zero

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1266 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2015-05-30 13:59:21 +00:00
parent 4016d60a4c
commit dabea0e2ab
3 changed files with 19 additions and 35 deletions
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lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32_de0nano.wdo
+2 -2
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@@ -187,7 +187,7 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_activate
add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_clr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {119326322 ps} 0}
WaveRestoreCursors {{Cursor 1} {197521836 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -201,4 +201,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {126 us}
WaveRestoreZoom {0 ps} {231 us}