From dabea0e2abdf36ff683bd7efac7a1031e6fa35fe Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 30 May 2015 13:59:21 +0000 Subject: [PATCH] - fixed write latency, which shall be zero git-svn-id: http://moon:8086/svn/vhdl/trunk@1266 cc03376c-175c-47c8-b038-4cd826a8556b --- .../sim/tb_ctrl_sdr_wb32_de0nano.wdo | 4 +-- .../ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd | 26 ++++--------------- .../ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd | 24 ++++++++--------- 3 files changed, 19 insertions(+), 35 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32_de0nano.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32_de0nano.wdo index 9987367..ea6622a 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32_de0nano.wdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_sdr_wb32_de0nano.wdo @@ -187,7 +187,7 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_activate add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_clr TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {119326322 ps} 0} +WaveRestoreCursors {{Cursor 1} {197521836 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -201,4 +201,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {0 ps} {126 us} +WaveRestoreZoom {0 ps} {231 us} diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd index 79a528b..05d2b41 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd @@ -75,10 +75,9 @@ architecture tech of sdram_phy is signal reset_counter : unsigned(7 downto 0) := (others => '1'); signal reset : STD_LOGIC := '1'; - signal we_cl_pipe : unsigned(TCAS-1 downto 0); - signal re_cl_pipe : unsigned(TCAS+2 downto 0); -- +2 = number of pipe registers used here + signal re_cl_pipe : unsigned(TCAS+1 downto 0); -- +2 = number of pipe registers used here - type u_tag_array_t is array (natural range 0 to TCAS+3) of user_tag_t; + type u_tag_array_t is array (natural range 0 to TCAS+2) of user_tag_t; signal u_tag_pipe : u_tag_array_t; attribute KEEP : string; @@ -92,10 +91,9 @@ begin rst0_out <= rst0; -- clk0_rd <= clk_fb; -- no feedback pin on DE0-Nano, use shifted clk1_0_out from clock gen - phy_out.wr_data_re <= we_cl_pipe(we_cl_pipe'left); phy_out.rd_data_we <= re_cl_pipe(re_cl_pipe'left); phy_out.tag_rd <= u_tag_pipe(u_tag_pipe'high); - phy_out.tag_wr <= u_tag_pipe(1); + phy_out.tag_wr <= u_tag_pipe(0); ------------------------------------------------------------------------------------------------------------------------------------------------ inst_sdram_clk : entity work.sdram_clk @@ -146,21 +144,6 @@ utag_pipe: end if; end process; -we_pipe: - process(clk0) - begin - if rising_edge(clk0) then - if rst0 = '1' then - we_cl_pipe <= (others => '0'); - else - for i in we_cl_pipe'length-1 downto 1 loop - we_cl_pipe(i) <= we_cl_pipe(i-1); - end loop; - we_cl_pipe(0) <= phy_ctrl.we; - end if; - end if; - end process; - re_pipe: process(clk0) begin @@ -211,7 +194,8 @@ part_clk <= clk0 after TPD_BOARD_SIM; part_ctrl_reg.addr <= (others=>'0'); part_ctrl_reg.cke <= '0'; else - part_ctrl_reg <= phy_ctrl.part; + part_ctrl_reg <= phy_ctrl.part; + phy_out.wr_data_re <= phy_ctrl.we; end if; end if; end process; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd index f9c9f57..bc63b46 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd @@ -343,7 +343,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -366,7 +366,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -389,7 +389,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -412,7 +412,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; end loop; @@ -439,7 +439,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -462,7 +462,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -485,7 +485,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -508,7 +508,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; end loop; @@ -754,7 +754,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -777,7 +777,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -800,7 +800,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; ------------------------------------------------------------ @@ -823,7 +823,7 @@ STIMULUS: process end loop; STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; + wait until rising_edge(CLK_O) and dout_cnt = 8; CYC_O <= '0'; end loop;