- Intital revision

git-svn-id: http://moon:8086/svn/vhdl/trunk@166 cc03376c-175c-47c8-b038-4cd826a8556b

lib/radio/decimator/CIC/src/cic_decim_pipe.vhd

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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_mix_cpx
+-- Module Name:   tb_mix_cpx.vhd
+-- Project Name:  mix_cpx
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+ENTITY cic_decim_pipe IS
+	Generic
+	(
+		nstages			: integer := 3;
+		max_ratio		: integer := 64;
+		max_diff_delay	: integer := 2;
+		max_width		: integer := 32;
+		max_width_frac	: integer := 20;
+		in_width		: integer := 32;
+		in_width_frac	: integer := 20;
+		out_width		: integer := 32;
+		out_width_frac	: integer := 20
+	);
+	Port
+	(
+		clk				: in std_logic;
+		rst				: in std_logic;
+		vld_in			: in std_logic;
+		ratio			: in natural range 1 to max_ratio;
+		diff_delay		: in natural range 1 to max_diff_delay;
+		shift_in		: in natural range 0 to max_width-1;
+		din				: in sfixed;
+		dout			: out sfixed;
+		vld_out 		: out std_logic
+	);
+END cic_decim_pipe;
+
+ARCHITECTURE behavior OF cic_decim_pipe IS 
+
+	COMPONENT cic_i_pipe
+	GENERIC
+	(
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk			: in std_logic;
+		rst			: in std_logic;
+		vld_in		: in std_logic;
+		din			: in sfixed;
+		dout		: out sfixed;
+		vld_out 	: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT cic_c_pipe
+	GENERIC
+	(
+		max_diff_delay	: integer;
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk			: in std_logic;
+		rst			: in std_logic;
+		vld_in		: in std_logic;
+		diff_delay	: in natural range 1 to max_diff_delay;
+		din			: in sfixed;
+		dout		: out sfixed;
+		vld_out 	: out std_logic
+	);
+	END COMPONENT;
+
+	subtype word_i_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+	type word_i_pipe_t is array (0 to nstages) of word_i_t;
+
+	signal word_i_pipe	: word_i_pipe_t;
+	signal vld_i_pipe	: unsigned (0 to nstages);
+	signal vld_i		: std_logic;
+	
+	subtype word_c_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+	type word_c_pipe_t is array (0 to nstages) of word_c_t;
+
+	signal word_c_pipe	: word_c_pipe_t;
+	signal vld_c_pipe	: unsigned (0 to nstages);
+	signal vld_c		: std_logic;
+
+	signal resample_cnt	: natural range 1 to max_ratio;
+	signal resample_vld	: std_logic;
+	
+BEGIN
+
+	word_i_pipe(0)	<= resize(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
+	vld_i_pipe(0)	<= vld_in;
+	vld_i			<= vld_i_pipe(nstages);
+	
+	gen_i_stages:
+	for i in 1 to nstages generate
+	begin
+		inst_cic_i_pipe: cic_i_pipe 
+		GENERIC MAP
+		(
+			max_width		=> max_width,
+			max_width_frac	=> max_width_frac,
+			in_width		=> max_width,
+			in_width_frac	=> max_width_frac,
+			out_width		=> max_width,
+			out_width_frac	=> max_width_frac
+		)
+		PORT MAP
+		(
+			clk				=> clk,
+			rst				=> rst,
+			vld_in			=> vld_i_pipe(i-1),
+			din				=> word_i_pipe(i-1),
+			dout			=> word_i_pipe(i),
+			vld_out			=> vld_i_pipe(i)
+		);
+	end generate;
+	
+	word_c_pipe(0)	<= word_i_pipe(nstages);
+	vld_c_pipe(0)	<= resample_vld;
+	vld_c			<= vld_c_pipe(nstages);
+
+	vld_out			<= vld_c;
+	
+	gen_c_stages:
+	for i in 1 to nstages generate
+	begin
+		inst_cic_c_pipe: cic_c_pipe 
+		GENERIC MAP
+		(
+			max_diff_delay	=> max_diff_delay,
+			max_width		=> max_width,
+			max_width_frac	=> max_width_frac,
+			in_width		=> max_width,
+			in_width_frac	=> max_width_frac,
+			out_width		=> max_width,
+			out_width_frac	=> max_width_frac
+		)
+		PORT MAP
+		(
+			clk				=> clk,
+			rst				=> rst,
+			vld_in			=> vld_c_pipe(i-1),
+			diff_delay		=> diff_delay,
+			din				=> word_c_pipe(i-1),
+			dout			=> word_c_pipe(i),
+			vld_out			=> vld_c_pipe(i)
+		);
+	end generate;
+	
+resampler_proc:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			resample_vld	<= '0';
+			if rst = '1' then
+				resample_cnt	<= 1;
+			elsif vld_i = '1' then
+				if resample_cnt = ratio then
+					resample_vld	<= '1';
+					resample_cnt	<= 1;
+				else
+					resample_cnt	<= resample_cnt + 1;
+				end if ;
+			end if;
+		end if;
+	end process;		
+
+dout_registers:
+	process(clk)
+	variable y : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	begin
+		if rising_edge(clk) then
+			y		:= resize(word_c_pipe(nstages) sra shift_in, y);
+			dout	<= y;
+		end if;
+	end process;		
+	
+END;