- Intital revision

git-svn-id: http://moon:8086/svn/vhdl/trunk@166 cc03376c-175c-47c8-b038-4cd826a8556b
2008-12-29 14:05:12 +00:00
parent f7e19d3d44
commit d9ba866ed0
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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+use work.cordic_pkg.all;
+
+	ENTITY syn_ddc IS
+	Generic 
+	(
+		nbits_in			: integer := 18;
+		nbits_in_frac		: integer := 16;
+		nbits_out			: integer := 18;
+		nbits_out_frac		: integer := 16;
+		lo_nbits_phase		: integer := 20;
+		lo_nbits_freq		: integer := 20;
+		cic_nstages			: integer := 3;
+		cic_max_ratio		: integer := 1024;
+		cic_max_diff_delay	: integer := 2;
+		cic_max_width		: integer := 48;
+		cic_max_width_frac	: integer := 16
+	);
+	PORT
+	(
+		rst					: in std_logic;
+		clk					: in std_logic;
+		lo_nco_rst			: in std_logic;
+		lo_nco_en			: in std_logic;
+		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
+		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
+		cic_ratio			: in natural range 1 to cic_max_ratio;
+		cic_diff_delay		: in natural range 1 to cic_max_diff_delay;
+		cic_shift_in		: in natural range 0 to cic_max_width-1;
+		din_i				: in  signed(nbits_in-1 downto 0);
+		din_q				: in  signed(nbits_in-1 downto 0);
+		dout_i				: out signed(nbits_out-1 downto 0);
+		dout_q				: out signed(nbits_out-1 downto 0);
+		din_vld				: in  std_logic;
+		dout_vld			: out std_logic
+	);
+	END syn_ddc;
+
+ARCHITECTURE behavior OF syn_ddc IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT ddc
+	GENERIC 
+	(
+		nbits_in			: integer;
+		nbits_in_frac		: integer;
+		nbits_out			: integer;
+		nbits_out_frac		: integer;
+		lo_nbits_phase		: integer;
+		lo_nbits_freq		: integer;
+		cic_nstages			: integer;
+		cic_max_ratio		: integer;
+		cic_max_diff_delay	: integer;
+		cic_max_width		: integer;
+		cic_max_width_frac	: integer
+	);
+	PORT
+	(
+		rst					: in std_logic;
+		clk					: in std_logic;
+		lo_nco_rst			: in std_logic;
+		lo_nco_en			: in std_logic;
+		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
+		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
+		cic_ratio			: in natural range 1 to cic_max_ratio;
+		cic_diff_delay		: in natural range 1 to cic_max_diff_delay;
+		cic_shift_in		: in natural range 0 to cic_max_width-1;
+		din_i				: in  sfixed;
+		din_q				: in  sfixed;
+		dout_i				: out sfixed;
+		dout_q				: out sfixed;
+		din_vld				: in  std_logic;
+		dout_vld			: out std_logic
+	);
+	END COMPONENT;
+
+	--Outputs
+	SIGNAL ddc_din_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL ddc_din_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL ddc_dout_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
+	SIGNAL ddc_dout_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	inst_ddc : ddc
+	GENERIC MAP 
+	(
+		nbits_in			=> nbits_in,
+		nbits_in_frac		=> nbits_in_frac,
+		nbits_out			=> nbits_out,
+		nbits_out_frac		=> nbits_out_frac,
+		lo_nbits_phase		=> lo_nbits_phase,
+		lo_nbits_freq		=> lo_nbits_freq,
+		cic_nstages			=> cic_nstages,
+		cic_max_ratio		=> cic_max_ratio,
+		cic_max_diff_delay	=> cic_max_diff_delay,
+		cic_max_width		=> cic_max_width,
+		cic_max_width_frac	=> cic_max_width_frac
+	)
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		lo_nco_rst			=> lo_nco_rst,
+		lo_nco_en			=> lo_nco_en,
+		lo_freq_in			=> lo_freq_in,
+		lo_phase_in			=> lo_phase_in,
+		cic_ratio			=> cic_ratio,
+		cic_diff_delay		=> cic_diff_delay,
+		cic_shift_in		=> cic_shift_in,
+		din_i				=> ddc_din_i,
+		din_q				=> ddc_din_q,
+		dout_i				=> ddc_dout_i,
+		dout_q				=> ddc_dout_q,
+		din_vld				=> din_vld,
+		dout_vld			=> dout_vld
+	);
+	
+	ddc_din_i	<= to_sfixed(din_i, ddc_din_i);
+	ddc_din_q	<= to_sfixed(din_q, ddc_din_q);
+	
+	dout_i	<= signed(ddc_dout_i);
+	dout_q	<= signed(ddc_dout_q);
+	
+END;