- Intital revision
git-svn-id: http://moon:8086/svn/vhdl/trunk@166 cc03376c-175c-47c8-b038-4cd826a8556b
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:42 13.05.2007
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-- Design Name: tb_nco
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-- Module Name: tb_nco.vhd
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-- Project Name: nco
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.fixed_pkg.all;
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use work.fixed_util_pkg.all;
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ENTITY ddc IS
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Generic
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(
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nbits_in : integer := 18;
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nbits_in_frac : integer := 16;
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nbits_out : integer := 18;
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nbits_out_frac : integer := 16;
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lo_nbits_phase : integer := 20;
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lo_nbits_freq : integer := 20;
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cic_nstages : integer := 3;
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cic_max_ratio : integer := 4096;
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cic_max_diff_delay : integer := 2;
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cic_max_width : integer := 32;
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cic_max_width_frac : integer := 20
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);
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PORT
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(
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rst : in std_logic;
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clk : in std_logic;
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lo_nco_rst : in std_logic;
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lo_nco_en : in std_logic;
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lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
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lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
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cic_ratio : in natural range 1 to cic_max_ratio;
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cic_diff_delay : in natural range 1 to cic_max_diff_delay;
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cic_shift_in : in natural range 0 to cic_max_width-1;
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din_i : in sfixed;
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din_q : in sfixed;
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dout_i : out sfixed;
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dout_q : out sfixed;
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din_vld : in std_logic;
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dout_vld : out std_logic
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);
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END ddc;
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ARCHITECTURE behavior OF ddc IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT mix
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GENERIC
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(
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nbits_din : integer;
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nbits_din_frac : integer;
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nbits_dout : integer;
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nbits_dout_frac : integer;
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nbits_phase : integer;
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nbits_freq : integer
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);
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PORT
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(
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rst : in std_logic;
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clk : in std_logic;
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nco_rst : in std_logic;
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nco_en : in std_logic;
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freq_in : in unsigned(nbits_freq-1 downto 0);
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phase_in : in unsigned(nbits_phase-1 downto 0);
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din_i : in sfixed;
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din_q : in sfixed;
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dout_i : out sfixed;
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dout_q : out sfixed;
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din_vld : in std_logic;
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dout_vld : out std_logic
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);
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END COMPONENT;
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COMPONENT cic_decim_pipe
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GENERIC
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(
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nstages : integer;
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max_ratio : integer;
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max_diff_delay : integer;
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max_width : integer;
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max_width_frac : integer;
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in_width : integer;
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in_width_frac : integer;
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out_width : integer;
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out_width_frac : integer
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);
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PORT
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(
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clk : in std_logic;
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rst : in std_logic;
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vld_in : in std_logic;
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ratio : in natural range 1 to max_ratio;
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diff_delay : in natural range 1 to max_diff_delay;
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shift_in : in natural range 0 to max_width-1;
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din : in sfixed;
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dout : out sfixed;
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vld_out : out std_logic
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);
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END COMPONENT;
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constant lo_nbits_in : integer := nbits_in;
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constant lo_nbits_in_frac : integer := nbits_in_frac;
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constant lo_nbits_out : integer := nbits_in;
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constant lo_nbits_out_frac : integer := nbits_in_frac;
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constant cic_nbits_in : integer := lo_nbits_out;
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constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
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constant cic_nbits_out : integer := nbits_out;
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constant cic_nbits_out_frac : integer := nbits_out_frac;
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SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
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SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
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SIGNAL mix_dout_vld : std_logic;
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SIGNAL dec_dout_i : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
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SIGNAL dec_dout_q : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
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SIGNAL dec_dout_vld_i : std_logic;
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SIGNAL dec_dout_vld_q : std_logic;
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BEGIN
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dout_vld <= dec_dout_vld_i and dec_dout_vld_q;
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dout_i <= dec_dout_i;
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dout_q <= dec_dout_q;
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-- Instantiate the Unit Under Test (UUT)
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inst_mixer: mix
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GENERIC MAP
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(
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nbits_din => lo_nbits_in,
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nbits_din_frac => lo_nbits_in_frac,
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nbits_dout => lo_nbits_out,
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nbits_dout_frac => lo_nbits_out_frac,
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nbits_phase => lo_nbits_phase,
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nbits_freq => lo_nbits_freq
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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nco_rst => lo_nco_rst,
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nco_en => lo_nco_en,
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freq_in => lo_freq_in,
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phase_in => lo_phase_in,
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din_i => din_i,
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din_q => din_q,
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dout_i => mix_dout_i,
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dout_q => mix_dout_q,
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din_vld => din_vld,
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dout_vld => mix_dout_vld
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);
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inst_cic_decim_pipe_I : cic_decim_pipe
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GENERIC MAP
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(
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nstages => cic_nstages,
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max_ratio => cic_max_ratio,
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max_diff_delay => cic_max_diff_delay,
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max_width => cic_max_width,
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max_width_frac => cic_max_width_frac,
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in_width => cic_nbits_in,
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in_width_frac => cic_nbits_in_frac,
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out_width => cic_nbits_out,
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out_width_frac => cic_nbits_out_frac
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)
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PORT MAP
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(
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clk => clk,
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rst => rst,
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vld_in => mix_dout_vld,
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ratio => cic_ratio,
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diff_delay => cic_diff_delay,
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shift_in => cic_shift_in,
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din => mix_dout_i,
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dout => dec_dout_i,
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vld_out => dec_dout_vld_i
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);
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inst_cic_decim_pipe_Q : cic_decim_pipe
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GENERIC MAP
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(
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nstages => cic_nstages,
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max_ratio => cic_max_ratio,
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max_diff_delay => cic_max_diff_delay,
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max_width => cic_max_width,
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max_width_frac => cic_max_width_frac,
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in_width => cic_nbits_in,
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in_width_frac => cic_nbits_in_frac,
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out_width => cic_nbits_out,
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out_width_frac => cic_nbits_out_frac
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)
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PORT MAP
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(
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clk => clk,
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rst => rst,
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vld_in => mix_dout_vld,
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ratio => cic_ratio,
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diff_delay => cic_diff_delay,
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shift_in => cic_shift_in,
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din => mix_dout_q,
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dout => dec_dout_q,
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vld_out => dec_dout_vld_q
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);
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END;
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