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- added CFIR

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git-svn-id: http://moon:8086/svn/vhdl/trunk@183 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-02 16:19:08 +00:00
parent 655cfb7f0d
commit d7ed0a9fb0
4 changed files with 216 additions and 29 deletions
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lib/radio/ddc/src/ddc.vhd
+172 -12
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@@ -22,6 +22,9 @@ use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.filter_pkg.all;
use work.fir_stage_pkg.all;
use work.fir_iterative_pkg.all;
ENTITY ddc IS
Generic
@@ -46,9 +49,12 @@ ENTITY ddc IS
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
din_i : in sfixed;
din_q : in sfixed;
din_vld : in std_logic;
-- dec_i : out sfixed;
-- dec_q : out sfixed;
-- dec_vld : out std_logic;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
);
END ddc;
@@ -105,15 +111,94 @@ ARCHITECTURE behavior OF ddc IS
);
END COMPONENT;
constant lo_nbits_in : integer := nbits_in;
constant lo_nbits_in_frac : integer := nbits_in_frac;
constant lo_nbits_out : integer := nbits_in;
constant lo_nbits_out_frac : integer := nbits_in_frac;
COMPONENT fir_iterative
GENERIC
(
ntaps : integer;
nbits_in : integer;
nbits_in_frac : integer;
nbits_stages : integer;
nbits_stages_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
fir_mode : fir_iterative_mode_t;
rounding : boolean;
saturating : boolean
);
PORT
(
srst : in std_logic;
clk : in std_logic;
h_din : in sfixed;
h_addr_out : out natural;
ready : out std_logic;
x_valid : in std_logic;
x_din : in sfixed;
y_dout_valid : out std_logic;
y_dout : out sfixed
);
END COMPONENT;
constant cic_nbits_in : integer := lo_nbits_out;
constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
constant cic_nbits_out : integer := nbits_out+1;
constant cic_nbits_out_frac : integer := nbits_out_frac+1;
constant lo_nbits_in : integer := nbits_in;
constant lo_nbits_in_frac : integer := nbits_in_frac;
constant lo_nbits_out : integer := nbits_in;
constant lo_nbits_out_frac : integer := nbits_in_frac;
constant cic_nbits_in : integer := lo_nbits_out;
constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
constant cic_nbits_out : integer := nbits_out+1;
constant cic_nbits_out_frac : integer := nbits_out_frac+1;
constant cfir_mode : fir_iterative_mode_t := symmetric;
constant cfir_ntaps : integer := 31;
constant cfir_nbits_in : integer := cic_nbits_out;
constant cfir_nbits_in_frac : integer := cic_nbits_out_frac;
constant cfir_nbits_out : integer := nbits_out;
constant cfir_nbits_out_frac : integer := nbits_out_frac;
constant cfir_nbits_stages : integer := cfir_nbits_in;
constant cfir_nbits_stages_frac : integer := cfir_nbits_in_frac;
SIGNAL cfir_h_din_i : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
SIGNAL cfir_h_din_q : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
SIGNAL cfir_h_addr_i : natural range 0 to ntaps_addr(cfir_ntaps, cfir_mode)-1;
SIGNAL cfir_h_addr_q : natural range 0 to ntaps_addr(cfir_ntaps, cfir_mode)-1;
SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL cfir_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL cfir_vld_i : std_logic;
SIGNAL cfir_vld_q : std_logic;
SIGNAL cfir_ready_i : std_logic;
SIGNAL cfir_ready_q : std_logic;
type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is
variable res : sfixed_array_t(0 to x'length-1, proto'range);
variable tt : sfixed(proto'range);
begin
for i in x'range loop
tt := to_sfixed(x(i), proto);
for j in proto'range loop
res(i,j) := tt(j);
end loop;
end loop;
return res;
end to_sfixed_array;
-------------------------------------------------------------------------------
-- sfixed <= sfixed_array(i)
function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is
variable dst : sfixed(src'range(2));
begin
for j in src'range(2) loop
dst(j) := src(index, j);
end loop;
return dst;
end to_sfixed;
constant cfir_coef : sfixed_array_t(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1, shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac))
:= to_sfixed_array(FilterCoef_Lowpass(cfir_ntaps, 0.1, 1.0)(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1), cfir_h_din_i);
SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
@@ -126,10 +211,15 @@ ARCHITECTURE behavior OF ddc IS
BEGIN
dout_vld <= dec_dout_vld_i and dec_dout_vld_q;
dout_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-- assert false report "cfir_h_addr_i'length = " & natural'image(cfir_h_addr_i'length) & "." severity note;
-- dec_vld <= dec_dout_vld_i and dec_dout_vld_q;
-- dec_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-- dec_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_vld <= cfir_vld_i and cfir_vld_q;
dout_i <= resize(cfir_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_q <= resize(cfir_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-- Instantiate the Unit Under Test (UUT)
inst_mixer: mix
GENERIC MAP
@@ -199,4 +289,74 @@ BEGIN
vld_out => dec_dout_vld_q
);
cfir_I: entity work.fir_iterative
GENERIC MAP
(
ntaps => cfir_ntaps,
nbits_in => cfir_nbits_in,
nbits_in_frac => cfir_nbits_in_frac,
nbits_out => cfir_nbits_out,
nbits_out_frac => cfir_nbits_out_frac,
nbits_stages => cfir_nbits_stages,
nbits_stages_frac => cfir_nbits_stages_frac,
fir_mode => cfir_mode,
rounding => false,
saturating => false
)
PORT MAP
(
srst => rst,
clk => clk,
h_din => cfir_h_din_i,
h_addr_out => cfir_h_addr_i,
ready => cfir_ready_i,
x_valid => dec_dout_vld_i,
x_din => dec_dout_i,
y_dout_valid => cfir_vld_i,
y_dout => cfir_dout_i
);
cfir_Q: entity work.fir_iterative
GENERIC MAP
(
ntaps => cfir_ntaps,
nbits_in => cfir_nbits_in,
nbits_in_frac => cfir_nbits_in_frac,
nbits_out => cfir_nbits_out,
nbits_out_frac => cfir_nbits_out_frac,
nbits_stages => cfir_nbits_stages,
nbits_stages_frac => cfir_nbits_stages_frac,
fir_mode => cfir_mode,
rounding => false,
saturating => false
)
PORT MAP
(
srst => rst,
clk => clk,
h_din => cfir_h_din_q,
h_addr_out => cfir_h_addr_q,
ready => cfir_ready_q,
x_valid => dec_dout_vld_q,
x_din => dec_dout_q,
y_dout_valid => cfir_vld_q,
y_dout => cfir_dout_q
);
cfir_coef_mem_i:
process(clk)
begin
if rising_edge(clk) then
cfir_h_din_i <= to_sfixed(cfir_coef, cfir_h_addr_i);
end if;
end process;
cfir_coef_mem_q:
process(clk)
begin
if rising_edge(clk) then
cfir_h_din_q <= to_sfixed(cfir_coef, cfir_h_addr_q);
end if;
end process;
END;