From d7ed0a9fb038c338515b5934a97e359af055ed6d Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 2 Jan 2009 16:19:08 +0000 Subject: [PATCH] - added CFIR git-svn-id: http://moon:8086/svn/vhdl/trunk@183 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/radio/ddc/sim/tb_ddc.fdo | 7 +- lib/radio/ddc/sim/tb_ddc.wdo | 19 ++-- lib/radio/ddc/src/ddc.vhd | 184 ++++++++++++++++++++++++++++++++--- lib/radio/ddc/src/tb_ddc.vhd | 35 +++++-- 4 files changed, 216 insertions(+), 29 deletions(-) diff --git a/lib/radio/ddc/sim/tb_ddc.fdo b/lib/radio/ddc/sim/tb_ddc.fdo index 1fdd382..c6f3d19 100644 --- a/lib/radio/ddc/sim/tb_ddc.fdo +++ b/lib/radio/ddc/sim/tb_ddc.fdo @@ -3,6 +3,11 @@ vmap ieee_proposed ../../../../Common/sim/ieee_proposed vlib work vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" vcom -explicit -93 "../../../misc/utils_pkg.vhd" +vcom -explicit -93 "../../../filter/src/filter_pkg.vhd" +vcom -explicit -93 "../../../filter/src/fir_stage_pkg.vhd" +vcom -explicit -93 "../../../filter/src/fir_iterative_pkg.vhd" +vcom -explicit -93 "../../../filter/src/fir_stage_sys.vhd" +vcom -explicit -93 "../../../filter/src/fir_iterative.vhd" vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd" @@ -21,4 +26,4 @@ do {tb_ddc.wdo} view wave view structure view signals -run 400us +run 200us diff --git a/lib/radio/ddc/sim/tb_ddc.wdo b/lib/radio/ddc/sim/tb_ddc.wdo index 78f1929..e515c3e 100644 --- a/lib/radio/ddc/sim/tb_ddc.wdo +++ b/lib/radio/ddc/sim/tb_ddc.wdo @@ -2,13 +2,10 @@ onerror {resume} quietly WaveActivateNextPane {} 0 add wave -noupdate -format Logic /tb_ddc/clk add wave -noupdate -format Logic /tb_ddc/rst -add wave -noupdate -format Literal /tb_ddc/ddc_shift_in add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst add wave -noupdate -format Logic /tb_ddc/ddc_nco_en add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in -add wave -noupdate -format Literal /tb_ddc/ddc_ratio -add wave -noupdate -format Literal /tb_ddc/ddc_diff_delay add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i @@ -43,13 +40,10 @@ add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_ou add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f add wave -noupdate -format Logic /tb_ddc/clk add wave -noupdate -format Logic /tb_ddc/rst -add wave -noupdate -format Literal /tb_ddc/ddc_shift_in add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst add wave -noupdate -format Logic /tb_ddc/ddc_nco_en add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in -add wave -noupdate -format Literal /tb_ddc/ddc_ratio -add wave -noupdate -format Literal /tb_ddc/ddc_diff_delay add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i @@ -82,6 +76,17 @@ add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_i_out_ add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_f add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f +add wave -noupdate -divider CFIR +add wave -noupdate -format Literal /tb_ddc/uut/cfir_dout_i +add wave -noupdate -format Literal /tb_ddc/uut/cfir_dout_q +add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_i +add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_q +add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_i +add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_q +add wave -noupdate -format Literal /tb_ddc/uut/dec_dout_i +add wave -noupdate -format Literal /tb_ddc/uut/dec_dout_q +add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i +add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {199990000 ps} 0} configure wave -namecolwidth 150 @@ -97,4 +102,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {366606200 ps} {822810200 ps} +WaveRestoreZoom {1566606200 ps} {2022810200 ps} diff --git a/lib/radio/ddc/src/ddc.vhd b/lib/radio/ddc/src/ddc.vhd index dde1e07..0427b41 100644 --- a/lib/radio/ddc/src/ddc.vhd +++ b/lib/radio/ddc/src/ddc.vhd @@ -22,6 +22,9 @@ use ieee_proposed.fixed_pkg.all; library work; use work.fixed_util_pkg.all; +use work.filter_pkg.all; +use work.fir_stage_pkg.all; +use work.fir_iterative_pkg.all; ENTITY ddc IS Generic @@ -46,9 +49,12 @@ ENTITY ddc IS lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); din_i : in sfixed; din_q : in sfixed; + din_vld : in std_logic; +-- dec_i : out sfixed; +-- dec_q : out sfixed; +-- dec_vld : out std_logic; dout_i : out sfixed; dout_q : out sfixed; - din_vld : in std_logic; dout_vld : out std_logic ); END ddc; @@ -105,15 +111,94 @@ ARCHITECTURE behavior OF ddc IS ); END COMPONENT; - constant lo_nbits_in : integer := nbits_in; - constant lo_nbits_in_frac : integer := nbits_in_frac; - constant lo_nbits_out : integer := nbits_in; - constant lo_nbits_out_frac : integer := nbits_in_frac; + COMPONENT fir_iterative + GENERIC + ( + ntaps : integer; + nbits_in : integer; + nbits_in_frac : integer; + nbits_stages : integer; + nbits_stages_frac : integer; + nbits_out : integer; + nbits_out_frac : integer; + fir_mode : fir_iterative_mode_t; + rounding : boolean; + saturating : boolean + ); + PORT + ( + srst : in std_logic; + clk : in std_logic; + h_din : in sfixed; + h_addr_out : out natural; + ready : out std_logic; + x_valid : in std_logic; + x_din : in sfixed; + y_dout_valid : out std_logic; + y_dout : out sfixed + ); + END COMPONENT; - constant cic_nbits_in : integer := lo_nbits_out; - constant cic_nbits_in_frac : integer := lo_nbits_out_frac; - constant cic_nbits_out : integer := nbits_out+1; - constant cic_nbits_out_frac : integer := nbits_out_frac+1; + constant lo_nbits_in : integer := nbits_in; + constant lo_nbits_in_frac : integer := nbits_in_frac; + constant lo_nbits_out : integer := nbits_in; + constant lo_nbits_out_frac : integer := nbits_in_frac; + + constant cic_nbits_in : integer := lo_nbits_out; + constant cic_nbits_in_frac : integer := lo_nbits_out_frac; + constant cic_nbits_out : integer := nbits_out+1; + constant cic_nbits_out_frac : integer := nbits_out_frac+1; + + constant cfir_mode : fir_iterative_mode_t := symmetric; + constant cfir_ntaps : integer := 31; + constant cfir_nbits_in : integer := cic_nbits_out; + constant cfir_nbits_in_frac : integer := cic_nbits_out_frac; + constant cfir_nbits_out : integer := nbits_out; + constant cfir_nbits_out_frac : integer := nbits_out_frac; + constant cfir_nbits_stages : integer := cfir_nbits_in; + constant cfir_nbits_stages_frac : integer := cfir_nbits_in_frac; + + SIGNAL cfir_h_din_i : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); + SIGNAL cfir_h_din_q : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); + SIGNAL cfir_h_addr_i : natural range 0 to ntaps_addr(cfir_ntaps, cfir_mode)-1; + SIGNAL cfir_h_addr_q : natural range 0 to ntaps_addr(cfir_ntaps, cfir_mode)-1; + SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); + SIGNAL cfir_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); + SIGNAL cfir_vld_i : std_logic; + SIGNAL cfir_vld_q : std_logic; + SIGNAL cfir_ready_i : std_logic; + SIGNAL cfir_ready_q : std_logic; + + type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; + function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is + variable res : sfixed_array_t(0 to x'length-1, proto'range); + variable tt : sfixed(proto'range); + begin + for i in x'range loop + tt := to_sfixed(x(i), proto); + for j in proto'range loop + res(i,j) := tt(j); + end loop; + end loop; + return res; + end to_sfixed_array; + + ------------------------------------------------------------------------------- + -- sfixed <= sfixed_array(i) + function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is + variable dst : sfixed(src'range(2)); + begin + for j in src'range(2) loop + dst(j) := src(index, j); + end loop; + + return dst; + + end to_sfixed; + + constant cfir_coef : sfixed_array_t(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1, shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)) + := to_sfixed_array(FilterCoef_Lowpass(cfir_ntaps, 0.1, 1.0)(0 to ntaps_addr(cfir_ntaps, cfir_mode)-1), cfir_h_din_i); + SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); @@ -126,10 +211,15 @@ ARCHITECTURE behavior OF ddc IS BEGIN - dout_vld <= dec_dout_vld_i and dec_dout_vld_q; - dout_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); - dout_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); +-- assert false report "cfir_h_addr_i'length = " & natural'image(cfir_h_addr_i'length) & "." severity note; +-- dec_vld <= dec_dout_vld_i and dec_dout_vld_q; +-- dec_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); +-- dec_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); + dout_vld <= cfir_vld_i and cfir_vld_q; + dout_i <= resize(cfir_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); + dout_q <= resize(cfir_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); + -- Instantiate the Unit Under Test (UUT) inst_mixer: mix GENERIC MAP @@ -199,4 +289,74 @@ BEGIN vld_out => dec_dout_vld_q ); + cfir_I: entity work.fir_iterative + GENERIC MAP + ( + ntaps => cfir_ntaps, + nbits_in => cfir_nbits_in, + nbits_in_frac => cfir_nbits_in_frac, + nbits_out => cfir_nbits_out, + nbits_out_frac => cfir_nbits_out_frac, + nbits_stages => cfir_nbits_stages, + nbits_stages_frac => cfir_nbits_stages_frac, + fir_mode => cfir_mode, + rounding => false, + saturating => false + ) + PORT MAP + ( + srst => rst, + clk => clk, + h_din => cfir_h_din_i, + h_addr_out => cfir_h_addr_i, + ready => cfir_ready_i, + x_valid => dec_dout_vld_i, + x_din => dec_dout_i, + y_dout_valid => cfir_vld_i, + y_dout => cfir_dout_i + ); + + cfir_Q: entity work.fir_iterative + GENERIC MAP + ( + ntaps => cfir_ntaps, + nbits_in => cfir_nbits_in, + nbits_in_frac => cfir_nbits_in_frac, + nbits_out => cfir_nbits_out, + nbits_out_frac => cfir_nbits_out_frac, + nbits_stages => cfir_nbits_stages, + nbits_stages_frac => cfir_nbits_stages_frac, + fir_mode => cfir_mode, + rounding => false, + saturating => false + ) + PORT MAP + ( + srst => rst, + clk => clk, + h_din => cfir_h_din_q, + h_addr_out => cfir_h_addr_q, + ready => cfir_ready_q, + x_valid => dec_dout_vld_q, + x_din => dec_dout_q, + y_dout_valid => cfir_vld_q, + y_dout => cfir_dout_q + ); + +cfir_coef_mem_i: + process(clk) + begin + if rising_edge(clk) then + cfir_h_din_i <= to_sfixed(cfir_coef, cfir_h_addr_i); + end if; + end process; + +cfir_coef_mem_q: + process(clk) + begin + if rising_edge(clk) then + cfir_h_din_q <= to_sfixed(cfir_coef, cfir_h_addr_q); + end if; + end process; + END; diff --git a/lib/radio/ddc/src/tb_ddc.vhd b/lib/radio/ddc/src/tb_ddc.vhd index aeccbaa..65fff47 100644 --- a/lib/radio/ddc/src/tb_ddc.vhd +++ b/lib/radio/ddc/src/tb_ddc.vhd @@ -69,9 +69,12 @@ ARCHITECTURE behavior OF tb_ddc IS lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); din_i : in sfixed; din_q : in sfixed; + din_vld : in std_logic; +-- dec_i : out sfixed; +-- dec_q : out sfixed; +-- dec_vld : out std_logic; dout_i : out sfixed; dout_q : out sfixed; - din_vld : in std_logic; dout_vld : out std_logic ); END COMPONENT; @@ -128,10 +131,15 @@ ARCHITECTURE behavior OF tb_ddc IS --Outputs SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); + SIGNAL ddc_din_vld : std_logic := '0'; + + SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); + SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); + SIGNAL ddc_dec_vld : std_logic; + SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); SIGNAL ddc_dout_vld : std_logic; - SIGNAL ddc_din_vld : std_logic := '0'; SIGNAL rfgen_nco_rst : std_logic := '0'; SIGNAL rfgen_nco_en : std_logic := '0'; @@ -191,9 +199,12 @@ BEGIN lo_phase_in => ddc_phase_in, din_i => ddc_din_i, din_q => ddc_din_q, + din_vld => ddc_din_vld, +-- dec_i => ddc_dec_i, +-- dec_q => ddc_dec_q, +-- dec_vld => ddc_dec_vld, dout_i => ddc_dout_i, dout_q => ddc_dout_q, - din_vld => ddc_din_vld, dout_vld => ddc_dout_vld ); @@ -343,10 +354,12 @@ BEGIN END PROCESS; tb_fo : PROCESS(clk) - file RESULT_Ii: text open write_mode is "i_in.txt"; - file RESULT_Qi: text open write_mode is "q_in.txt"; - file RESULT_Io: text open write_mode is "i_dec.txt"; - file RESULT_Qo: text open write_mode is "q_dec.txt"; + file RESULT_Ii: text open write_mode is "i_in.txt"; + file RESULT_Qi: text open write_mode is "q_in.txt"; + file RESULT_Ifir: text open write_mode is "i_fir.txt"; + file RESULT_Qfir: text open write_mode is "q_fir.txt"; + file RESULT_Idec: text open write_mode is "i_dec.txt"; + file RESULT_Qdec: text open write_mode is "q_dec.txt"; variable L: line; BEGIN @@ -356,8 +369,12 @@ BEGIN fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q))); end if; if ddc_dout_vld = '1' then - fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(ddc_dout_i))); - fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(ddc_dout_q))); + fprint(RESULT_Ifir, L,"%s\n", REAL'image(to_real(ddc_dout_i))); + fprint(RESULT_Qfir, L,"%s\n", REAL'image(to_real(ddc_dout_q))); + end if; + if ddc_dec_vld = '1' then + fprint(RESULT_Idec, L,"%s\n", REAL'image(to_real(ddc_dec_i))); + fprint(RESULT_Qdec, L,"%s\n", REAL'image(to_real(ddc_dec_q))); end if; end if;