Initial import
git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:16:14 10/02/05
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-- Design Name:
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-- Module Name: mix_cpx - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use work.fixed_pkg.all;
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use work.mix_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity mix_cpx is
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Generic
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(
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nbits_in : integer := 12;
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nbits_in_frac : integer := 12;
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nbits_out : integer := 12;
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nbits_out_frac : integer := 12;
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nbits_scale_z : integer := 0;
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has_in_reg : boolean := false;
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has_pipe_reg : boolean := false;
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has_out_reg : boolean := false;
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rounding : boolean := true;
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saturating : boolean := true
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);
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Port
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(
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srst : in std_logic;
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clk : in std_logic;
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in_valid : in std_logic;
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x_re_in : in sfixed;
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x_im_in : in sfixed;
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y_re_in : in sfixed;
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y_im_in : in sfixed;
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out_valid : out std_logic;
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z_re_out : out sfixed;
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z_im_out : out sfixed
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);
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end mix_cpx;
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architecture Behavioral of mix_cpx is
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constant nbits_prod : integer := nbits_out + nbits_scale_z;
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constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
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signal x_re, x_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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signal p_re_left, p_re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
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signal p_im_left, p_im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
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signal valid, p_valid : std_logic;
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------------------------------------------------------------
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begin
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------------------------------------------------------------
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proc_in_reg: process(srst, clk, in_valid, x_re_in, x_im_in, y_re_in, y_im_in)
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begin
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if has_in_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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x_re <= to_sfixed(0, x_re);
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x_im <= to_sfixed(0, x_im);
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y_re <= to_sfixed(0, y_re);
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y_im <= to_sfixed(0, y_im);
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valid <= '0';
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else
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valid <= in_valid;
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if in_valid = '1' then
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x_re <= x_re_in;
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x_im <= x_im_in;
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y_re <= y_re_in;
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y_im <= y_im_in;
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end if;
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end if;
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end if;
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else
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x_re <= x_re_in;
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x_im <= x_im_in;
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y_re <= y_re_in;
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y_im <= y_im_in;
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valid <= in_valid;
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end if;
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end process;
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------------------------------------------------------------
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proc_pipe_reg: process(srst, clk, valid, x_re, x_im, y_re, y_im)
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variable re_left, re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
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variable im_left, im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
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begin
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re_left := resize(x_re * y_re, re_left);
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re_right := resize(x_im * y_im, re_right);
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im_left := resize(x_re * y_im, im_left);
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im_right := resize(x_im * y_re, im_right);
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if has_pipe_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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p_re_left <= to_sfixed(0, p_re_left);
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p_re_right <= to_sfixed(0, p_re_right);
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p_im_left <= to_sfixed(0, p_im_left);
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p_im_right <= to_sfixed(0, p_im_right);
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p_valid <= '0';
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else
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p_re_left <= re_left;
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p_re_right <= re_right;
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p_im_left <= im_left;
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p_im_right <= im_right;
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p_valid <= valid;
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end if;
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end if;
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else
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p_re_left <= re_left;
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p_re_right <= re_right;
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p_im_left <= im_left;
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p_im_right <= im_right;
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p_valid <= valid;
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end if;
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end process;
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------------------------------------------------------------
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proc_out_reg: process(srst, clk, p_valid, p_re_left, p_re_right, p_im_left, p_im_right)
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variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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begin
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sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, rounding, saturating);
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sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, rounding, saturating);
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if has_out_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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z_re_out <= to_sfixed(0, re);
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z_im_out <= to_sfixed(0, im);
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out_valid <= '0';
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else
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z_re_out <= sum_re;
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z_im_out <= sum_im;
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out_valid <= p_valid;
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end if;
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end if;
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else
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z_re_out <= re;
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z_im_out <= im;
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out_valid <= p_valid;
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end if;
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end process;
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------------------------------------------------------------
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end Behavioral;
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@@ -0,0 +1,62 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use work.fixed_pkg.all;
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package mix_pkg is
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-------------------------------------------------------------
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-- Constructor helpers
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-- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
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function uproto (nbits : integer; nbits_frac : integer) return ufixed;
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-- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
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function sproto (nbits : integer; nbits_frac : integer) return sfixed;
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function to_unsigned (src : ufixed) return UNSIGNED;
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function to_signed (src : sfixed) return SIGNED;
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-------------------------------------------------------------------------------
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end; -- package mix_cpx_pkg;
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package body mix_pkg is
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-------------------------------------------------------------
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-- Constuctor helpers
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function uproto (nbits : integer; nbits_frac : integer) return ufixed is
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constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0');
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begin
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return result(nbits-nbits_frac-1 downto -nbits_frac);
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end uproto;
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-------------------------------------------------------------
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function sproto (nbits : integer; nbits_frac : integer) return sfixed is
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constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0');
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begin
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return result(nbits-nbits_frac downto -nbits_frac+1);
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end sproto;
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-------------------------------------------------------------
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function to_unsigned (src : ufixed) return UNSIGNED is
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subtype t is UNSIGNED(src'high - src'low downto 0);
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variable slv : t;
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begin
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slv := t(src);
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return UNSIGNED(to_X01(std_logic_vector(slv)));
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end function to_unsigned;
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-------------------------------------------------------------
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function to_signed (src : sfixed) return SIGNED is
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subtype t is SIGNED(src'high - src'low downto 0);
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variable slv : t;
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begin
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slv := t(src);
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return SIGNED(to_X01(std_logic_vector(slv)));
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end function to_signed;
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-------------------------------------------------------------------------------
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end; -- package mix_pkg;
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@@ -0,0 +1,155 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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||||
--
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||||
-- Create Date: 12:16:14 10/02/05
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-- Design Name:
|
||||
-- Module Name: mix_cpx - Behavioral
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-- Project Name:
|
||||
-- Target Device:
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||||
-- Tool versions:
|
||||
-- Description:
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||||
--
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||||
-- Dependencies:
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||||
--
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||||
-- Revision:
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||||
-- Revision 0.01 - File Created
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||||
-- Additional Comments:
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||||
--
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||||
--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use work.fixed_pkg.all;
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use work.mix_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity mix_real is
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Generic
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(
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nbits_in : integer := 12;
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nbits_in_frac : integer := 12;
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nbits_out : integer := 12;
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nbits_out_frac : integer := 12;
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nbits_scale_z : integer := 0;
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has_in_reg : boolean := false;
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has_pipe_reg : boolean := false;
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has_out_reg : boolean := false;
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rounding : boolean := true;
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saturating : boolean := true
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);
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Port
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(
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srst : in std_logic;
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clk : in std_logic;
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in_valid : in std_logic;
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x_re_din : in sfixed;
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y_re_din : in sfixed;
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y_im_din : in sfixed;
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out_valid : out std_logic;
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z_re_dout : out sfixed;
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z_im_dout : out sfixed
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);
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end mix_real;
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architecture Behavioral of mix_real is
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constant nbits_prod : integer := nbits_out + nbits_scale_z;
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constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
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signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
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signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
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signal valid, p_valid : std_logic;
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------------------------------------------------------------
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begin
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------------------------------------------------------------
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proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din)
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begin
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if has_in_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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x_re <= to_sfixed(0, x_re);
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y_re <= to_sfixed(0, y_re);
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y_im <= to_sfixed(0, y_im);
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valid <= '0';
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else
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valid <= in_valid;
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if in_valid = '1' then
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x_re <= x_re_din;
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y_re <= y_re_din;
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y_im <= y_im_din;
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end if;
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end if;
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end if;
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else
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x_re <= x_re_din;
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y_re <= y_re_din;
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y_im <= y_im_din;
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valid <= in_valid;
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end if;
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end process;
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------------------------------------------------------------
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proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im)
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variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
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variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
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begin
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re_left := resize(x_re * y_re, re_left);
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im_left := resize(x_re * y_im, im_left);
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if has_pipe_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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p_re_left <= to_sfixed(0, p_re_left);
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p_im_left <= to_sfixed(0, p_im_left);
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p_valid <= '0';
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else
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p_re_left <= re_left;
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p_im_left <= im_left;
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p_valid <= valid;
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end if;
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end if;
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else
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p_re_left <= re_left;
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p_im_left <= im_left;
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p_valid <= valid;
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end if;
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end process;
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------------------------------------------------------------
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proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left)
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variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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begin
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sum_re := resize(scalb(p_re_left, nbits_scale_z), re, rounding, saturating);
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||||
sum_im := resize(scalb(p_im_left, nbits_scale_z), im, rounding, saturating);
|
||||
if has_out_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
z_re_dout <= to_sfixed(0, re);
|
||||
z_im_dout <= to_sfixed(0, im);
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out_valid <= '0';
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||||
else
|
||||
z_re_dout <= sum_re;
|
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z_im_dout <= sum_im;
|
||||
out_valid <= p_valid;
|
||||
end if;
|
||||
end if;
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||||
else
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||||
z_re_dout <= re;
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z_im_dout <= im;
|
||||
out_valid <= p_valid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,208 @@
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||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
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use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
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use work.PCK_FIO.all;
|
||||
|
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ENTITY tb_mix_cpx IS
|
||||
Generic (
|
||||
nbits_in : integer := 24;
|
||||
nbits_in_frac : integer := 24;
|
||||
nbits_out : integer := 24;
|
||||
nbits_out_frac : integer := 24;
|
||||
nbits_scale_z : integer := 0;
|
||||
has_in_reg : boolean := true;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
END tb_mix_cpx;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mix_cpx IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT mix_cpx
|
||||
GENERIC
|
||||
(
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
nbits_scale_z : integer;
|
||||
has_in_reg : boolean;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
PORT
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
in_valid : in std_logic;
|
||||
x_re_in : in sfixed;
|
||||
x_im_in : in sfixed;
|
||||
y_re_in : in sfixed;
|
||||
y_im_in : in sfixed;
|
||||
out_valid : out std_logic;
|
||||
z_re_out : out sfixed;
|
||||
z_im_out : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL in_valid : std_logic := '0';
|
||||
SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
|
||||
--Outputs
|
||||
SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL out_valid : std_logic;
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
SIGNAL x_re : real := 0.0;
|
||||
SIGNAL x_im : real := 0.0;
|
||||
SIGNAL y_re : real := 0.0;
|
||||
SIGNAL y_im : real := 0.0;
|
||||
SIGNAL z_re : real := 0.0;
|
||||
SIGNAL z_im : real := 0.0;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: mix_cpx
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
nbits_scale_z => nbits_scale_z,
|
||||
has_in_reg => has_in_reg,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => srst,
|
||||
clk => clk,
|
||||
in_valid => in_valid,
|
||||
x_re_in => x_re_in,
|
||||
x_im_in => x_im_in,
|
||||
y_re_in => y_re_in,
|
||||
y_im_in => y_im_in,
|
||||
out_valid => out_valid,
|
||||
z_re_out => z_re_out,
|
||||
z_im_out => z_im_out
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.5, x_re_in);
|
||||
x_im_in <= to_sfixed(0.5, x_im_in);
|
||||
y_re_in <= to_sfixed(0.5, y_re_in);
|
||||
y_im_in <= to_sfixed(0.5, y_im_in);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 5*PERIOD;
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.125, x_re_in);
|
||||
x_im_in <= to_sfixed(0.25, x_im_in);
|
||||
y_re_in <= to_sfixed(0.25, y_re_in);
|
||||
y_im_in <= to_sfixed(0.125, y_im_in);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 5*PERIOD;
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.125, x_re_in);
|
||||
x_im_in <= to_sfixed(-0.25, x_im_in);
|
||||
y_re_in <= to_sfixed(0.25, y_re_in);
|
||||
y_im_in <= to_sfixed(0.125, y_im_in);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.125, x_re_in);
|
||||
x_im_in <= to_sfixed(-0.25, x_im_in);
|
||||
y_re_in <= to_sfixed(0.25, y_re_in);
|
||||
y_im_in <= to_sfixed(0.125, y_im_in);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.3, x_re_in);
|
||||
x_im_in <= to_sfixed(0.0, x_im_in);
|
||||
y_re_in <= to_sfixed(-0.5, y_re_in);
|
||||
y_im_in <= to_sfixed(0.5, y_im_in);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.0, x_re_in);
|
||||
x_im_in <= to_sfixed(-0.7071, x_im_in);
|
||||
y_re_in <= to_sfixed(0.0, y_re_in);
|
||||
y_im_in <= to_sfixed(-0.7071, y_im_in);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
x_re <= to_real(x_re_in);
|
||||
x_im <= to_real(x_im_in);
|
||||
y_re <= to_real(y_re_in);
|
||||
y_im <= to_real(y_im_in);
|
||||
z_re <= to_real(z_re_out);
|
||||
z_im <= to_real(z_im_out);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,197 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
use work.PCK_FIO.all;
|
||||
|
||||
ENTITY tb_mix_real IS
|
||||
Generic (
|
||||
nbits_in : integer := 24;
|
||||
nbits_in_frac : integer := 24;
|
||||
nbits_out : integer := 24;
|
||||
nbits_out_frac : integer := 24;
|
||||
nbits_scale_z : integer := 0;
|
||||
has_in_reg : boolean := true;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
END tb_mix_real;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mix_real IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT mix_real
|
||||
GENERIC
|
||||
(
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
nbits_scale_z : integer;
|
||||
has_in_reg : boolean;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
PORT
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
in_valid : in std_logic;
|
||||
x_re_din : in sfixed;
|
||||
y_re_din : in sfixed;
|
||||
y_im_din : in sfixed;
|
||||
out_valid : out std_logic;
|
||||
z_re_dout : out sfixed;
|
||||
z_im_dout : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL in_valid : std_logic := '0';
|
||||
SIGNAL x_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_im_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
|
||||
--Outputs
|
||||
SIGNAL z_re_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL z_im_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL out_valid : std_logic;
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
SIGNAL x_re : real := 0.0;
|
||||
SIGNAL y_re : real := 0.0;
|
||||
SIGNAL y_im : real := 0.0;
|
||||
SIGNAL z_re : real := 0.0;
|
||||
SIGNAL z_im : real := 0.0;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: mix_real
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
nbits_scale_z => nbits_scale_z,
|
||||
has_in_reg => has_in_reg,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => srst,
|
||||
clk => clk,
|
||||
in_valid => in_valid,
|
||||
x_re_din => x_re_din,
|
||||
y_re_din => y_re_din,
|
||||
y_im_din => y_im_din,
|
||||
out_valid => out_valid,
|
||||
z_re_dout => z_re_dout,
|
||||
z_im_dout => z_im_dout
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.5, x_re_din);
|
||||
y_re_din <= to_sfixed(0.5, y_re_din);
|
||||
y_im_din <= to_sfixed(0.5, y_im_din);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 5*PERIOD;
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.125, x_re_din);
|
||||
y_re_din <= to_sfixed(0.25, y_re_din);
|
||||
y_im_din <= to_sfixed(0.125, y_im_din);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 5*PERIOD;
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.125, x_re_din);
|
||||
y_re_din <= to_sfixed(0.25, y_re_din);
|
||||
y_im_din <= to_sfixed(0.125, y_im_din);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.125, x_re_din);
|
||||
y_re_din <= to_sfixed(0.25, y_re_din);
|
||||
y_im_din <= to_sfixed(0.125, y_im_din);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.3, x_re_din);
|
||||
y_re_din <= to_sfixed(-0.5, y_re_din);
|
||||
y_im_din <= to_sfixed(0.5, y_im_din);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.0, x_re_din);
|
||||
y_re_din <= to_sfixed(0.0, y_re_din);
|
||||
y_im_din <= to_sfixed(-0.7071, y_im_din);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
x_re <= to_real(x_re_din);
|
||||
y_re <= to_real(y_re_din);
|
||||
y_im <= to_real(y_im_din);
|
||||
z_re <= to_real(z_re_dout);
|
||||
z_im <= to_real(z_im_dout);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,158 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
use work.PCK_FIO.all;
|
||||
|
||||
ENTITY tb_undc_real IS
|
||||
Generic (
|
||||
nbits_data : integer := 24;
|
||||
nbits_data_frac : integer := 24;
|
||||
nbits_k : integer := 24;
|
||||
nbits_k_frac : integer := 24;
|
||||
has_in_reg : boolean := true;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
END tb_undc_real;
|
||||
|
||||
ARCHITECTURE behavior OF tb_undc_real IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT undc_real
|
||||
Generic
|
||||
(
|
||||
nbits_data : integer;
|
||||
nbits_data_frac : integer;
|
||||
nbits_k : integer;
|
||||
nbits_k_frac : integer;
|
||||
has_in_reg : boolean;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
din_valid : in std_logic;
|
||||
din : in sfixed;
|
||||
kin_valid : in std_logic;
|
||||
kin : in sfixed;
|
||||
dout_valid : out std_logic;
|
||||
dout : out sfixed;
|
||||
dc_out : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL din_valid : std_logic := '0';
|
||||
SIGNAL kin_valid : std_logic := '0';
|
||||
SIGNAL din : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
|
||||
SIGNAL kin : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
|
||||
|
||||
--Outputs
|
||||
SIGNAL dout : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
|
||||
SIGNAL dc_out : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
|
||||
SIGNAL dout_valid : std_logic;
|
||||
|
||||
SIGNAL k : real := 0.0;
|
||||
SIGNAL x : real := 0.0;
|
||||
SIGNAL y : real := 0.0;
|
||||
SIGNAL dc : real := 0.0;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: undc_real
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_data => nbits_data,
|
||||
nbits_data_frac => nbits_data_frac,
|
||||
nbits_k => nbits_k,
|
||||
nbits_k_frac => nbits_k_frac,
|
||||
has_in_reg => has_in_reg,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => srst,
|
||||
clk => clk,
|
||||
din_valid => din_valid,
|
||||
din => din,
|
||||
kin_valid => kin_valid,
|
||||
kin => kin,
|
||||
dout_valid => dout_valid,
|
||||
dout => dout,
|
||||
dc_out => dc_out
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
-- Load k
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
kin <= to_sfixed(0.0005, kin);
|
||||
kin_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
kin_valid <= '1';
|
||||
------------------------------------------
|
||||
-- Process
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
din <= to_sfixed(0.5, din);
|
||||
din_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
din_valid <= '1';
|
||||
wait for 5*PERIOD;
|
||||
|
||||
wait for 200*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
k <= to_real(kin);
|
||||
x <= to_real(din);
|
||||
y <= to_real(dout);
|
||||
dc <= to_real(dc_out);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,139 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: mix_cpx - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
entity undc_real is
|
||||
Generic
|
||||
(
|
||||
nbits_data : integer := 12;
|
||||
nbits_data_frac : integer := 12;
|
||||
nbits_k : integer := 12;
|
||||
nbits_k_frac : integer := 12;
|
||||
has_in_reg : boolean := false;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
din_valid : in std_logic;
|
||||
din : in sfixed;
|
||||
kin_valid : in std_logic;
|
||||
kin : in sfixed;
|
||||
dout_valid : out std_logic;
|
||||
dout : out sfixed;
|
||||
dc_out : out sfixed
|
||||
);
|
||||
end undc_real;
|
||||
|
||||
architecture Behavioral of undc_real is
|
||||
|
||||
constant nbits_internal : integer := nbits_data + nbits_data;
|
||||
constant nbits_internal_frac : integer := nbits_data_frac + nbits_data_frac;
|
||||
|
||||
signal x : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
|
||||
signal k : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
|
||||
signal dc : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
|
||||
signal y : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
|
||||
signal y1 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
|
||||
signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
|
||||
|
||||
begin
|
||||
|
||||
dout <= resize(y, sproto(nbits_data, nbits_data_frac), rounding, saturating);
|
||||
dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), false, false);
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_din_reg: process(clk, din_valid, din)
|
||||
begin
|
||||
if has_in_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
x <= to_sfixed(0, x);
|
||||
else
|
||||
if din_valid = '1' then
|
||||
x <= din;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
x <= din;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_valid_reg: process(clk, din_valid)
|
||||
begin
|
||||
if has_in_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
dout_valid <= '0';
|
||||
else
|
||||
dout_valid <= din_valid;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
dout_valid <= din_valid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_kin_reg: process(clk, kin_valid, kin)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
k <= to_sfixed(0, k);
|
||||
else
|
||||
if kin_valid = '1' then
|
||||
k <= kin;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_pipe_y: process(clk, x, dc)
|
||||
begin
|
||||
y <= resize(x - dc, y, false, false);
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
y1 <= to_sfixed(0, y1);
|
||||
y2 <= to_sfixed(0, y2);
|
||||
dc <= to_sfixed(0, dc);
|
||||
else
|
||||
y1 <= y;
|
||||
y2 <= resize(y1 * k, y2, false, false);
|
||||
dc <= resize(y2 + dc, dc, false, false);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
Reference in New Issue
Block a user