|}\\n"",\n" &
+ "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
+
+ "> );\n"
+ );
+
+fprint(RESULT, L,
+ "\n" &
+ "-- Results of the call with various format specifiers\n\n"
+ );
+
+
+fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+
+
+fprint(RESULT, L,
+ "\n----------------------\n" &
+ "-- Support for time --\n" &
+ "----------------------\n"
+ );
+
+fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
+ "-- into an integer value (of nanoseconds)\n"
+ );
+fprint (RESULT, L, "> wait for 648 ns\n");
+fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
+
+wait for 648 ns;
+
+fprint (RESULT, L, "The time is now %d ns\n", fo(now));
+
+
+fprint(RESULT, L,
+ "\n----------------------------------------\n" &
+ "-- Erroneous calls and error messages --\n" &
+ "----------------------------------------\n"
+ );
+
+fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
+ "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
+ );
+
+fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
+
+fprint(RESULT, L, "\n");
+
+fprint(RESULT, L, "-- Unsupported format specifier\n" &
+ "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
+ "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
+ );
+
+fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
+
+fprint(RESULT, L, "\n");
+
+fprint(RESULT, L,
+ "\n----------------------------------------\n" &
+ "-- Things you wouldn't expect to work --\n" &
+ "----------------------------------------\n"
+ );
+
+fprint(RESULT, L, "\n-- Nested iteration\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
+fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
+
+wait;
+
+end process USAGE;
+
+end TB;
diff --git a/lib/PCK_FIO-2002.7/CHANGES b/lib/PCK_FIO-2002.7/CHANGES
new file mode 100644
index 0000000..b755a56
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/CHANGES
@@ -0,0 +1,86 @@
+---- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----
+---- PCK_FIO: a VHDL package for C-style formatted file output
+---- Copyright (C) 1995, 2001 Easics NV
+----
+---- This library is free software; you can redistribute it and/or
+---- modify it under the terms of the GNU Lesser General Public
+---- License as published by the Free Software Foundation; either
+---- version 2.1 of the License, or (at your option) any later version.
+----
+---- This library is distributed in the hope that it will be useful,
+---- but WITHOUT ANY WARRANTY; without even the implied warranty of
+---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+---- Lesser General Public License for more details.
+----
+---- You should have received a copy of the GNU Lesser General Public
+---- License along with this library; if not, write to the Free Software
+---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----
+---- For suggestions, bug reports, enhancement requests, and info about
+---- our design services, you can contact us at the following address:
+---- http://www.easics.com
+---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
+---- tel.: +32 16 395 600 fax : +32 16 395 619
+---- e-mail: jand@easics.be (Jan Decaluwe)
+----
+
+
+Changes from version 1.16 to version 2002.07
+============================================
+
+PCK_FIO is now distributed under the GNU Lesser General Public Licencse
+instead of the ordinary GPL, to better reflect intended usage.
+
+Cosmetic changes in source code to correct some typos in the testbench output.
+A new testbench is also supplied.
+
+The package now uses IEEE.numeric_std as default.
+
+URL http://www.easics.com has been made part of address.
+
+Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993.
+Because of backwards-incompatibility, it has been necessary to supply
+different sets of files for 1987 and 1993.
+
+Split the packages into a separate file for the header and a
+separate file for the body (in compliance with Easics' guidelines).
+
+These changes resulted in the files:
+
+Files for VHDL-1993:
+--------------------
+ PCK_FIO_1993.vhd : the source code of the header file for the package
+ PCK_FIO_1993_BODY.vhd: the source code of the body of the package
+ TB_PCK_FIO_1993.vhd: the testbench for the package
+
+Files for VHDL-1987:
+--------------------
+ PCK_FIO_1987.vhd: the source code of the header file for the package
+ PCK_FIO_1987_BODY.vhd: the source code of the body of the package
+ TB_PCK_FIO_1987.vhd: the testbench for the package
+
+Updated README and PCK_FIO.html to support these changes.
+
+Adapted package files to support NUL termination of strings.
+fo(Arg: string) now prints the string until the first NUL.
+Several examples of its use are demonstrated in the supplied testbenches.
+
+Made cosmetic changes to code to improve readability.
+
+Acknowledgment
+--------------
+These changes have been implemented by Peter Geens.
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.html b/lib/PCK_FIO-2002.7/PCK_FIO.html
new file mode 100644
index 0000000..6b5fc72
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/PCK_FIO.html
@@ -0,0 +1,339 @@
+
+
+
+
+
+ VHDL package for formatted file output
+
+
+
+
+
+
+Name
+PCK_FIO - VHDL package for formatted file output
+
+
+
+Contents
+Usage
+
The file output function 'fo'
+
Format specifiers
+
Special characters
+
Things to watch out for
+
Methodology notes
+
Parametrization
+
Test bench
+
Known limitations and problems
+
Author
+
+
+
+Usage
+PCK_FIO is a VHDL package that defines fprint, a function
+for formatted file output.
+After installing the package you can call fprint as follows:
+
fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
+where F is the filehandle and L is the line variable.
+The argument Format is the format string, which consists of ``normal''
+substrings which are copied verbatim, and format specifiers, starting with
+'%'.
+A typical format string looks as follows:
+
"Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
+The remaining arguments are the expressions whose results you want to write
+to the file, embedded in fo function calls. There can be 0 to
+32 of such arguments. The expressions can be of any type for which an fo
+function exists. String expressions can also be called directly.
+
+
+
+The file output function 'fo'
+The fo (file output) functions do the trick. They
+return a tagged string representation that is meaningful to format specifiers.
+Here are some examples:
+ fo (signed'("1100")) returns "S:1100"
+ fo (unsigned'("1100")) returns "U:1100"
+ fo (TRUE) returns "L:T"
+ fo (127) returns "I:127"
+The internal behavior of fo is irrelevant to the typical user.
+
+The fo function is currently overloaded as follows:
+
+ function fo (Arg: unsigned) return string;
+ function fo (Arg: signed) return string;
+ function fo (Arg: std_logic_vector) return string;
+ function fo (Arg: std_ulogic_vector) return string;
+ function fo (Arg: bit_vector) return string;
+ function fo (Arg: integer) return string;
+ function fo (Arg: std_ulogic) return string;
+ function fo (Arg: bit) return string;
+ function fo (Arg: boolean) return string;
+ function fo (Arg: character) return string;
+ function fo (Arg: string) return string;
+ function fo (Arg: time) return string;
+
+
To support null-terminated strings, the function fo(Arg:
+string) processes Arg up to the first NUL character,
+if any. If you want the whole string to be outputted you can just enter
+the string as a direct argument in fprint. See also the
+examples in the testbench.
+
+
+
+
+Format specifiers
+The general format of a format specifier is:
+ %[-][n]c
+The optional - sign specifies left justified output; default is
+right justified.
+The optional number n specifies a field-width. If it is not specified,
+fprint
+does something reasonable.
+
c is the conversion specifier. Currently the following conversion
+specifiers are supported:
+
+-
+r
+
+-
+reasonable output format (inspired by Synopsys VSS)
+
+Prints the ``most reasonable'' representation e.g. hex for
+unsigned, signed and other bit-like vectors (not preferred for integers)
+
+-
+b
+
+-
+bit-oriented output
+
+-
+d
+
+-
+decimal output
+
+-
+s
+
+-
+string output (e.g. in combination with 'IMAGE for enum types)
+
+-
+q
+
+-
+``qualified'' string output (shows internal representation from fo)
+
+-
+{}
+
+-
+Iteration operator, used as follows:
+
+-
+%n{<format-string>}
+
+
In this case, n is the iteration count and is mandatory. Iteration
+can be nested.
+
+
+
+Special characters
+To print a double quote, use '""' in the format string (VHDL
+convention). To print the special characters, '\', and '%',
+escape them with '\'. To prevent '{' and '}'
+from being interpreted as opening and closing brackets in iteration strings,
+escape them with '\'.
+A newline is specified in the format string by '\n'.
+
+
+
+Things to notice
+The fprint function expands into VHDL write and writeline
+commands. As in plain VHDL, nothing will be written to the output file
+until a writeline is given. Therefore, don't forget to include
+'\n'
+commands in the format string, or it ``will not work''.
+The preferred format specifier for integers is, naturally, %d.
+This calls the VHDL write for integers. If you specify a field
+width that is too small, the field will automatically be expanded. If you
+use %r for integers, the field is not expanded automatically, which
+means that some digits are simply thrown away. This may sometimes be useful
+but it is also dangerous. Look at the test bench output for differences
+between %d and %r output.
+
When using the %d format specifier, the VHDL constraints for
+the allowed integer range apply.
+
In VHDL, signed/unsigned types have been standardized only relatively
+recently, in the package IEEE.numeric_std. The lack of a standard
+has caused (and is causing) portability issues. The most popular non-standard
+package that defines signed/unsigned is IEEE.std_logic_arith from
+Synopsys. PCK_FIO works with both packages, but refers to the standard
+package IEEE.numeric_std by default. To use IEEE.std_logic_arith
+instead, replace the reference to IEEE.numeric_std in the source
+code. This needs to be done consistently in a design database (e.g.
+in the PCK_FIO test bench as well).
+
+
+
+Methodology notes
+The obvious application for fprint is in test benches, to produce
+output files that trace the simulation behavior.
+Another interesting application for fprint is to produce info,
+warning and error messages in your models. As it can take arguments, fprint
+is much better suited for this task than VHDL's assert or report
+statements. Actually fprint produces its own (few) warning messages.
+
An advanced usage is the generation of test vectors in a specific format.
+Instead of using the fo functions, you can write your own set
+of functions that return the symbols of a specific test format in a way
+that is understandable to the fprint format specifiers. As an
+example, when a high output value should be represented using the symbol
+'H' it suffices to write a conversion function that returns "B:H" and call
+it in combination with the %b format specifier.
+
+
+
+Parametrization
+Prefix and postfix strings for bit-oriented and hex-oriented output are
+parameterizable in the packages to accommodate different output styles.
+The settings in the distribution are such that hex output is indicated
+by the prefix '0x', while bit output prefix and postfix are empty
+strings.
+You can adapt the output style by modifying the following constants
+in the package header:
+
-- prefix string for hex output
+
-- VHDL style: "X"""
+
-- Verilog style: "h'"
+
-- C style: "0x"
+
constant FIO_h_PRE: string := "0x";
+
-- postfix string for hex output
+
-- VHDL style: """"
+
constant FIO_h_POST: string := "";
+
-- prefix string for bit vector output
+
-- VHDL style: "B"""
+
-- Verilog style: "b'"
+
constant FIO_bv_PRE: string := "";
+
-- postfix string for bit vector output
+
-- VHDL style: """"
+
constant FIO_bv_POST: string := "";
+
-- prefix string for bit output
+
-- VHDL style: "'"
+
-- Verilog style: "b'"
+
constant FIO_b_PRE: string := "";
+
-- postfix string for bit output
+
-- VHDL style: "'"
+
constant FIO_b_POST: string := "";
+
+
+
+Test bench
+Included in the distribution are the files TB_PCK_FIO_1987.vhd and
+TB_PCK_FIO_1993 with a test bench,depending on the standard you're
+running, for the PCK_FIO package. The file PCK_FIO.out.gold contains
+the expected output. If you run the test bench it should produce the file
+PCK_FIO.out
+that should be identical to PCK_FIO.out.gold. The source files
+should be analyzed in a VHDL library EASICS_PACKAGES.
+A good way to understand fprint is to inspect the test bench
+and what it produces.
+
+
+
+Known limitations and problems
+This VHDL package is an implementation of a flexible concept. It is likely
+to be extended and modified in the future. Backward compatibility is not
+guaranteed. Therefore, it is not recommended to give this package the status
+of a company wide standard package (or even worse, a VHDL standard package).
+Rather, it should be linked with a particular project (and it can be regarded
+as a standard package within that project).
+PCK_FIO is available in either standard VHDL Std1076-1987 or standard
+VHDL Std1076-1993. Nevertheless, some simulators/versions have problems
+with the package. The following is an overview of currently known issues:
+
+
+PCK_FIO_1987 and various simulators/versions
+
+
+| Simulator |
+
+PCK_FIO_1987 |
+
+
+
+| Synopsys VSS 3.5 and earlier |
+
+Incorrect (all zero) output in compiled mode |
+
+
+
+| Synopsys VSS 97.01 |
+
+OK |
+
+
+
+| Synopsys VSS/Scirocco 2000.02 |
+
+Incorrect output in compiled mode, interpreted mode works |
+
+
+
+| Mentor quickhdl |
+
+OK |
+
+
+
+| Modeltech modelsim |
+
+OK |
+
+
+
+| Cadence Leapfrog |
+
+Should work with 4.4.1
+
Mysterious problems have been reported - please run the test bench
+and report problems |
+
+
+
+
+
+PCK_FIO_1993 and various simulators/versions
+
+
+| Simulator |
+
+PCK_FIO_1993 |
+
+
+
+| Synopsys VSS/Scirocco 2000.02 |
+
+Compile errors due to improper handling of files by Synopsys |
+
+
+
+| Synopsys VSS/Scirocco 2000.06 |
+
+works fine |
+
+
+
+| Modeltech modelsim 5.4c and higher |
+
+OK |
+
+
+
+Although the package name suggests file IO, it only does file output.
+
+
+
+Author
+Jan Decaluwe
+
+
+
+
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold b/lib/PCK_FIO-2002.7/PCK_FIO.out.gold
new file mode 100644
index 0000000..3fcfe4c
Binary files /dev/null and b/lib/PCK_FIO-2002.7/PCK_FIO.out.gold differ
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd
new file mode 100644
index 0000000..d4cf8e6
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd
@@ -0,0 +1,105 @@
+---- $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----
+---- PCK_FIO: a VHDL package for C-style formatted file output
+---- Copyright (C) 1995, 2001 Easics NV
+----
+---- This library is free software; you can redistribute it and/or
+---- modify it under the terms of the GNU Lesser General Public
+---- License as published by the Free Software Foundation; either
+---- version 2.1 of the License, or (at your option) any later version.
+----
+---- This library is distributed in the hope that it will be useful,
+---- but WITHOUT ANY WARRANTY; without even the implied warranty of
+---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+---- Lesser General Public License for more details.
+----
+---- You should have received a copy of the GNU Lesser General Public
+---- License along with this library; if not, write to the Free Software
+---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----
+---- For suggestions, bug reports, enhancement requests, and info about
+---- our design services, you can contact us at the following address:
+---- http://www.easics.com
+---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
+---- tel.: +32 16 395 600 fax : +32 16 395 619
+---- e-mail: jand@easics.be (Jan Decaluwe)
+----
+
+use STD.TEXTIO.all;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- signed/unsigned definition: use either std_logic_arith or numeric_std
+-- use IEEE.std_logic_arith.all; -- the Synopsys one
+use IEEE.numeric_std.all;
+
+package PCK_FIO is
+
+ -- prefix string for hex output
+ -- VHDL style: "X"""
+ -- Verilog style: "h'"
+ -- C style: "0x"
+ constant FIO_h_PRE: string := "0x";
+
+ -- postfix string for hex output
+ -- VHDL style: """"
+ constant FIO_h_POST: string := "";
+
+ -- prefix string for bit vector output
+ -- VHDL style: "B"""
+ -- Verilog style: "b'"
+ constant FIO_bv_PRE: string := "";
+
+ -- postfix string for bit vector output
+ -- VHDL style: """"
+ constant FIO_bv_POST: string := "";
+
+ -- prefix string for bit output
+ -- VHDL style: "'"
+ -- Verilog style: "b'"
+ constant FIO_b_PRE: string := "";
+
+ -- postfix string for bit output
+ -- VHDL style: "'"
+ constant FIO_b_POST: string := "";
+
+ -- digit width for the string representation of integers
+ constant FIO_d_WIDTH: integer := 10;
+
+ -- bit width for the string representation of integers
+ constant FIO_b_WIDTH: integer := 32;
+
+ -- definition of the NIL string (default value for fprint arguments)
+ -- fprint stops consuming arguments at the first NIL argument
+ constant FIO_NIL: string := "\";
+
+
+ procedure fprint
+ (F: out text;
+ L: inout line;
+ Format: in string;
+ A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
+ A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
+ A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
+ A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
+ );
+
+ function fo (Arg: unsigned) return string;
+ function fo (Arg: signed) return string;
+ function fo (Arg: std_logic_vector) return string;
+ function fo (Arg: std_ulogic_vector) return string;
+ function fo (Arg: bit_vector) return string;
+ function fo (Arg: integer) return string;
+ function fo (Arg: std_ulogic) return string;
+ function fo (Arg: bit) return string;
+ function fo (Arg: boolean) return string;
+ function fo (Arg: character) return string;
+ function fo (Arg: string) return string;
+ function fo (Arg: time) return string;
+
+ procedure FIO_FormatExpand (FMT: inout line;
+ Format: in string;
+ StartPointer: in positive);
+
+end PCK_FIO;
+
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd
new file mode 100644
index 0000000..44e42cf
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd
@@ -0,0 +1,821 @@
+---- $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----
+---- PCK_FIO: a VHDL package for C-style formatted file output
+---- Copyright (C) 1995, 2001 Easics NV
+----
+---- This library is free software; you can redistribute it and/or
+---- modify it under the terms of the GNU Lesser General Public
+---- License as published by the Free Software Foundation; either
+---- version 2.1 of the License, or (at your option) any later version.
+----
+---- This library is distributed in the hope that it will be useful,
+---- but WITHOUT ANY WARRANTY; without even the implied warranty of
+---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+---- Lesser General Public License for more details.
+----
+---- You should have received a copy of the GNU Lesser General Public
+---- License along with this library; if not, write to the Free Software
+---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----
+---- For suggestions, bug reports, enhancement requests, and info about
+---- our design services, you can contact us at the following address:
+---- http://www.easics.com
+---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
+---- tel.: +32 16 395 600 fax : +32 16 395 619
+---- e-mail: jand@easics.be (Jan Decaluwe)
+----
+
+
+package body PCK_FIO is
+
+ --------------------------
+ -- FIO Warnings support --
+ --------------------------
+
+ procedure FIO_Warning_Fsbla (F: out text;
+ L: inout line;
+ Format: in string;
+ Pointer: in positive) is
+ begin
+ fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
+ "Format specifier beyond last argument\n");
+ fprint (F, L, "** in format string: ""%s""\n", Format);
+ fprint (F, L, "** ");
+ for i in 1 to Pointer-1 loop
+ fprint (F, L, "-");
+ end loop;
+ fprint (F, L, "^\n");
+ end FIO_Warning_Fsbla;
+
+ procedure FIO_Warning_Ufs (F: out text;
+ L: inout line;
+ Format: in string;
+ Pointer: in positive;
+ Char: in character) is
+ begin
+ fprint (F, L, "\n** Warning: FIO_PrintArg: " &
+ "Unexpected format specifier '%r'\n",
+ fo(Char));
+ fprint (F, L, "** in format string: ""%s""\n", Format) ;
+ fprint (F, L, "** ");
+ for i in 1 to Pointer-1 loop
+ fprint (F, L, "-");
+ end loop;
+ fprint (F, L, "^\n** Assuming 'q' to proceed: ");
+ end FIO_Warning_Ufs;
+
+
+ ----------------------------------
+ -- bit conversion support --
+ ----------------------------------
+
+ type T_bit_map is array(bit) of character;
+
+ constant C_BIT_MAP: T_bit_map
+ := ('0', '1');
+
+ ----------------------------------
+ -- std_logic conversion support --
+ ----------------------------------
+
+ type T_std_logic_map is array(std_ulogic) of character;
+
+ constant C_STD_LOGIC_MAP: T_std_logic_map
+ := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+
+ ------------------------------
+ -- Digit conversion support --
+ ------------------------------
+
+ -- types & constants
+
+ subtype S_digit_chars is character range '0' to '9';
+ subtype S_digits is integer range 0 to 9 ;
+
+ type T_digit_chars_map is array(S_digit_chars) of S_digits;
+
+ constant C_DIGIT_CHARS_MAP: T_digit_chars_map
+ := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+
+ type T_digits_map is array(S_digits) of S_digit_chars;
+
+ constant C_DIGITS_MAP: T_digits_map
+ := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
+
+
+ --------------------------------
+ -- Decimal conversion support --
+ --------------------------------
+
+ -- unsigned to decimal
+
+ function U_To_d (Arg: string) return integer is
+ constant Argument: string(Arg'length downto 1) := Arg;
+ variable Result: integer := 0;
+ begin
+ for i in Argument'range loop
+ case Argument(i) is when '1' => Result := 2**(i-1) + Result;
+ when '0' => null;
+ when others => return(-1);
+ end case;
+ end loop;
+ return (Result);
+ end U_To_d;
+
+ -- signed to decimal
+
+ function S_To_d (Arg: string) return integer is
+ constant Argument: string(Arg'length downto 1) := Arg;
+ variable Result: integer := 0;
+ begin
+ case Argument(Argument'left) is
+ when '1' => Result := - 2**(Argument'left-1);
+ when '0' => Result := 0;
+ when others => return (integer'low);
+ end case;
+ for i in Argument'left-1 downto 1 loop
+ case Argument(i) is when '1' => Result := 2**(i-1) + Result;
+ when '0' => null;
+ when others => return(integer'low);
+ end case;
+ end loop;
+ return (Result);
+ end S_To_d;
+
+ -- string to decimal
+
+ function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
+ constant Sign: character := Arg(1);
+ constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
+ variable Char: character;
+ variable Result: integer := 0;
+ begin
+ Result := 0;
+ for i in Value'range loop
+ Result := Result * 10;
+ Char := Value(i);
+ if (Char /= ' ') then
+ Result := Result + C_DIGIT_CHARS_MAP(Char);
+ end if;
+ end loop;
+ case Sign is when '-' => return(-Result);
+ when others => return(Result);
+ end case;
+ end I_To_d;
+
+ -- boolean (0,1) to decimal
+
+ function B_To_d (Arg: string(1 to 1)) return integer is
+ begin
+ case Arg is when "1" => return(1);
+ when "0" => return(0);
+ when others => return(-1);
+ end case;
+ end B_To_d;
+
+ -- boolean (T,F) to decimal
+
+ function L_To_d (Arg: string(1 to 1)) return integer is
+ begin
+ case Arg is when "T" => return(1);
+ when others => return(0);
+ end case;
+ end L_To_d;
+
+
+
+ ----------------------------
+ -- Hex conversion support --
+ ----------------------------
+
+ -- Constants & types
+
+ constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
+
+ -- Function to return Hex index of a nibble
+
+ function U_To_h_Index(Arg: string(4 downto 1)) return integer is
+ variable Index: integer := 0;
+ begin
+ for i in Arg'range loop
+ case Arg(i) is when '1' => Index := 2**(i-1) + Index;
+ when '0' => null;
+ when others => return (17);
+ end case;
+ end loop;
+ return (Index+1);
+ end U_To_h_Index;
+
+ -- Hex conversion
+
+ function U_To_h (Arg: string) return string is
+ variable Result: string((Arg'length-1)/4 +1 downto 1);
+ variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
+ begin
+ ExtArg(Arg'length downto 1) := Arg;
+ for i in Result'range loop
+ Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
+ end loop;
+ return (FIO_h_PRE & Result & FIO_h_POST);
+ end U_To_h;
+
+
+
+ ----------------------------
+ -- Bit conversion support --
+ ----------------------------
+
+ function L_To_b (Arg: string(1 to 1)) return string is
+ variable Result: string(1 to 1);
+ begin
+ case Arg is when "T" => Result := "1";
+ when others => Result := "0";
+ end case;
+ return(FIO_b_PRE & Result & FIO_b_POST);
+ end L_To_b;
+
+
+ function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
+ Justified: side;
+ Width: integer) return string is
+
+ variable IntValue: integer := I_To_d(Arg);
+ variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
+ variable Sign: character := ' ';
+ constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
+ variable BitWidth: integer range 0 to FIO_b_WIDTH;
+ variable MsPos: integer range 1 to BitValue'length;
+ variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
+
+ begin
+
+ if (IntValue < 0) then
+ Sign := '-';
+ IntValue := -IntValue;
+ end if;
+
+ for i in BitValue'reverse_range loop
+ BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
+ IntValue := IntValue / 2;
+ exit when (IntValue = 0);
+ end loop;
+
+ BitValueExtended := BitValue & Blanks;
+
+ if (Width = 0) or (Width > FIO_b_WIDTH+1) then
+ BitWidth := FIO_b_WIDTH;
+ else
+ BitWidth := Width-1;
+ end if;
+
+ if (Justified = RIGHT) then
+ return (FIO_bv_PRE &
+ Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
+ FIO_bv_POST);
+ else
+ for i in BitValue'range loop
+ if BitValue(i) /= ' ' then
+ MSPos := i;
+ exit;
+ end if;
+ end loop;
+ return (FIO_bv_PRE &
+ Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
+ FIO_bv_POST);
+ end if;
+
+ end I_To_b;
+
+
+ -----------------------------------
+ -- Reasonable conversion support --
+ -----------------------------------
+
+ function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
+ Justified: side;
+ Width: integer) return string is
+ constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
+ constant Sign: character := Arg(1);
+ constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
+ variable IntWidth: integer range 0 to FIO_d_WIDTH;
+ variable MsPos: integer range 1 to Value'length;
+ variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
+ begin
+ if (Width = 0) or (Width > FIO_d_WIDTH+1) then
+ IntWidth := FIO_d_WIDTH;
+ else
+ IntWidth := Width-1;
+ end if;
+ if (Justified = RIGHT) then
+ return (Sign & Value(Value'length-IntWidth+1 to Value'length));
+ else
+ for i in Value'range loop
+ if Value(i) /= ' ' then
+ MSPos := i;
+ exit;
+ end if;
+ end loop;
+ return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
+ end if;
+ end I_To_r;
+
+
+ -------------------------------------------
+ -- Reasonable output conversion function --
+ -------------------------------------------
+
+ function ReasonableOutput (Arg: string;
+ Justified: side;
+ Width: integer) return string is
+ constant Argument: string(1 to Arg'length) := Arg;
+ constant TypeSpec: string (1 to 2) := Argument(1 to 2);
+ constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
+ begin
+ case TypeSpec is
+ when "U:" | "S:" | "V:" =>
+ return U_To_h(Value);
+ when "I:" =>
+ return I_To_r(Value, Justified, Width);
+ when "B:" | "L:" | "C:" =>
+ return Value;
+ when others =>
+ return Argument;
+ end case;
+
+ end ReasonableOutput;
+
+
+ ------------------------------------
+ -- Bit output conversion function --
+ ------------------------------------
+
+ function BitOutput (Arg: string;
+ Justified: side;
+ Width: integer) return string is
+ constant Argument: string(1 to Arg'length) := Arg;
+ constant TypeSpec: string (1 to 2) := Argument(1 to 2);
+ constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
+ begin
+ case TypeSpec is
+ when "U:" | "S:" | "V:" =>
+ return (FIO_bv_PRE & Value & FIO_bv_POST);
+ when "B:" =>
+ -- Value(1 to 1) instead of Value for LeapFrog
+ return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
+ when "I:" =>
+ return I_To_b(Value, Justified, Width);
+ when "L:" =>
+ -- Value(1 to 1) instead of Value for LeapFrog
+ return L_To_b(Value(1 to 1));
+ when others =>
+ return Argument;
+ end case;
+
+ end BitOutput;
+
+
+ -------------------------------------------
+ -- Decimal output conversion function --
+ -------------------------------------------
+
+ function DecimalOutput (Arg: string) return integer is
+ constant Argument: string(1 to Arg'length) := Arg;
+ constant TypeSpec: string (1 to 2) := Argument(1 to 2);
+ constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
+ begin
+ case TypeSpec is
+ when "U:"| "V:" =>
+ return U_To_d(Value);
+ when "S:" =>
+ return S_To_d(Value);
+ when "I:" =>
+ return I_To_d(Value);
+ when "B:" =>
+ return B_To_d(Value);
+ when "L:" =>
+ return L_To_d(Value);
+ when others =>
+ return integer'low;
+ end case;
+
+ end DecimalOutput;
+
+
+ ----------------------------
+ -- Atomic print functions --
+ ----------------------------
+
+ -- test for end of format string
+
+ function FIO_EOS (Format: in string;
+ Pointer: in integer)
+ return boolean is
+ begin
+ return (Pointer > Format'length);
+ end FIO_EOS;
+
+
+ -- Atomic value print function
+
+ procedure FIO_PrintValue (F: out text;
+ L: inout line;
+ Format: in string;
+ Pointer: inout integer;
+ Last: in boolean := FALSE) is
+ variable Char: character;
+ begin
+ while (not FIO_EOS(Format, Pointer)) loop
+ Char := Format(Pointer);
+ case Char is
+ when '\' =>
+ Pointer := Pointer + 1;
+ exit when (FIO_EOS(Format, Pointer));
+ Char := Format(Pointer);
+ case Char is when 'n' => writeline(F, L);
+ when others => write(L, Char);
+ end case;
+ when '%' =>
+ if Last then
+ FIO_Warning_Fsbla(F, L, Format, Pointer);
+ end if;
+ Pointer := Pointer + 1;
+ exit;
+ when others =>
+ write(L, char);
+ end case;
+ Pointer := Pointer + 1;
+ end loop;
+ end FIO_PrintValue;
+
+
+ ---- Atomic argument print function
+
+ procedure FIO_PrintArg (F: out text;
+ L: inout line;
+ Format: in string;
+ Pointer: inout integer;
+ Arg: in string) is
+ variable Char: character;
+ variable Justified: side;
+ variable Width: integer;
+ begin
+
+ FIO_PrintValue(F, L, Format, Pointer);
+
+ Justified := RIGHT;
+ Width := 0;
+ while (not FIO_EOS(Format, Pointer)) loop
+ Char := Format(Pointer);
+ case Char is
+ when '-' =>
+ Justified := LEFT;
+ Pointer := Pointer + 1;
+ when '0' to '9' =>
+ Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
+ Pointer := Pointer + 1;
+ when 'r' =>
+ write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ when 'b' =>
+ write(L, BitOutput(Arg, Justified, Width), Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ when 'd' =>
+ write(L, DecimalOutput(Arg), Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ when 'q' | 's' =>
+ write(L, Arg, Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ when others =>
+ FIO_Warning_Ufs(F, L, Format, Pointer, Char);
+ write(L, Arg, Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ end case;
+ end loop;
+ end FIO_PrintArg;
+
+
+ -----------------------------------------------------
+ -- The format string iteration expansion procedure --
+ -----------------------------------------------------
+
+ procedure FIO_FormatExpand (FMT: inout line;
+ Format: in string;
+ StartPointer: in positive) is
+
+ variable Pointer: positive := StartPointer;
+ variable TokenStart: positive;
+ variable IterStringStart: positive;
+ variable IterStringEnd: positive;
+ variable IterCount: natural;
+ variable OpenBrackets: natural;
+ variable L: line;
+
+ begin
+
+ FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
+
+ case Format(Pointer) is
+
+ -- look for format specifier
+ when '%' =>
+
+ -- initialize iteration token search
+ TokenStart := Pointer;
+ IterCount := 0;
+ Pointer := Pointer + 1;
+
+ -- start iteration token search
+ TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
+
+ case Format(Pointer) is
+
+ -- read iteration counter
+ when '0' to '9' =>
+ IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
+ Pointer := Pointer + 1;
+
+ -- expect open bracket
+ when '{' =>
+
+ -- initialize iteration string read
+ OpenBrackets := 1;
+ IterStringStart := Pointer + 1;
+ Pointer := Pointer + 1;
+ -- quit prematurely when iteration count is 0
+ next FORMAT_SEARCH when (IterCount = 0);
+
+ -- start iteration string read
+ ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
+
+ case Format(Pointer) is
+ -- keep track of open brackets
+ when '{' =>
+ OpenBrackets := OpenBrackets + 1;
+ Pointer := Pointer + 1;
+ -- when closing bracket is found, process iteration string
+ when '}' =>
+ OpenBrackets := OpenBrackets - 1;
+ if (OpenBrackets = 0) then
+ IterStringEnd := Pointer-1;
+ if (TokenStart /= 1) then
+ write(L, Format(1 to TokenStart-1));
+ end if;
+ for i in 1 to IterCount loop
+ write(L, Format(IterStringStart to IterStringEnd));
+ end loop;
+ if (IterStringEnd /= Format'length) then
+ write(L, Format(IterStringEnd+2 to Format'length));
+ end if;
+ -- call expansion procedure recursively on expanded format
+ FIO_FormatExpand(FMT, L.all, TokenStart);
+ deallocate(L);
+ return;
+ end if;
+ Pointer := Pointer + 1;
+ -- skip escaped characters
+ when '\' =>
+ Pointer := Pointer + 2;
+ -- read iteration string
+ when others =>
+ Pointer := Pointer + 1;
+
+ end case;
+
+ end loop ITER_STRING_READ;
+
+ -- stop iteration token search when no opening bracket found
+ when others =>
+ Pointer := Pointer + 1;
+ next FORMAT_SEARCH;
+
+ end case;
+
+ end loop TOKEN_READ;
+
+ -- skip escaped characters
+ when '\' =>
+ Pointer := Pointer + 2;
+
+ -- read other characters
+ when others =>
+ Pointer := Pointer + 1;
+
+ end case;
+
+ end loop FORMAT_SEARCH;
+
+ write(FMT, Format);
+ deallocate(L);
+
+ end FIO_FormatExpand;
+
+
+
+ --------------------------
+ -- The fprint procedure --
+ --------------------------
+
+ procedure fprint
+ (F: out text;
+ L: inout line;
+ Format: in string;
+ A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
+ A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
+ A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
+ A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
+ ) is
+
+ variable Pointer: integer;
+ variable FMT: line;
+
+ begin
+
+ Pointer := 1;
+
+ FIO_FormatExpand (FMT, Format, Format'low);
+
+ if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
+ if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
+ if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
+ if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
+ if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
+ if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
+ if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
+ if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
+ if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
+ if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
+ if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
+ if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
+ if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
+ if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
+ if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
+ if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
+ if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
+ if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
+ if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
+ if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
+ if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
+ if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
+ if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
+ if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
+ if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
+ if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
+ if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
+ if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
+ if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
+ if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
+ if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
+ if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
+ end if; end if; end if; end if; end if; end if; end if; end if;
+ end if; end if; end if; end if; end if; end if; end if; end if;
+ end if; end if; end if; end if; end if; end if; end if; end if;
+ end if; end if; end if; end if; end if; end if; end if; end if;
+
+ FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
+
+ deallocate(FMT);
+
+ end fprint;
+
+
+ -------------------------------------------
+ -- Formatted output conversion functions --
+ -------------------------------------------
+
+ function fo (Arg: unsigned) return string is
+ constant Argument: unsigned(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_STD_LOGIC_MAP(Argument(i));
+ end loop;
+ return ("U:" & Result);
+ end fo;
+
+ function fo (Arg: signed) return string is
+ constant Argument: signed(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_STD_LOGIC_MAP(Argument(i));
+ end loop;
+ return ("S:" & Result);
+ end fo;
+
+ function fo (Arg: std_logic_vector) return string is
+ constant Argument: std_logic_vector(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_STD_LOGIC_MAP(Argument(i));
+ end loop;
+ return ("V:" & Result);
+ end fo;
+
+ function fo (Arg: std_ulogic_vector) return string is
+ constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_STD_LOGIC_MAP(Argument(i));
+ end loop;
+ return ("V:" & Result);
+ end fo;
+
+ function fo (Arg: bit_vector) return string is
+ constant Argument: bit_vector(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_BIT_MAP(Argument(i));
+ end loop;
+ return ("V:" & Result);
+ end fo;
+
+ function fo (Arg: integer) return string is
+ variable Argument: integer := Arg;
+ variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
+ variable Sign: character := ' ';
+ begin
+ if (Argument < 0) and (Argument /= integer'low) then
+ Sign := '-';
+ Argument := -Argument;
+ end if;
+ for i in Result'reverse_range loop
+ Result(i) := C_DIGITS_MAP(Argument mod 10);
+ Argument := Argument / 10;
+ exit when (Argument = 0);
+ end loop;
+ return ("I:" & Sign & Result);
+ end fo;
+
+ function fo (Arg: std_ulogic) return string is
+ begin
+ return ("B:" & C_STD_LOGIC_MAP(Arg));
+ end fo;
+
+ function fo (Arg: bit) return string is
+ begin
+ return ("B:" & C_BIT_MAP(Arg));
+ end fo;
+
+ function fo (Arg: boolean) return string is
+ begin
+ if (ARG = TRUE) then
+ return ("L:T");
+ else
+ return ("L:F");
+ end if;
+ end fo;
+
+ function fo (Arg: character) return string is
+ begin
+ return ("C:" & Arg);
+ end fo;
+
+ -- auxilary function fgets(Arg: string)
+ -- gives index until first NUL
+ -- reads string from 1 to Arg'length
+ function fgets (Arg: string) return integer is
+ variable index: integer := Arg'length;
+ begin
+ for i in 1 to Arg'length loop
+ if Arg(i) = NUL then
+ index := i - 1;
+ exit;
+ else
+ null;
+ end if;
+ end loop;
+ return index;
+ end fgets;
+
+ function fo (Arg: string) return string is
+ begin
+ return Arg(1 to fgets(Arg));
+ end fo;
+
+ function fo (Arg: time) return string is
+ begin
+ return fo (integer (Arg / 1 ns));
+ end fo;
+
+end PCK_FIO;
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd
new file mode 100644
index 0000000..9df893e
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd
@@ -0,0 +1,108 @@
+---- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----
+---- PCK_FIO: a VHDL package for C-style formatted file output
+---- Copyright (C) 1995, 2001 Easics NV
+----
+---- This library is free software; you can redistribute it and/or
+---- modify it under the terms of the GNU Lesser General Public
+---- License as published by the Free Software Foundation; either
+---- version 2.1 of the License, or (at your option) any later version.
+----
+---- This library is distributed in the hope that it will be useful,
+---- but WITHOUT ANY WARRANTY; without even the implied warranty of
+---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+---- Lesser General Public License for more details.
+----
+---- You should have received a copy of the GNU Lesser General Public
+---- License along with this library; if not, write to the Free Software
+---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----
+---- For suggestions, bug reports, enhancement requests, and info about
+---- our design services, you can contact us at the following address:
+---- http://www.easics.com
+---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
+---- tel.: +32 16 395 600 fax : +32 16 395 619
+---- e-mail: jand@easics.be (Jan Decaluwe)
+----
+
+
+use STD.TEXTIO.all;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- signed/unsigned definition: use either std_logic_arith or numeric_std
+-- use IEEE.std_logic_arith.all; -- the Synopsys one
+use IEEE.numeric_std.all;
+
+package PCK_FIO is
+
+
+ -- prefix string for hex output
+ -- VHDL style: "X"""
+ -- Verilog style: "h'"
+ -- C style: "0x"
+ constant FIO_h_PRE: string := "0x";
+
+ -- postfix string for hex output
+ -- VHDL style: """"
+ constant FIO_h_POST: string := "";
+
+ -- prefix string for bit vector output
+ -- VHDL style: "B"""
+ -- Verilog style: "b'"
+ constant FIO_bv_PRE: string := "";
+
+ -- postfix string for bit vector output
+ -- VHDL style: """"
+ constant FIO_bv_POST: string := "";
+
+ -- prefix string for bit output
+ -- VHDL style: "'"
+ -- Verilog style: "b'"
+ constant FIO_b_PRE: string := "";
+
+ -- postfix string for bit output
+ -- VHDL style: "'"
+ constant FIO_b_POST: string := "";
+
+ -- digit width for the string representation of integers
+ constant FIO_d_WIDTH: integer := 10;
+
+ -- bit width for the string representation of integers
+ constant FIO_b_WIDTH: integer := 32;
+
+ -- definition of the NIL string (default value for fprint arguments)
+ -- fprint stops consuming arguments at the first NIL argument
+ constant FIO_NIL: string := "\";
+
+ procedure fprint
+ (file F: text;
+ L: inout line;
+ Format: in string;
+ A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
+ A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
+ A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
+ A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
+ );
+
+ function fo (Arg: unsigned) return string;
+ function fo (Arg: signed) return string;
+ function fo (Arg: std_logic_vector) return string;
+ function fo (Arg: std_ulogic_vector) return string;
+ function fo (Arg: bit_vector) return string;
+ function fo (Arg: integer) return string;
+ function fo (Arg: std_ulogic) return string;
+ function fo (Arg: bit) return string;
+ function fo (Arg: boolean) return string;
+ function fo (Arg: character) return string;
+ function fo (Arg: string) return string;
+ function fo (Arg: time) return string;
+
+ procedure FIO_FormatExpand (FMT: inout line;
+ Format: in string;
+ StartPointer: in positive);
+
+end PCK_FIO;
+
+
+
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
new file mode 100644
index 0000000..3d123f0
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
@@ -0,0 +1,814 @@
+---- $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----
+---- PCK_FIO: a VHDL package for C-style formatted file output
+---- Copyright (C) 1995, 2001 Easics NV
+----
+---- This library is free software; you can redistribute it and/or
+---- modify it under the terms of the GNU Lesser General Public
+---- License as published by the Free Software Foundation; either
+---- version 2.1 of the License, or (at your option) any later version.
+----
+---- This library is distributed in the hope that it will be useful,
+---- but WITHOUT ANY WARRANTY; without even the implied warranty of
+---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+---- Lesser General Public License for more details.
+----
+---- You should have received a copy of the GNU Lesser General Public
+---- License along with this library; if not, write to the Free Software
+---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----
+---- For suggestions, bug reports, enhancement requests, and info about
+---- our design services, you can contact us at the following address:
+---- http://www.easics.com
+---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
+---- tel.: +32 16 395 600 fax : +32 16 395 619
+---- e-mail: jand@easics.be (Jan Decaluwe)
+----
+
+
+ package body PCK_FIO is
+
+ --------------------------
+ -- FIO Warnings support --
+ --------------------------
+
+ procedure FIO_Warning_Fsbla (file F: text;
+ L: inout line;
+ Format: in string;
+ Pointer: in positive) is
+ begin
+ fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
+ "Format specifier beyond last argument\n");
+ fprint (F, L, "** in format string: ""%s""\n", Format);
+ fprint (F, L, "** ");
+ for i in 1 to Pointer-1 loop
+ fprint (F, L, "-");
+ end loop;
+ fprint (F, L, "^\n");
+ end FIO_Warning_Fsbla;
+
+ procedure FIO_Warning_Ufs (file F: text;
+ L: inout line;
+ Format: in string;
+ Pointer: in positive;
+ Char: in character) is
+ begin
+ fprint (F, L, "\n** Warning: FIO_PrintArg: " &
+ "Unexpected format specifier '%r'\n",
+ fo(Char));
+ fprint (F, L, "** in format string: ""%s""\n", Format) ;
+ fprint (F, L, "** ");
+ for i in 1 to Pointer-1 loop
+ fprint (F, L, "-");
+ end loop;
+ fprint (F, L, "^\n** Assuming 'q' to proceed: ");
+ end FIO_Warning_Ufs;
+
+
+ ----------------------------------
+ -- bit conversion support --
+ ----------------------------------
+
+ type T_bit_map is array(bit) of character;
+
+ constant C_BIT_MAP: T_bit_map
+ := ('0', '1');
+
+ ----------------------------------
+ -- std_logic conversion support --
+ ----------------------------------
+
+ type T_std_logic_map is array(std_ulogic) of character;
+
+ constant C_STD_LOGIC_MAP: T_std_logic_map
+ := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+
+ ------------------------------
+ -- Digit conversion support --
+ ------------------------------
+
+ -- types & constants
+
+ subtype S_digit_chars is character range '0' to '9';
+ subtype S_digits is integer range 0 to 9 ;
+
+ type T_digit_chars_map is array(S_digit_chars) of S_digits;
+
+ constant C_DIGIT_CHARS_MAP: T_digit_chars_map
+ := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+
+ type T_digits_map is array(S_digits) of S_digit_chars;
+
+ constant C_DIGITS_MAP: T_digits_map
+ := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
+
+
+ --------------------------------
+ -- Decimal conversion support --
+ --------------------------------
+
+ -- unsigned to decimal
+
+ function U_To_d (Arg: string) return integer is
+ constant Argument: string(Arg'length downto 1) := Arg;
+ variable Result: integer := 0;
+ begin
+ for i in Argument'range loop
+ case Argument(i) is when '1' => Result := 2**(i-1) + Result;
+ when '0' => null;
+ when others => return(-1);
+ end case;
+ end loop;
+ return (Result);
+ end U_To_d;
+
+ -- signed to decimal
+
+ function S_To_d (Arg: string) return integer is
+ constant Argument: string(Arg'length downto 1) := Arg;
+ variable Result: integer := 0;
+ begin
+ case Argument(Argument'left) is
+ when '1' => Result := - 2**(Argument'left-1);
+ when '0' => Result := 0;
+ when others => return (integer'low);
+ end case;
+ for i in Argument'left-1 downto 1 loop
+ case Argument(i) is when '1' => Result := 2**(i-1) + Result;
+ when '0' => null;
+ when others => return(integer'low);
+ end case;
+ end loop;
+ return (Result);
+ end S_To_d;
+
+ -- string to decimal
+
+ function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
+ constant Sign: character := Arg(1);
+ constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
+ variable Char: character;
+ variable Result: integer := 0;
+ begin
+ Result := 0;
+ for i in Value'range loop
+ Result := Result * 10;
+ Char := Value(i);
+ if (Char /= ' ') then
+ Result := Result + C_DIGIT_CHARS_MAP(Char);
+ end if;
+ end loop;
+ case Sign is when '-' => return(-Result);
+ when others => return(Result);
+ end case;
+ end I_To_d;
+
+ -- boolean (0,1) to decimal
+
+ function B_To_d (Arg: string(1 to 1)) return integer is
+ begin
+ case Arg is when "1" => return(1);
+ when "0" => return(0);
+ when others => return(-1);
+ end case;
+ end B_To_d;
+
+ -- boolean (T,F) to decimal
+
+ function L_To_d (Arg: string(1 to 1)) return integer is
+ begin
+ case Arg is when "T" => return(1);
+ when others => return(0);
+ end case;
+ end L_To_d;
+
+
+
+ ----------------------------
+ -- Hex conversion support --
+ ----------------------------
+
+ -- Constants & types
+
+ constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
+
+ -- Function to return Hex index of a nibble
+
+ function U_To_h_Index(Arg: string(4 downto 1)) return integer is
+ variable Index: integer := 0;
+ begin
+ for i in Arg'range loop
+ case Arg(i) is when '1' => Index := 2**(i-1) + Index;
+ when '0' => null;
+ when others => return (17);
+ end case;
+ end loop;
+ return (Index+1);
+ end U_To_h_Index;
+
+ -- Hex conversion
+
+ function U_To_h (Arg: string) return string is
+ variable Result: string((Arg'length-1)/4 +1 downto 1);
+ variable ExtArg: string(Result'length*4 downto 1) := (others => '0');
+ begin
+ ExtArg(Arg'length downto 1) := Arg;
+ for i in Result'range loop
+ Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));
+ end loop;
+ return (FIO_h_PRE & Result & FIO_h_POST);
+ end U_To_h;
+
+
+
+ ----------------------------
+ -- Bit conversion support --
+ ----------------------------
+
+ function L_To_b (Arg: string(1 to 1)) return string is
+ variable Result: string(1 to 1);
+ begin
+ case Arg is when "T" => Result := "1";
+ when others => Result := "0";
+ end case;
+ return(FIO_b_PRE & Result & FIO_b_POST);
+ end L_To_b;
+
+
+ function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
+ Justified: side;
+ Width: integer) return string is
+
+ variable IntValue: integer := I_To_d(Arg);
+ variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' ');
+ variable Sign: character := ' ';
+ constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
+ variable BitWidth: integer range 0 to FIO_b_WIDTH;
+ variable MsPos: integer range 1 to BitValue'length;
+ variable BitValueExtended: string(1 to 2*FIO_b_WIDTH);
+
+ begin
+
+ if (IntValue < 0) then
+ Sign := '-';
+ IntValue := -IntValue;
+ end if;
+
+ for i in BitValue'reverse_range loop
+ BitValue(i) := C_DIGITS_MAP(IntValue mod 2);
+ IntValue := IntValue / 2;
+ exit when (IntValue = 0);
+ end loop;
+
+ BitValueExtended := BitValue & Blanks;
+
+ if (Width = 0) or (Width > FIO_b_WIDTH+1) then
+ BitWidth := FIO_b_WIDTH;
+ else
+ BitWidth := Width-1;
+ end if;
+
+ if (Justified = RIGHT) then
+ return (FIO_bv_PRE &
+ Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) &
+ FIO_bv_POST);
+ else
+ for i in BitValue'range loop
+ if BitValue(i) /= ' ' then
+ MSPos := i;
+ exit;
+ end if;
+ end loop;
+ return (FIO_bv_PRE &
+ Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) &
+ FIO_bv_POST);
+ end if;
+
+ end I_To_b;
+
+
+ -----------------------------------
+ -- Reasonable conversion support --
+ -----------------------------------
+
+ function I_To_r (Arg: string(1 to FIO_d_WIDTH+1);
+ Justified: side;
+ Width: integer) return string is
+ constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
+ constant Sign: character := Arg(1);
+ constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
+ variable IntWidth: integer range 0 to FIO_d_WIDTH;
+ variable MsPos: integer range 1 to Value'length;
+ variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks;
+ begin
+ if (Width = 0) or (Width > FIO_d_WIDTH+1) then
+ IntWidth := FIO_d_WIDTH;
+ else
+ IntWidth := Width-1;
+ end if;
+ if (Justified = RIGHT) then
+ return (Sign & Value(Value'length-IntWidth+1 to Value'length));
+ else
+ for i in Value'range loop
+ if Value(i) /= ' ' then
+ MSPos := i;
+ exit;
+ end if;
+ end loop;
+ return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
+ end if;
+ end I_To_r;
+
+
+ -------------------------------------------
+ -- Reasonable output conversion function --
+ -------------------------------------------
+
+ function ReasonableOutput (Arg: string;
+ Justified: side;
+ Width: integer) return string is
+ constant Argument: string(1 to Arg'length) := Arg;
+ constant TypeSpec: string (1 to 2) := Argument(1 to 2);
+ constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
+ begin
+ case TypeSpec is
+ when "U:" | "S:" | "V:" =>
+ return U_To_h(Value);
+ when "I:" =>
+ return I_To_r(Value, Justified, Width);
+ when "B:" | "L:" | "C:" =>
+ return Value;
+ when others =>
+ return Argument;
+ end case;
+
+ end ReasonableOutput;
+
+
+ ------------------------------------
+ -- Bit output conversion function --
+ ------------------------------------
+
+ function BitOutput (Arg: string;
+ Justified: side;
+ Width: integer) return string is
+ constant Argument: string(1 to Arg'length) := Arg;
+ constant TypeSpec: string (1 to 2) := Argument(1 to 2);
+ constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
+ begin
+ case TypeSpec is
+ when "U:" | "S:" | "V:" =>
+ return (FIO_bv_PRE & Value & FIO_bv_POST);
+ when "B:" =>
+ -- Value(1 to 1) instead of Value for LeapFrog
+ return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);
+ when "I:" =>
+ return I_To_b(Value, Justified, Width);
+ when "L:" =>
+ -- Value(1 to 1) instead of Value for LeapFrog
+ return L_To_b(Value(1 to 1));
+ when others =>
+ return Argument;
+ end case;
+
+ end BitOutput;
+
+
+ -------------------------------------------
+ -- Decimal output conversion function --
+ -------------------------------------------
+
+ function DecimalOutput (Arg: string) return integer is
+ constant Argument: string(1 to Arg'length) := Arg;
+ constant TypeSpec: string (1 to 2) := Argument(1 to 2);
+ constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
+ begin
+ case TypeSpec is
+ when "U:"| "V:" =>
+ return U_To_d(Value);
+ when "S:" =>
+ return S_To_d(Value);
+ when "I:" =>
+ return I_To_d(Value);
+ when "B:" =>
+ return B_To_d(Value);
+ when "L:" =>
+ return L_To_d(Value);
+ when others =>
+ return integer'low;
+ end case;
+
+ end DecimalOutput;
+
+
+ ----------------------------
+ -- Atomic print functions --
+ ----------------------------
+
+ -- test for end of format string
+
+ function FIO_EOS (Format: in string;
+ Pointer: in integer)
+ return boolean is
+ begin
+ return (Pointer > Format'length);
+ end FIO_EOS;
+
+
+ -- Atomic value print function
+
+ procedure FIO_PrintValue (file F: text;
+ L: inout line;
+ Format: in string;
+ Pointer: inout integer;
+ Last: in boolean := FALSE) is
+ variable Char: character;
+ begin
+ while (not FIO_EOS(Format, Pointer)) loop
+ Char := Format(Pointer);
+ case Char is
+ when '\' =>
+ Pointer := Pointer + 1;
+ exit when (FIO_EOS(Format, Pointer));
+ Char := Format(Pointer);
+ case Char is when 'n' => writeline(F, L);
+ when others => write(L, Char);
+ end case;
+ when '%' =>
+ if Last then
+ FIO_Warning_Fsbla(F, L, Format, Pointer);
+ end if;
+ Pointer := Pointer + 1;
+ exit;
+ when others =>
+ write(L, char);
+ end case;
+ Pointer := Pointer + 1;
+ end loop;
+ end FIO_PrintValue;
+
+
+ ---- Atomic argument print function
+
+ procedure FIO_PrintArg (file F: text;
+ L: inout line;
+ Format: in string;
+ Pointer: inout integer;
+ Arg: in string) is
+ variable Char: character;
+ variable Justified: side;
+ variable Width: integer;
+
+ begin
+
+ FIO_PrintValue(F, L, Format, Pointer);
+
+ Justified := RIGHT;
+ Width := 0;
+ while (not FIO_EOS(Format, Pointer)) loop
+ Char := Format(Pointer);
+ case Char is
+ when '-' =>
+ Justified := LEFT;
+ Pointer := Pointer + 1;
+ when '0' to '9' =>
+ Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
+ Pointer := Pointer + 1;
+ when 'r' =>
+ write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ when 'b' =>
+ write(L, BitOutput(Arg, Justified, Width), Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ when 'd' =>
+ write(L, DecimalOutput(Arg), Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ when 'q' | 's' =>
+ write(L, Arg, Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ when others =>
+ FIO_Warning_Ufs(F, L, Format, Pointer, Char);
+ write(L, Arg, Justified, Width);
+ Pointer := Pointer + 1;
+ exit;
+ end case;
+ end loop;
+ end FIO_PrintArg;
+
+
+ -----------------------------------------------------
+ -- The format string iteration expansion procedure --
+ -----------------------------------------------------
+
+ procedure FIO_FormatExpand (FMT: inout line;
+ Format: in string;
+ StartPointer: in positive) is
+
+ variable Pointer: positive := StartPointer;
+ variable TokenStart: positive;
+ variable IterStringStart: positive;
+ variable IterStringEnd: positive;
+ variable IterCount: natural;
+ variable OpenBrackets: natural;
+ variable L: line;
+
+ begin
+
+ FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop
+
+ case Format(Pointer) is
+
+ -- look for format specifier
+ when '%' =>
+
+ -- initialize iteration token search
+ TokenStart := Pointer;
+ IterCount := 0;
+ Pointer := Pointer + 1;
+
+ -- start iteration token search
+ TOKEN_READ: while not FIO_EOS(Format, Pointer) loop
+
+ case Format(Pointer) is
+
+ -- read iteration counter
+ when '0' to '9' =>
+ IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer));
+ Pointer := Pointer + 1;
+
+ -- expect open bracket
+ when '{' =>
+
+ -- initialize iteration string read
+ OpenBrackets := 1;
+ IterStringStart := Pointer + 1;
+ Pointer := Pointer + 1;
+ -- quit prematurely when iteration count is 0
+ next FORMAT_SEARCH when (IterCount = 0);
+
+ -- start iteration string read
+ ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop
+
+ case Format(Pointer) is
+ -- keep track of open brackets
+ when '{' =>
+ OpenBrackets := OpenBrackets + 1;
+ Pointer := Pointer + 1;
+ -- when closing bracket is found, process iteration string
+ when '}' =>
+ OpenBrackets := OpenBrackets - 1;
+ if (OpenBrackets = 0) then
+ IterStringEnd := Pointer-1;
+ if (TokenStart /= 1) then
+ write(L, Format(1 to TokenStart-1));
+ end if;
+ for i in 1 to IterCount loop
+ write(L, Format(IterStringStart to IterStringEnd));
+ end loop;
+ if (IterStringEnd /= Format'length) then
+ write(L, Format(IterStringEnd+2 to Format'length));
+ end if;
+ -- call expansion procedure recursively on expanded format
+ FIO_FormatExpand(FMT, L.all, TokenStart);
+ deallocate(L);
+ return;
+ end if;
+ Pointer := Pointer + 1;
+ -- skip escaped characters
+ when '\' =>
+ Pointer := Pointer + 2;
+ -- read iteration string
+ when others =>
+ Pointer := Pointer + 1;
+
+ end case;
+
+ end loop ITER_STRING_READ;
+
+ -- stop iteration token search when no opening bracket found
+ when others =>
+ Pointer := Pointer + 1;
+ next FORMAT_SEARCH;
+
+ end case;
+
+ end loop TOKEN_READ;
+
+ -- skip escaped characters
+ when '\' =>
+ Pointer := Pointer + 2;
+
+ -- read other characters
+ when others =>
+ Pointer := Pointer + 1;
+
+ end case;
+
+ end loop FORMAT_SEARCH;
+
+ write(FMT, Format);
+ deallocate(L);
+
+ end FIO_FormatExpand;
+
+
+
+ --------------------------
+ -- The fprint procedure --
+ --------------------------
+
+ procedure fprint
+ (file F: text;
+ L: inout line;
+ Format: in string;
+ A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
+ A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
+ A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
+ A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
+ ) is
+
+ variable Pointer: integer;
+ variable FMT: line;
+
+ begin
+
+ Pointer := 1;
+
+ FIO_FormatExpand (FMT, Format, Format'low);
+
+ if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
+ if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
+ if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
+ if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
+ if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
+ if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
+ if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
+ if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
+ if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
+ if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
+ if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
+ if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
+ if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
+ if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
+ if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
+ if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
+ if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
+ if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
+ if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
+ if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
+ if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
+ if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
+ if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
+ if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
+ if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
+ if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
+ if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
+ if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
+ if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
+ if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
+ if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
+ if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
+ end if; end if; end if; end if; end if; end if; end if; end if;
+ end if; end if; end if; end if; end if; end if; end if; end if;
+ end if; end if; end if; end if; end if; end if; end if; end if;
+ end if; end if; end if; end if; end if; end if; end if; end if;
+
+ FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
+
+ deallocate(FMT);
+
+ end fprint;
+
+
+ -------------------------------------------
+ -- Formatted output conversion functions --
+ -------------------------------------------
+
+ function fo (Arg: unsigned) return string is
+ constant Argument: unsigned(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_STD_LOGIC_MAP(Argument(i));
+ end loop;
+ return ("U:" & Result);
+ end fo;
+
+ function fo (Arg: signed) return string is
+ constant Argument: signed(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_STD_LOGIC_MAP(Argument(i));
+ end loop;
+ return ("S:" & Result);
+ end fo;
+
+ function fo (Arg: std_logic_vector) return string is
+ constant Argument: std_logic_vector(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_STD_LOGIC_MAP(Argument(i));
+ end loop;
+ return ("V:" & Result);
+ end fo;
+
+ function fo (Arg: std_ulogic_vector) return string is
+ constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_STD_LOGIC_MAP(Argument(i));
+ end loop;
+ return ("V:" & Result);
+ end fo;
+
+ function fo (Arg: bit_vector) return string is
+ constant Argument: bit_vector(1 to Arg'length) := Arg;
+ variable Result: string(1 to Arg'length);
+ begin
+ for i in Argument'range loop
+ Result(i) := C_BIT_MAP(Argument(i));
+ end loop;
+ return ("V:" & Result);
+ end fo;
+
+ function fo (Arg: integer) return string is
+ variable Argument: integer := Arg;
+ variable Result: string(1 to FIO_d_WIDTH) := (others => ' ');
+ variable Sign: character := ' ';
+ begin
+ if (Argument < 0) and (Argument /= integer'low) then
+ Sign := '-';
+ Argument := -Argument;
+ end if;
+ for i in Result'reverse_range loop
+ Result(i) := C_DIGITS_MAP(Argument mod 10);
+ Argument := Argument / 10;
+ exit when (Argument = 0);
+ end loop;
+ return ("I:" & Sign & Result);
+ end fo;
+
+ function fo (Arg: std_ulogic) return string is
+ begin
+ return ("B:" & C_STD_LOGIC_MAP(Arg));
+ end fo;
+
+ function fo (Arg: bit) return string is
+ begin
+ return ("B:" & C_BIT_MAP(Arg));
+ end fo;
+
+ function fo (Arg: boolean) return string is
+ begin
+ if (ARG = TRUE) then
+ return ("L:T");
+ else
+ return ("L:F");
+ end if;
+ end fo;
+
+ function fo (Arg: character) return string is
+ begin
+ return ("C:" & Arg);
+ end fo;
+
+ -- auxilary function fgets(Arg :string)
+ -- returns index of first NUL in Arg or if no NUL is present just Arg'length
+ -- goes through Arg from 1 to Arg'length
+ function fgets (Arg: string) return integer is
+ variable index: integer := Arg'length;
+ begin
+ for i in 1 to Arg'length loop
+ if Arg(i) = NUL then
+ index := i - 1;
+ exit;
+ else
+ null;
+ end if;
+ end loop;
+ return index;
+ end fgets;
+
+ -- returns the Arg string until the first NUL was encountered
+ -- if fo is used on a string with NUL in it it will stop reading the rest
+ -- of the string, even if a larger field width has been supplied. fo will
+ -- then just pad the remaining characters with blanco's
+ function fo (Arg: string) return string is
+ begin
+ return Arg(1 to fgets(Arg));
+ end fo;
+
+ function fo (Arg: time) return string is
+ begin
+ return fo (integer (Arg / 1 ns));
+ end fo;
+
+end PCK_FIO;
+
diff --git a/lib/PCK_FIO-2002.7/README b/lib/PCK_FIO-2002.7/README
new file mode 100644
index 0000000..b16c6c5
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/README
@@ -0,0 +1,88 @@
+---- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----
+---- PCK_FIO: a VHDL package for C-style formatted file output
+---- Copyright (C) 1995, 2001 Easics NV
+----
+---- This library is free software; you can redistribute it and/or
+---- modify it under the terms of the GNU Lesser General Public
+---- License as published by the Free Software Foundation; either
+---- version 2.1 of the License, or (at your option) any later version.
+----
+---- This library is distributed in the hope that it will be useful,
+---- but WITHOUT ANY WARRANTY; without even the implied warranty of
+---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+---- Lesser General Public License for more details.
+----
+---- You should have received a copy of the GNU Lesser General Public
+---- License along with this library; if not, write to the Free Software
+---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----
+---- For suggestions, bug reports, enhancement requests, and info about
+---- our design services, you can contact us at the following address:
+---- http://www.easics.com
+---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
+---- tel.: +32 16 395 600 fax : +32 16 395 619
+---- e-mail: jand@easics.be (Jan Decaluwe)
+----
+
+Version 2002.07
+===============
+
+Contents
+========
+
+This distribution contains the following files:
+
+ PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package
+ PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package
+ PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package
+ PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package
+ TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO
+ TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO
+ PCK_FIO.out.gold: Certified test bench output
+ PCK_FIO.html: Manual for PCK_FIO in html format
+ README: This file
+
+
+Installation
+============
+
+VHDL-1987
+---------
+To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
+analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library.
+
+To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library.
+
+VHDL-1993
+---------
+To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
+analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library.
+
+To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library.
+
+Numeric packages
+----------------
+If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need
+to edit the source code of the package, both header and body, and the test bench
+and replace the package use clause. PCK_FIO works with either of these packages.
+
+Documentation
+-------------
+To install the documentation, put the file point PCK_FIO.html in a path of
+your choosing, point your web browser to it, and bookmark it.
+
+
+Installation check
+==================
+
+After installing the test bench, you should run it. The corresponding VHDL
+design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
+
+Simulating the test bench should create a file called PCK_FIO.out. This file
+should be identical to PCK_FIO.out.gold. Any difference indicates a portability
+issue or a simulator non-compliance or bug.
+
+
+
+
diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd
new file mode 100644
index 0000000..2e18ff4
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd
@@ -0,0 +1,531 @@
+---- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----
+---- PCK_FIO: a VHDL package for C-style formatted file output
+---- Copyright (C) 1995, 2001 Easics NV
+----
+---- This library is free software; you can redistribute it and/or
+---- modify it under the terms of the GNU Lesser General Public
+---- License as published by the Free Software Foundation; either
+---- version 2.1 of the License, or (at your option) any later version.
+----
+---- This library is distributed in the hope that it will be useful,
+---- but WITHOUT ANY WARRANTY; without even the implied warranty of
+---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+---- Lesser General Public License for more details.
+----
+---- You should have received a copy of the GNU Lesser General Public
+---- License along with this library; if not, write to the Free Software
+---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----
+---- For suggestions, bug reports, enhancement requests, and info about
+---- our design services, you can contact us at the following address:
+---- http://www.easics.com
+---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
+---- tel.: +32 16 395 600 fax : +32 16 395 619
+---- e-mail: jand@easics.be (Jan Decaluwe)
+----
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- signed/unsigned definition: use either std_logic_arith or numeric_std
+-- use IEEE.std_logic_arith.all; -- the Synopsys one
+ use IEEE.numeric_std.all;
+
+use STD.TEXTIO.all;
+
+library EASICS_PACKAGES;
+use EASICS_PACKAGES.PCK_FIO.all;
+
+entity TBE_PCK_FIO is
+
+end TBE_PCK_FIO;
+
+architecture TB of TBE_PCK_FIO is
+
+begin
+
+USAGE: process
+
+ file RESULT: text is out "PCK_FIO.out";
+ variable L: line;
+ variable Pointer: integer;
+ variable BoolTrue: boolean := TRUE;
+ variable BoolFalse: boolean := FALSE;
+ variable IntPos: integer := 5678;
+ variable BigIntPos: integer := 12345678;
+ variable IntNeg: integer := -8765;
+ variable BigIntNeg: integer := -87654321;
+ variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
+ variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
+ variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
+ variable SigPos: signed(6 downto 0) := signed'("0010010");
+ variable SigNeg: signed(6 downto 0) := signed'("1010010");
+ variable BitX: std_logic := 'X';
+ variable Bit1: std_logic := '1';
+ variable Bit0: std_logic := '0';
+
+ variable parameter_1: integer := 1234;
+ variable parameter_2: integer := 2345;
+ variable parameter_3: integer := 4567;
+
+ constant TempString: string :="ABC" & NUL & "DEF";
+begin
+
+fprint(RESULT, L,
+ "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
+ "-----------------------------------------\n\n" &
+ "This is the result of running the PCK_FIO testbench.\n" &
+ "This file should be compared with PCK_FIO.out.gold, which is\n" &
+ "the reference output. Any difference indicates a portability\n" &
+ "issue or a simulator non-compliance or bug.\n\n"
+ );
+
+
+fprint(RESULT, L,
+ "\n--------------------\n" &
+ "-- Basic features --\n" &
+ "--------------------\n\n"
+ );
+
+fprint(RESULT, L,
+ "-- First some auxiliary declarations\n"
+ );
+
+fprint(RESULT, L,
+ "> file RESULT: text is out ""PCK_FIO.out"";\n" &
+ "> variable L: line;\n" &
+ "> variable BoolTrue: boolean := TRUE;\n" &
+ "> variable BoolFalse: boolean := FALSE;\n" &
+ "> variable IntPos: integer := 5678;\n" &
+ "> variable BigIntPos: integer := 12345678;\n" &
+ "> variable IntNeg: integer := -8765;\n" &
+ "> variable BigIntNeg: integer := -87654321;\n" &
+ "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
+ "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
+ "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
+ "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
+ "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
+ "> variable BitX: std_logic := 'X';\n" &
+ "> variable Bit1: std_logic := '1';\n" &
+ "> variable Bit0: std_logic := '0';\n" &
+ "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
+);
+
+
+fprint(RESULT, L,
+ "\n\n-- fprint call with no arguments\n" &
+ "> fprint(RESULT, L, ""No arguments.\\n"");\n"
+ );
+fprint(RESULT, L, "No arguments.\n");
+
+
+fprint(RESULT, L,
+ "\n-- Special characters need to be escaped\n" &
+ "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
+ );
+
+fprint(RESULT, L, "Special characters: \% \\ "" \n");
+
+
+fprint(RESULT, L,
+ "\n-- Various format specifiers interprete the same object differently\n" &
+ "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
+ "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
+ "> );\n"
+ );
+
+fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
+ fo(Uns), fo(Uns), fo(Uns), fo(Uns)
+ );
+
+fprint(RESULT, L,
+ "\n-- Format string can be shortened by using the iteration specifier\n" &
+ "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
+ "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
+ "> );\n"
+ );
+
+fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
+ fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
+ );
+fprint(RESULT, L,
+ "\n-------------------------------\n"&
+ "--Testing string manipulation--\n"&
+ "-------------------------------\n");
+fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
+ & " & NUL & ""DEF""\n");
+-- temp_string: string:="ABC"&NUL&"DEF"
+-- test for detecting NUL in string
+fprint(RESULT, L, "\n--test for NUL ending in strings\n");
+fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
+fprint(RESULT, L, fo(TempString));
+
+-- direct inclusion of string in fprint should give whole string
+fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
+fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
+fprint(RESULT, L, TempString & "\n");
+
+-- influence of given width
+
+fprint(RESULT, L, "\n--if there are less characters in the given string then"
+ & " in the width fo will\n"&
+ "-- pad the remaining with blanco's according to the given justification\n");
+fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
+fprint(RESULT, L, "%5s", fo(TempString));
+fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
+fprint(RESULT, L, "%-5s",fo(TempString));
+fprint(RESULT, L, "\n--with specified width without fo\n");
+fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
+fprint(RESULT, L, "%9s", TempString);
+fprint(RESULT, L, "\n\n-- if the width is smaller then the number" &
+ " of characters in the string fprint\n" &
+ "-- will output the string with the minimum of characters needed\n");
+fprint(RESULT, L, "\n--with specified width,using fo\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
+fprint(RESULT, L, "%2s",fo(TempString));
+fprint(RESULT, L, "\n--with specified width without fo\n");
+fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
+fprint(RESULT, L, "%4s", TempString);
+
+
+fprint(RESULT, L,
+ "\n\n------------------------------------\n" &
+ "-- Support for bit-oriented types --\n" &
+ "------------------------------------\n"
+ );
+
+fprint (RESULT, L, "\n-- Reasonable format\n" &
+ "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
+ "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
+ "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
+ "> );\n"
+ );
+
+
+fprint(RESULT, L, "Reasonable format: %9{%r }\n",
+ fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
+ fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
+ );
+
+fprint (RESULT, L, "\n-- Decimal format\n" &
+ "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
+ "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
+ "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
+ "> );\n"
+ );
+
+
+fprint(RESULT, L, "Decimal format: %9{%d }\n",
+ fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
+ fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
+ );
+
+fprint (RESULT, L, "\n-- Bit format\n" &
+ "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
+ "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
+ "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
+ "> );\n"
+ );
+
+
+fprint(RESULT, L, "Bit format: %9{%b }\n",
+ fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
+ fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
+ );
+
+fprint(RESULT, L,
+ "\n\n" &
+ "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n"
+ );
+
+
+fprint(RESULT, L, "\n" &
+ "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" &
+ "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
+
+ "> );\n"
+ );
+
+fprint(RESULT, L,
+ "\n" &
+ "-- Results of the call with various format specifiers\n\n"
+ );
+
+fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "\n");
+
+
+
+fprint(RESULT, L,
+ "\n-------------------------------\n" &
+ "-- Support for integer types --\n" &
+ "-------------------------------\n"
+ );
+
+fprint(RESULT, L,
+ "\n\n" &
+ "-- Template of the call: ( stands for the format specifier)\n"
+ );
+
+
+fprint(RESULT, L, "\n" &
+ "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" &
+ "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
+
+ "> );\n"
+ );
+
+fprint(RESULT, L,
+ "\n" &
+ "-- Results of the call with various format specifiers\n\n"
+ );
+
+
+fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+
+
+fprint(RESULT, L,
+ "\n----------------------\n" &
+ "-- Support for time --\n" &
+ "----------------------\n"
+ );
+
+fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
+ "-- into an integer value (of nanoseconds)\n"
+ );
+fprint (RESULT, L, "> wait for 648 ns\n");
+fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
+
+wait for 648 ns;
+
+fprint (RESULT, L, "The time is now %d ns\n", fo(now));
+
+
+fprint(RESULT, L,
+ "\n----------------------------------------\n" &
+ "-- Erroneous calls and error messages --\n" &
+ "----------------------------------------\n"
+ );
+
+fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
+ "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
+ );
+
+fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
+
+fprint(RESULT, L, "\n");
+
+fprint(RESULT, L, "-- Unsupported format specifier\n" &
+ "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
+ "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
+ );
+
+fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
+
+fprint(RESULT, L, "\n");
+
+fprint(RESULT, L,
+ "\n----------------------------------------\n" &
+ "-- Things you wouldn't expect to work --\n" &
+ "----------------------------------------\n"
+ );
+
+fprint(RESULT, L, "\n-- Nested iteration\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
+fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
+
+wait;
+
+end process USAGE;
+
+end TB;
+
+
diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd
new file mode 100644
index 0000000..0386a11
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd
@@ -0,0 +1,536 @@
+---- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+----
+---- PCK_FIO: a VHDL package for C-style formatted file output
+---- Copyright (C) 1995, 2001 Easics NV
+----
+---- This library is free software; you can redistribute it and/or
+---- modify it under the terms of the GNU Lesser General Public
+---- License as published by the Free Software Foundation; either
+---- version 2.1 of the License, or (at your option) any later version.
+----
+---- This library is distributed in the hope that it will be useful,
+---- but WITHOUT ANY WARRANTY; without even the implied warranty of
+---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+---- Lesser General Public License for more details.
+----
+---- You should have received a copy of the GNU Lesser General Public
+---- License along with this library; if not, write to the Free Software
+---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----
+---- For suggestions, bug reports, enhancement requests, and info about
+---- our design services, you can contact us at the following address:
+---- http://www.easics.com
+---- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
+---- tel.: +32 16 395 600 fax : +32 16 395 619
+---- e-mail: jand@easics.be (Jan Decaluwe)
+----
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- signed/unsigned definition: use either std_logic_arith or numeric_std
+-- use IEEE.std_logic_arith.all; -- the Synopsys one
+use IEEE.numeric_std.all;
+
+use STD.TEXTIO.all;
+
+library EASICS_PACKAGES;
+use EASICS_PACKAGES.PCK_FIO.all;
+
+entity TBE_PCK_FIO is
+
+end TBE_PCK_FIO;
+
+architecture TB of TBE_PCK_FIO is
+
+begin
+
+USAGE: process
+
+ file RESULT: text open write_mode is "PCK_FIO.out";
+ variable L: line;
+ variable Pointer: integer;
+ variable BoolTrue: boolean := TRUE;
+ variable BoolFalse: boolean := FALSE;
+ variable IntPos: integer := 5678;
+ variable BigIntPos: integer := 12345678;
+ variable IntNeg: integer := -8765;
+ variable BigIntNeg: integer := -87654321;
+ variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
+ variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
+ variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
+ variable SigPos: signed(6 downto 0) := signed'("0010010");
+ variable SigNeg: signed(6 downto 0) := signed'("1010010");
+ variable BitX: std_logic := 'X';
+ variable Bit1: std_logic := '1';
+ variable Bit0: std_logic := '0';
+
+ variable parameter_1: integer := 1234;
+ variable parameter_2: integer := 2345;
+ variable parameter_3: integer := 4567;
+
+ constant TempString: string :="ABC" & NUL & "DEF";
+begin
+
+fprint(RESULT, L,
+ "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
+ "-----------------------------------------\n\n" &
+ "This is the result of running the PCK_FIO testbench.\n" &
+ "This file should be compared with PCK_FIO.out.gold, which is\n" &
+ "the reference output. Any difference indicates a portability\n" &
+ "issue or a simulator non-compliance or bug.\n\n"
+ );
+
+
+fprint(RESULT, L,
+ "\n--------------------\n" &
+ "-- Basic features --\n" &
+ "--------------------\n\n"
+ );
+
+fprint(RESULT, L,
+ "-- First some auxiliary declarations\n"
+ );
+
+fprint(RESULT, L,
+ "> file RESULT: text is out ""PCK_FIO.out"";\n" &
+ "> variable L: line;\n" &
+ "> variable BoolTrue: boolean := TRUE;\n" &
+ "> variable BoolFalse: boolean := FALSE;\n" &
+ "> variable IntPos: integer := 5678;\n" &
+ "> variable BigIntPos: integer := 12345678;\n" &
+ "> variable IntNeg: integer := -8765;\n" &
+ "> variable BigIntNeg: integer := -87654321;\n" &
+ "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
+ "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
+ "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
+ "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
+ "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
+ "> variable BitX: std_logic := 'X';\n" &
+ "> variable Bit1: std_logic := '1';\n" &
+ "> variable Bit0: std_logic := '0';\n" &
+ "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
+);
+
+
+fprint(RESULT, L,
+ "\n\n-- fprint call with no arguments\n" &
+ "> fprint(RESULT, L, ""No arguments.\\n"");\n"
+ );
+fprint(RESULT, L, "No arguments.\n");
+
+
+fprint(RESULT, L,
+ "\n-- Special characters need to be escaped\n" &
+ "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
+ );
+
+fprint(RESULT, L, "Special characters: \% \\ "" \n");
+
+
+fprint(RESULT, L,
+ "\n-- Various format specifiers interprete the same object differently\n" &
+ "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
+ "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
+ "> );\n"
+ );
+
+fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
+ fo(Uns), fo(Uns), fo(Uns), fo(Uns)
+ );
+
+fprint(RESULT, L,
+ "\n-- Format string can be shortened by using the iteration specifier\n" &
+ "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
+ "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
+ "> );\n"
+ );
+
+fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
+ fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
+ );
+fprint(RESULT, L,
+ "\n-------------------------------\n"&
+ "--Testing string manipulation--\n"&
+ "-------------------------------\n");
+fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
+ & " & NUL & ""DEF""\n");
+-- TempString: string:="ABC" & NUL & "DEF"
+-- test for detecting NUL in string
+fprint(RESULT, L ,"\n--test for NUL ending in strings\n");
+fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
+fprint(RESULT, L, fo(TempString));
+
+-- direct inclusion of string in fprint should give whole string
+fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
+fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
+fprint(RESULT, L, TempString & "\n");
+
+-- influence of given width
+
+fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"&
+ "-- pad the remaining with blanco's according to the given justification\n");
+fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
+fprint(RESULT, L, "%5s", fo(TempString));
+fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
+fprint(RESULT, L, "%-5s", fo(TempString));
+fprint(RESULT, L, "\n--with specified width without fo\n");
+fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
+fprint(RESULT, L, "%9s", TempString);
+fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"&
+ "-- will output the string with the minimum of characters needed\n");
+fprint(RESULT, L, "\n--with specified width,using fo\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
+fprint(RESULT, L, "%2s", fo(TempString));
+fprint(RESULT, L, "\n--with specified width without fo\n");
+fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
+fprint(RESULT, L, "%4s", TempString);
+
+fprint(RESULT, L,
+ "\n\n------------------------------------\n" &
+ "-- Support for bit-oriented types --\n" &
+ "------------------------------------\n"
+ );
+
+fprint (RESULT, L, "\n-- Reasonable format\n" &
+ "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
+ "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
+ "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
+ "> );\n"
+ );
+
+
+fprint(RESULT, L, "Reasonable format: %9{%r }\n",
+ fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
+ fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
+ );
+
+fprint (RESULT, L, "\n-- Decimal format\n" &
+ "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
+ "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
+ "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
+ "> );\n"
+ );
+
+
+fprint(RESULT, L, "Decimal format: %9{%d }\n",
+ fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
+ fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
+ );
+
+fprint (RESULT, L, "\n-- Bit format\n" &
+ "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
+ "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
+ "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
+ "> );\n"
+ );
+
+
+fprint(RESULT, L, "Bit format: %9{%b }\n",
+ fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
+ fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
+ );
+
+fprint(RESULT, L,
+ "\n\n" &
+ "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n"
+ );
+
+
+fprint(RESULT, L, "\n" &
+ "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" &
+ "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
+ "> );\n"
+ );
+
+fprint(RESULT, L,
+ "\n" &
+ "-- Results of the call with various format specifiers\n\n"
+ );
+
+fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
+ fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
+ );
+fprint(RESULT, L, "\n");
+
+
+
+fprint(RESULT, L,
+ "\n-------------------------------\n" &
+ "-- Support for integer types --\n" &
+ "-------------------------------\n"
+ );
+
+fprint(RESULT, L,
+ "\n\n" &
+ "-- Template of the call: ( stands for the format specifier)\n"
+ );
+
+
+fprint(RESULT, L, "\n" &
+ "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" &
+ "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
+
+ "> );\n"
+ );
+
+fprint(RESULT, L,
+ "\n" &
+ "-- Results of the call with various format specifiers\n\n"
+ );
+
+
+fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
+ fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
+ );
+fprint(RESULT, L, "\n");
+
+
+fprint(RESULT, L,
+ "\n----------------------\n" &
+ "-- Support for time --\n" &
+ "----------------------\n"
+ );
+
+fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
+ "-- into an integer value (of nanoseconds)\n"
+ );
+fprint (RESULT, L, "> wait for 648 ns\n");
+fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
+
+wait for 648 ns;
+
+fprint (RESULT, L, "The time is now %d ns\n", fo(now));
+
+
+fprint(RESULT, L,
+ "\n----------------------------------------\n" &
+ "-- Erroneous calls and error messages --\n" &
+ "----------------------------------------\n"
+ );
+
+fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
+ "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
+ );
+
+fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
+
+fprint(RESULT, L, "\n");
+
+fprint(RESULT, L, "-- Unsupported format specifier\n" &
+ "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
+ "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
+ );
+
+fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
+
+fprint(RESULT, L, "\n");
+
+fprint(RESULT, L,
+ "\n----------------------------------------\n" &
+ "-- Things you wouldn't expect to work --\n" &
+ "----------------------------------------\n"
+ );
+
+fprint(RESULT, L, "\n-- Nested iteration\n");
+fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
+fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
+
+wait;
+
+end process USAGE;
+
+end TB;
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987
new file mode 100644
index 0000000..c5a4a92
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987
@@ -0,0 +1,34 @@
+### msMakefile generated by vma on Thu Oct 4 17:33:56 CEST 2001
+
+ANALYZER = vcom -quiet -nologo
+ANALYZER_C = vcom -quiet -nologo
+all : \
+ bin/tbe_pck_fio/tb.dat \
+ bin/tbe_pck_fio/_primary.dat
+
+# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB)
+# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO
+
+bin/tbe_pck_fio/tb.dat \
+bin/tbe_pck_fio/_primary.dat : \
+ bin/pck_fio/body.dat \
+ bin/pck_fio/_primary.dat \
+ TB_PCK_FIO_1987.vhd
+ ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd
+
+
+# Prerequisites for package body EASICS_PACKAGES.PCK_FIO()
+
+bin/pck_fio/body.dat : \
+ bin/pck_fio/_primary.dat \
+ PCK_FIO_1987_BODY.vhd
+ ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd
+
+
+# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO
+
+bin/pck_fio/_primary.dat : \
+ PCK_FIO_1987.vhd
+ ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd
+
+
diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993
new file mode 100644
index 0000000..0f9a351
--- /dev/null
+++ b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993
@@ -0,0 +1,34 @@
+### msMakefile generated by vma on Thu Oct 4 17:32:23 CEST 2001
+
+ANALYZER = vcom -quiet -nologo -93
+ANALYZER_C = vcom -quiet -nologo -93
+all : \
+ bin/tbe_pck_fio/tb.dat \
+ bin/tbe_pck_fio/_primary.dat
+
+# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB)
+# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO
+
+bin/tbe_pck_fio/tb.dat \
+bin/tbe_pck_fio/_primary.dat : \
+ bin/pck_fio/body.dat \
+ bin/pck_fio/_primary.dat \
+ TB_PCK_FIO_1993.vhd
+ ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd
+
+
+# Prerequisites for package body EASICS_PACKAGES.PCK_FIO()
+
+bin/pck_fio/body.dat : \
+ bin/pck_fio/_primary.dat \
+ PCK_FIO_1993_BODY.vhd
+ ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd
+
+
+# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO
+
+bin/pck_fio/_primary.dat : \
+ PCK_FIO_1993.vhd
+ ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd
+
+
diff --git a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj b/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj
new file mode 100644
index 0000000..ba54b14
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj
@@ -0,0 +1,13 @@
+vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_config.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\dpram.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
+vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do b/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do
new file mode 100644
index 0000000..16b23bb
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do
@@ -0,0 +1,6 @@
+vlib simprim
+
+vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
+vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd
+vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd
+vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do b/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do
new file mode 100644
index 0000000..d35d8c9
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do
@@ -0,0 +1,6 @@
+vlib unisim
+
+vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd
+vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd
+vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd
+vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo
new file mode 100644
index 0000000..7af84ba
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo
@@ -0,0 +1,27 @@
+## NOTE: Do not edit this file.
+##
+
+vlib work
+vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit -93 "../src/fifo_sync.vhd"
+vcom -explicit -93 "../src/sdram_config.vhd"
+vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
+vcom -explicit -93 "../src/clockgen_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_cmd.vhd"
+vcom -explicit -93 "../src/sdram_ctrl.vhd"
+vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit -93 "../src/mt46v16m16.vhd"
+vcom -explicit -93 "../src/tb_sdr_ctrl.vhd"
+
+#restart -force
+vsim -t 1ps -lib work tb_sdr_ctrl
+do {tb_sdr_ctrl.wdo}
+view wave
+view structure
+view signals
+run 800us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo
new file mode 100644
index 0000000..4a9d3f1
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo
@@ -0,0 +1,93 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_full
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_re
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_we
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
+add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
+add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 4} {14963876 ps} 0}
+configure wave -namecolwidth 184
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {14733925 ps} {15711632 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo
new file mode 100644
index 0000000..4f1cf1c
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo
@@ -0,0 +1,27 @@
+## NOTE: Do not edit this file.
+##
+
+vlib work
+vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit -93 "../src/fifo_sync.vhd"
+vcom -explicit -93 "../src/sdram_config.vhd"
+vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
+vcom -explicit -93 "../src/clockgen_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_cmd.vhd"
+vcom -explicit -93 "../src/sdram_ctrl.vhd"
+vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit -93 "../src/mt46v16m16.vhd"
+vcom -explicit -93 "../src/tb_sdr_ctrl_fifo.vhd"
+
+#restart -force
+vsim -t 1ps -lib work tb_sdr_ctrl_fifo
+do {tb_sdr_ctrl_fifo.wdo}
+view wave
+view structure
+view signals
+run 20us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo
new file mode 100644
index 0000000..4088038
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo
@@ -0,0 +1,68 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/clk_out
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/rst_out
+add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
+add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cas_n
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cs_n
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_ras_n
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_we_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_addr
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_busy
+add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/u_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_cmd_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_r
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_data_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_w
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_rd
+add wave -noupdate -divider {Read FIFO}
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/was_write
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr_next
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw_next
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_full
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_empty
+add wave -noupdate -divider {Write FIFO}
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr_next
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw
+add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw_next
+add wave -noupdate -divider {Command FIFO}
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_full
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 4} {13893123 ps} 0}
+configure wave -namecolwidth 172
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {13879998 ps} {13928553 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo
new file mode 100644
index 0000000..eee9b52
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo
@@ -0,0 +1,27 @@
+## NOTE: Do not edit this file.
+##
+
+vlib work
+vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit -93 "../src/fifo_sync.vhd"
+vcom -explicit -93 "../src/sdram_config.vhd"
+vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
+vcom -explicit -93 "../src/clockgen_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_cmd.vhd"
+vcom -explicit -93 "../src/sdram_ctrl.vhd"
+vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit -93 "../src/mt46v16m16.vhd"
+vcom -explicit -93 "../src/tb_sdr_ctrl_lin_r_rand_w.vhd"
+
+#restart -force
+vsim -t 1ps -lib work tb_sdr_ctrl
+do {tb_sdr_ctrl_lin_r_rand_w.wdo}
+view wave
+view structure
+view signals
+run 1200us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo
new file mode 100644
index 0000000..542c24b
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo
@@ -0,0 +1,87 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
+add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
+add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {21725359 ps} {22204052 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo
new file mode 100644
index 0000000..4716a01
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo
@@ -0,0 +1,27 @@
+## NOTE: Do not edit this file.
+##
+
+vlib work
+vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit -93 "../src/fifo_sync.vhd"
+vcom -explicit -93 "../src/sdram_config.vhd"
+vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
+vcom -explicit -93 "../src/clockgen_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_cmd.vhd"
+vcom -explicit -93 "../src/sdram_ctrl.vhd"
+vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit -93 "../src/mt46v16m16.vhd"
+vcom -explicit -93 "../src/tb_sdr_ctrl_lin_w_rand_r.vhd"
+
+#restart -force
+vsim -t 1ps -lib work tb_sdr_ctrl
+do {tb_sdr_ctrl_lin_w_rand_r.wdo}
+view wave
+view structure
+view signals
+run 1200us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo
new file mode 100644
index 0000000..542c24b
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo
@@ -0,0 +1,87 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
+add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
+add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {21725359 ps} {22204052 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo
new file mode 100644
index 0000000..9be2261
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo
@@ -0,0 +1,27 @@
+## NOTE: Do not edit this file.
+##
+
+vlib work
+vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit -93 "../src/fifo_sync.vhd"
+vcom -explicit -93 "../src/sdram_config.vhd"
+vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
+vcom -explicit -93 "../src/clockgen_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_cmd.vhd"
+vcom -explicit -93 "../src/sdram_ctrl.vhd"
+vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit -93 "../src/mt46v16m16.vhd"
+vcom -explicit -93 "../src/tb_sdr_ctrl_rand_addr.vhd"
+
+#restart -force
+vsim -t 1ps -lib work tb_sdr_ctrl
+do {tb_sdr_ctrl_rand_rw.wdo}
+view wave
+view structure
+view signals
+run 1000us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo
new file mode 100644
index 0000000..eb20b08
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo
@@ -0,0 +1,82 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
+add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
+add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 4} {60573747 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {60552548 ps} {60600861 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo
new file mode 100644
index 0000000..c868866
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo
@@ -0,0 +1,27 @@
+## NOTE: Do not edit this file.
+##
+
+vlib work
+vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit -93 "../src/fifo_sync.vhd"
+vcom -explicit -93 "../src/sdram_config.vhd"
+vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
+vcom -explicit -93 "../src/clockgen_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_cmd.vhd"
+vcom -explicit -93 "../src/sdram_ctrl.vhd"
+vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit -93 "../src/mt46v16m16.vhd"
+vcom -explicit -93 "../src/tb_sdr_ctrl_rand_rw.vhd"
+
+#restart -force
+vsim -t 1ps -lib work tb_sdr_ctrl
+do {tb_sdr_ctrl_rand_rw.wdo}
+view wave
+view structure
+view signals
+run 10000us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo
new file mode 100644
index 0000000..e3087e6
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo
@@ -0,0 +1,84 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst
+add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
+add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
+add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
+add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
+add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -divider {Main controller}
+add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
+add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
+add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
+add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
+add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
+add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
+add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 4} {16004147 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {15914249 ps} {16324366 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo
new file mode 100644
index 0000000..dbf023a
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo
@@ -0,0 +1,28 @@
+## NOTE: Do not edit this file.
+##
+
+vlib work
+vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
+vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
+vcom -explicit -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit -93 "../src/fifo_sync.vhd"
+vcom -explicit -93 "../src/sdram_config.vhd"
+vcom -explicit -93 "../src/sdram_types.vhd"
+vcom -explicit -93 "../src/reset_virtex4.vhd"
+vcom -explicit -93 "../src/clockgen_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_cmd.vhd"
+vcom -explicit -93 "../src/sdram_ctrl.vhd"
+vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit -93 "../src/sdram_ctrl_frontend.vhd"
+vcom -explicit -93 "../src/mt46v16m16.vhd"
+vcom -explicit -93 "../src/tb_sdram_ctrl_frontend.vhd"
+
+#restart -force
+vsim -t 1ps -lib work tb_sdram_ctrl_frontend
+do {tb_sdram_ctrl_frontend.wdo}
+view wave
+view structure
+view signals
+run 40us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo
new file mode 100644
index 0000000..565f89c
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo
@@ -0,0 +1,45 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/addr
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/busy
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/en
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/r_wn
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/din
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/be
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/dout_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout_reg
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/clk_out
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cs_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_we_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_ras_n
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cas_n
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_ba
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_dm
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_data
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_busy
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
+add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/sdr_cmd_busy
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full
+add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 4} {27951315 ps} 0}
+configure wave -namecolwidth 172
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {42 us}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd
new file mode 100644
index 0000000..c924c8c
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd
@@ -0,0 +1,240 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Clock generator (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library ieee, work;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clockgen is
+ generic
+ (
+ read_phaseshift : integer := 0;
+ frequency_hz : integer := 100E6
+ );
+ port
+ (
+ -- Clocks and Reset
+ rst : in std_logic; -- external async reset, low active
+ clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
+ clk_fb_in : in std_logic; -- feedback clock
+ read_clk0_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 0°
+ read_clk270_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 270°
+ sys_clk0_out : out std_logic; -- System clock, dcm#0 output 0°
+ sys_clk270_out : out std_logic; -- System clock, dcm#0 output 270°
+ locked_out : out std_logic; -- DCM locked status
+ error_out : out std_logic -- indicates DCM Errors
+ );
+
+end;
+
+architecture tech of clockgen is
+
+ constant CLKIN_PER : real := real(1000E6/frequency_hz);
+
+ signal locked : unsigned(1 downto 0);
+ signal dcm_rst : unsigned(1 downto 0);
+ signal read_clk0 : std_logic;
+ signal read_clk270 : std_logic;
+ signal read_clk0_bufg : std_logic;
+ signal read_clk270_bufg : std_logic;
+ signal sys_clk0 : std_logic;
+ signal sys_clk270 : std_logic;
+ signal sys_clk0_bufg : std_logic;
+ signal sys_clk270_bufg : std_logic;
+ signal dcm1_locked, dcm2_locked : unsigned(2 downto 0);
+ signal cnt_q : unsigned(4 downto 0);
+
+ type STATE_TYPE is (s0, s1, s2, s3, s4);
+ signal state_q : STATE_TYPE;
+
+begin
+
+ read_clk0_out <= read_clk0_bufg;
+ read_clk270_out <= read_clk270_bufg;
+ sys_clk0_out <= sys_clk0_bufg;
+ sys_clk270_out <= sys_clk270_bufg;
+
+bufg11: bufg
+ port map
+ (
+ o => sys_clk0_bufg,
+ i => sys_clk0
+ );
+
+bufg12: bufg
+ port map (
+ o => sys_clk270_bufg,
+ i => sys_clk270
+ );
+
+bufg13: bufg
+ port map
+ (
+ o => read_clk0_bufg,
+ i => read_clk0
+ );
+
+bufg14: bufg
+ port map (
+ o => read_clk270_bufg,
+ i => read_clk270
+ );
+
+ -------------------------------------------------------------------------------------------------------
+ -- Clock generation
+ -------------------------------------------------------------------------------------------------------
+
+inst_DCM_BASE_0 : DCM_BASE
+ generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
+ CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+ CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
+ CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+ CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
+ DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+ DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
+ DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ -- an integer from 0 to 15
+ DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
+ DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
+ PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
+ STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ port map (
+ CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput
+ CLK180 => open, -- 180 degree DCM CLK output
+ CLK270 => sys_clk270, -- 270 degree DCM CLK output
+ CLK2X => open, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => open, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => open, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => locked(0), -- DCM LOCK status output
+ CLKFB => clk_fb_in, -- DCM clock feedback
+ CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
+ RST => dcm_rst(0) -- DCM asynchronous reset input
+ );
+
+ inst_DCM_BASE_1 : DCM_BASE
+ generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
+ CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
+ CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
+ CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
+ CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
+ DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
+ DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ -- an integer from 0 to 15
+ DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
+ DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
+ PHASE_SHIFT => read_phaseshift, -- Amount of fixed phase shift from -255 to 1023
+ STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ port map (
+ CLK0 => read_clk0, -- 0 degree DCM CLK ouptput
+ CLK180 => open, -- 180 degree DCM CLK output
+ CLK270 => read_clk270, -- 270 degree DCM CLK output
+ CLK2X => open, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => open, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => open, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => locked(1), -- DCM LOCK status output
+ CLKFB => read_clk0_bufg, -- DCM clock feedback
+ CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
+ RST => dcm_rst(1) -- DCM asynchronous reset input
+ );
+
+ dcm_rst(1) <= not locked(0);
+
+dcm_fsm:
+ process(rst, clk_in)
+ begin
+ if rst = '1' then
+ state_q <= s0;
+ dcm_rst(0) <= '0';
+ cnt_q <= "11111";
+ error_out <= '0';
+ locked_out <= '0';
+ dcm1_locked <= (others => '0');
+ dcm2_locked <= (others => '0');
+ elsif rising_edge(clk_in) then
+ case state_q is
+ when s0 =>
+ state_q <= s1;
+
+ when s1 =>
+ cnt_q <= cnt_q - 1;
+ if cnt_q = 0 then
+ dcm_rst(0) <= '1';
+ state_q <= s2;
+ end if;
+
+ when s2 =>
+ cnt_q <= cnt_q - 1;
+ if cnt_q = 0 then
+ dcm_rst(0) <= '0';
+ state_q <= s3;
+ end if;
+
+ when s3 =>
+ if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
+ state_q <= s4;
+ error_out <= '0';
+ end if;
+
+ when s4 =>
+ if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
+ locked_out <= '1';
+ else
+ error_out <= '1';
+ end if;
+ end case;
+
+ -- synchronize 'dcm1_locked'
+ dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
+ dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
+
+ end if;
+ end process;
+
+end architecture tech;
+
+
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd
new file mode 100644
index 0000000..1494c9b
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd
@@ -0,0 +1,370 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: DDR physical layer (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity ddr_phy is
+ Port (
+ sys_rst : in STD_LOGIC;
+ sys_clk0 : in STD_LOGIC;
+ sys_clk270 : in STD_LOGIC;
+ u_tag_in : in user_tag_t;
+ u_tag_rd : out user_tag_t;
+ u_tag_wr : out user_tag_t;
+ read_clk : in STD_LOGIC;
+ phy_ctrl : in phy_ctrl_t;
+ part_ctrl : in part_ctrl_t;
+ sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0);
+ sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0);
+ sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0);
+ sdr_data_vld : out STD_LOGIC;
+ sdr_data_req_w : out STD_LOGIC;
+ sdr_data_req_r : out STD_LOGIC;
+ part_clk_p : out STD_LOGIC;
+ part_clk_n : out STD_LOGIC;
+ part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
+ part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+ part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0);
+ part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0);
+ part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0);
+ part_cs_n : out STD_LOGIC;
+ part_we_n : out STD_LOGIC;
+ part_cas_n : out STD_LOGIC;
+ part_ras_n : out STD_LOGIC;
+ part_cke : out STD_LOGIC
+ );
+end ddr_phy;
+
+architecture tech of ddr_phy is
+
+ signal dqs_drive : std_logic;
+ signal drive : std_logic;
+ signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0);
+ signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0);
+ signal dqs_rst : std_logic;
+ signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0);
+ signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0);
+ signal part_ctrl_reg : part_ctrl_t;
+ signal we_reg : std_logic;
+ signal read_en : std_logic;
+
+ type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
+ signal u_tag_pipe : u_tag_array_t;
+
+begin
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+utag_pipe:
+ process(sys_rst, sys_clk0)
+ begin
+ if rising_edge(sys_clk0) then
+ for i in u_tag_pipe'length-1 downto 1 loop
+ u_tag_pipe(i) <= u_tag_pipe(i-1);
+ end loop;
+ if phy_ctrl.utag_we = '1' then
+ u_tag_pipe(0) <= u_tag_in;
+ end if;
+ end if;
+ end process;
+
+WE_REGISTER:
+ process(sys_rst, sys_clk0)
+ begin
+ if sys_rst = '1' then
+ we_reg <= '0';
+ elsif rising_edge(sys_clk0) then
+ we_reg <= phy_ctrl.we;
+ end if;
+ end process;
+
+DATA_DRIVE_GEN:
+ process(sys_clk0)
+ begin
+ if falling_edge(sys_clk0) then
+ dqs_rst <= not we_reg;
+ drive <= we_reg;
+ end if;
+ end process;
+
+DQS_DRIVE_GEN:
+ process(sys_clk0)
+ variable p : unsigned(1 downto 0);
+ begin
+ if rising_edge(sys_clk0) then
+ if phy_ctrl.drive_en = '1' then
+ p := (others => '1');
+ else
+ p := p(p'left-1 downto 0) & '0';
+ end if;
+ end if;
+ dqs_drive <= p(p'left);
+ end process;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- SDRAM Clock
+ODDR_clk_p : ODDR
+ generic map
+ (
+ DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
+ )
+ port map (
+ Q => part_clk_p, -- 1-bit DDR output
+ C => sys_clk0, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => '1', -- 1-bit data input (positive edge)
+ D2 => '0', -- 1-bit data input (negative edge)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ODDR_clk_n : ODDR
+ generic map
+ (
+ DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
+ )
+ port map (
+ Q => part_clk_n, -- 1-bit DDR output
+ C => sys_clk0, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => '0', -- 1-bit data input (positive edge)
+ D2 => '1', -- 1-bit data input (negative edge)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- Data OUT DDR-FFs
+gen_ddr_data_out:
+ for n in 0 to DDR_DATA_WIDTH-1 generate
+ begin
+ ODDR_data : ODDR
+ generic map
+ (
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
+ )
+ port map (
+ Q => ddr_data_w(n), -- 1-bit DDR output
+ C => sys_clk270, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge)
+ D2 => sdr_data_w(n), -- 1-bit data input (negative edge)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+ end generate gen_ddr_data_out;
+
+-- Sample tristate on clock90
+ process (sys_clk270)
+ begin
+ if rising_edge(sys_clk270) then
+ for n in 0 to DDR_DATA_WIDTH-1 loop
+ drive270(n) <= drive;
+ end loop;
+ end if;
+ end process;
+
+-- Output mux
+out_mux_data:
+ for n in 0 to DDR_DATA_WIDTH-1 generate
+ part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
+ end generate;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- Data-mask OUT DDR-FFs
+gen_ddr_dm_out:
+ for n in 0 to DDR_DM_WIDTH-1 generate
+ begin
+ ODDR_dm : ODDR
+ generic map
+ (
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
+ )
+ port map (
+ Q => part_dm(n), -- 1-bit DDR output
+ C => sys_clk270, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge)
+ D2 => sdr_dm(n), -- 1-bit data input (negative edge)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+ end generate gen_ddr_dm_out;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+-- DQS OUT DDR-FFs
+gen_dqs_out:
+ for n in 0 to DDR_DQS_WIDTH-1 generate
+ begin
+ ODDR_dqs : ODDR
+ generic map
+ (
+ DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
+ INIT => '0', -- Initial value for Q port ('1' or '0')
+ SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC")
+ )
+ port map (
+ Q => dqs(n), -- 1-bit DDR output
+ C => sys_clk0, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D2 => '0', -- 1-bit data input (positive edge)
+ D1 => '1', -- 1-bit data input (negative edge)
+ R => dqs_rst, -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+ end generate gen_dqs_out;
+
+-- Tristate-Control fuer dqs
+ process (sys_clk0) is
+ variable zctrl : boolean;
+ begin
+ if rising_edge(sys_clk0) then
+ if dqs_drive = '1' then
+ zctrl := false;
+ else
+ zctrl := true;
+ end if;
+ if zctrl then
+ dqs_zen <= (others => '1');
+ else
+ dqs_zen <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+-- Tristate-Buffer fuer dqs
+gen_out_mux_dqs:
+ for n in 0 to DDR_DQS_WIDTH-1 generate
+ part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
+ end generate gen_out_mux_dqs;
+
+------------------------------------------------------------------------------------------------------------------------------------------------
+ process (sys_rst, sys_clk0) is
+ begin
+ if sys_rst = '1' then
+ part_ctrl_reg.cmd <= COMMAND(SD_DESELECT);
+ part_ctrl_reg.ba <= (others=>'0');
+ part_ctrl_reg.addr <= (others=>'0');
+ part_ctrl_reg.cke <= '0';
+ elsif rising_edge(sys_clk0) then
+ part_ctrl_reg <= part_ctrl;
+ end if;
+ end process;
+
+ process (sys_clk0) is
+ begin
+ if falling_edge(sys_clk0) then
+ part_ras_n <= part_ctrl_reg.cmd.ras_n;
+ part_cas_n <= part_ctrl_reg.cmd.cas_n;
+ part_we_n <= part_ctrl_reg.cmd.we_n;
+ part_cs_n <= part_ctrl_reg.cmd.cs_n;
+ part_ba <= part_ctrl_reg.ba;
+ part_addr <= part_ctrl_reg.addr;
+ part_cke <= part_ctrl_reg.cke;
+ end if;
+ end process;
+
+-----------------------------------------------------------------
+-- READ DATA Processing
+-----------------------------------------------------------------
+gen_ddr_data_in:
+ for n in 0 to DDR_DATA_WIDTH-1 generate
+ begin
+ IDDR_data : IDDR
+ generic map
+ (
+ DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+ INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
+ INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
+ SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC"
+ )
+ port map
+ (
+ Q1 => data_r(n), -- 1-bit output for positive edge of clock
+ Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock
+ C => read_clk, -- 1-bit clock input
+ CE => read_en, -- 1-bit clock enable input
+ D => part_data(n), -- 1-bit DDR data input
+ R => '0', -- 1-bit reset
+ S => '0' -- 1-bit set
+ );
+ end generate;
+
+
+data_sample_stage:
+ process (sys_clk0)
+ begin
+ if falling_edge(sys_clk0) then
+ data_reg_r <= data_r;
+ end if;
+ end process;
+
+misc_flags_and_data_out:
+ process (sys_rst, sys_clk0)
+ variable p : unsigned(3 downto 0);
+ begin
+ if sys_rst = '1' then
+ p := (others => '0');
+ read_en <= '0';
+ sdr_data_vld <= '0';
+ sdr_data_req_w <= '0';
+ sdr_data_req_r <= '0';
+ elsif rising_edge(sys_clk0) then
+ sdr_data_r <= data_reg_r;
+ if p(3) = '1' then
+ u_tag_rd <= u_tag_pipe(4);
+ end if;
+ if phy_ctrl.we = '1' then
+ u_tag_wr <= u_tag_pipe(0);
+ end if;
+ sdr_data_req_w <= phy_ctrl.we;
+ sdr_data_req_r <= phy_ctrl.re;
+ sdr_data_vld <= p(3);
+ read_en <= p(1);
+ if phy_ctrl.re = '1' then
+ p := p(p'left-1 downto 0) & '1';
+ else
+ p := p(p'left-1 downto 0) & '0';
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+end tech;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd
new file mode 100644
index 0000000..79ce51f
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd
@@ -0,0 +1,111 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.fifo_ctrl_pkg.all;
+
+entity fifo_sync is
+ Generic (
+ addr_width : natural := 4;
+ data_width : natural := 8;
+ almost_full_thresh : integer := 12;
+ almost_empty_thresh : integer := 4
+ );
+ Port
+ (
+ rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ we : in STD_LOGIC;
+ re : in STD_LOGIC;
+ fifo_full : out STD_LOGIC;
+ fifo_empty : out STD_LOGIC;
+ fifo_afull : out STD_LOGIC;
+ fifo_aempty : out STD_LOGIC;
+ data_w : in unsigned (data_width-1 downto 0);
+ data_r : out unsigned (data_width-1 downto 0)
+ );
+end fifo_sync;
+
+architecture Behavioral of fifo_sync is
+
+ signal mem_we : STD_LOGIC;
+ signal ptr_w : unsigned (addr_width-1 downto 0);
+ signal ptr_r : unsigned (addr_width-1 downto 0);
+ signal full : STD_LOGIC;
+ signal empty : STD_LOGIC;
+ signal almost_full : STD_LOGIC;
+ signal almost_empty : STD_LOGIC;
+
+begin
+
+ mem_we <= we;
+ fifo_full <= full;
+ fifo_empty <= empty;
+ fifo_afull <= almost_full;
+ fifo_aempty <= almost_empty;
+
+ inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+ GENERIC MAP
+ (
+ addr_width => addr_width,
+ almost_full_thresh => almost_full_thresh,
+ almost_empty_thresh => almost_empty_thresh
+ )
+ PORT MAP
+ (
+ rst => rst,
+ clk => clk,
+ we => we,
+ re => re,
+ ptr_w => ptr_w,
+ ptr_r => ptr_r,
+ fifo_full => full,
+ fifo_empty => empty,
+ fifo_afull => almost_full,
+ fifo_aempty => almost_empty
+
+ );
+
+ inst_dpram_1w1r: entity work.dpram_1w1r_dist
+ GENERIC MAP (
+ addr_width => addr_width,
+ data_width => data_width
+ )
+ PORT MAP(
+ clka => clk,
+ clkb => clk,
+ en_a => '1',
+ en_b => '1',
+ we_a => mem_we,
+ addr_a => ptr_w,
+ addr_b => ptr_r,
+ din_a => data_w,
+ dout_b => data_r
+ );
+
+end Behavioral;
+
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd
new file mode 100644
index 0000000..356bb28
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd
@@ -0,0 +1,1320 @@
+-----------------------------------------------------------------------------------------
+--
+-- File Name: MT46V16M16.VHD
+-- Version: 2.1
+-- Date: January 14th, 2002
+-- Model: Behavioral
+-- Simulator: NCDesktop - http://www.cadence.com
+-- ModelSim PE - http://www.model.com
+--
+-- Dependencies: None
+--
+-- Author: Son P. Huynh
+-- Email: sphuynh@micron.com
+-- Phone: (208) 368-3825
+-- Company: Micron Technology, Inc.
+-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
+--
+-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
+--
+-- Limitation: Doesn't model internal refresh counter
+--
+-- Note:
+--
+-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
+-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
+-- All rights researved
+--
+-- Rev Author Date Changes
+-- --- ---------------------------- ---------- -------------------------------------
+-- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter
+-- Micron Technology, Inc.
+--
+-- 2.0 Son P. Huynh 11/08/2001 - Second release
+-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE
+--
+-----------------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+ USE IEEE.STD_LOGIC_1164.ALL;
+ USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+ USE IEEE.STD_LOGIC_ARITH.ALL;
+
+ENTITY MT46V16M16 IS
+ GENERIC ( -- Timing for -75Z CL2
+ tCK : TIME := 7.500 ns;
+ tCH : TIME := 3.375 ns; -- 0.45*tCK
+ tCL : TIME := 3.375 ns; -- 0.45*tCK
+ tDH : TIME := 0.500 ns;
+ tDS : TIME := 0.500 ns;
+ tIH : TIME := 0.900 ns;
+ tIS : TIME := 0.900 ns;
+ tMRD : TIME := 15.000 ns;
+ tRAS : TIME := 40.000 ns;
+ tRAP : TIME := 20.000 ns;
+ tRC : TIME := 65.000 ns;
+ tRFC : TIME := 75.000 ns;
+ tRCD : TIME := 20.000 ns;
+ tRP : TIME := 20.000 ns;
+ tRRD : TIME := 15.000 ns;
+ tWR : TIME := 15.000 ns;
+ addr_bits : INTEGER := 13;
+ data_bits : INTEGER := 16;
+ cols_bits : INTEGER := 9
+ );
+ PORT (
+ Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+ Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+ Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+ Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ Clk : IN STD_LOGIC;
+ Clk_n : IN STD_LOGIC;
+ Cke : IN STD_LOGIC;
+ Cs_n : IN STD_LOGIC;
+ Ras_n : IN STD_LOGIC;
+ Cas_n : IN STD_LOGIC;
+ We_n : IN STD_LOGIC;
+ Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+ );
+END MT46V16M16;
+
+ARCHITECTURE behave OF MT46V16M16 IS
+ -- Array for Read pipeline
+ TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+ TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+ TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+ -- Array for Write pipeline
+ TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
+ TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+ TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+ -- Array for Auto Precharge
+ TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+ TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+ TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
+
+ -- Array for Manual Precharge
+ TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+ TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+ TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+
+ -- Array for Burst Terminate
+ TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+
+ -- Array for Memory Access
+ TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+ TYPE Array_ram_pntr IS ACCESS Array_ram_type;
+ TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
+
+ -- Data pair
+ SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
+ SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+ -- Mode Register
+ SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+
+ -- Command Decode Variables
+ SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
+ SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
+
+ -- Burst Length Decode Variables
+ SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
+
+ -- Cas Latency Decode Variables
+ SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
+
+ -- Internal Control Signals
+ SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
+
+ -- System Clock
+ SIGNAL Sys_clk : STD_LOGIC := '0';
+
+ -- Dqs buffer
+ SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+
+BEGIN
+ -- Strip the strength
+ Cs_in <= To_X01 (Cs_n);
+ Ras_in <= To_X01 (Ras_n);
+ Cas_in <= To_X01 (Cas_n);
+ We_in <= To_X01 (We_n);
+
+ -- Commands Decode
+ Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
+ Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
+ Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
+ Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1));
+ Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
+ Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
+ Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
+ Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
+
+ -- Burst Length Decode
+ Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
+ Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
+ Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
+ Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
+
+ -- CAS Latency Decode
+ Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4));
+ Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
+ Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
+ Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
+ Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
+
+ -- Dqs buffer
+ Dqs <= Dqs_out;
+
+ --
+ -- System Clock
+ --
+ int_clk : PROCESS (Clk, Clk_n)
+ VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
+ begin
+ IF Clk = '1' AND Clk_n = '0' THEN
+ ClkZ := '1';
+ CkeZ := Cke;
+ ELSIF Clk = '0' AND Clk_n = '1' THEN
+ ClkZ := '0';
+ END IF;
+ Sys_clk <= CkeZ AND ClkZ;
+ END PROCESS;
+
+ --
+ -- Main Process
+ --
+ state_register : PROCESS
+ -- Precharge Variables
+ VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
+
+ -- Activate Variables
+ VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
+
+ -- Data IO variables
+ VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
+
+ -- Internal address mux variables
+ VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+ VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+ VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+ VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+ VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+ VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+ VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+ VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+
+ -- DLL Reset variables
+ VARIABLE DLL_enable : STD_LOGIC := '0';
+ VARIABLE DLL_reset : STD_LOGIC := '0';
+ VARIABLE DLL_done : STD_LOGIC := '0';
+ VARIABLE DLL_count : INTEGER := 0;
+
+ -- Timing Check
+ VARIABLE MRD_chk : TIME := 0 ns;
+ VARIABLE RFC_chk : TIME := 0 ns;
+ VARIABLE RRD_chk : TIME := 0 ns;
+ VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
+ VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
+ VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
+ VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
+ VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
+ VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
+
+ -- Read pipeline variables
+ VARIABLE Read_cmnd : Array_Read_cmnd;
+ VARIABLE Read_bank : Array_Read_bank;
+ VARIABLE Read_cols : Array_Read_cols;
+
+ -- Write pipeline variables
+ VARIABLE Write_cmnd : Array_Write_cmnd;
+ VARIABLE Write_bank : Array_Write_bank;
+ VARIABLE Write_cols : Array_Write_cols;
+
+ -- Auto Precharge variables
+ VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0');
+ VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
+ VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 );
+
+ -- Manual Precharge variables
+ VARIABLE A10_precharge : Array_A10_precharge;
+ VARIABLE Bank_precharge : Array_Bank_precharge;
+ VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
+
+ -- Burst Terminate variable
+ VARIABLE Cmnd_bst : Array_Cmnd_bst;
+
+ -- Memory Banks
+ VARIABLE Bank0 : Array_ram_stor;
+ VARIABLE Bank1 : Array_ram_stor;
+ VARIABLE Bank2 : Array_ram_stor;
+ VARIABLE Bank3 : Array_ram_stor;
+
+ -- Burst Counter
+ VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+ -- Internal Dqs initialize
+ VARIABLE Dqs_int : STD_LOGIC := '0';
+
+ -- Data buffer for DM Mask
+ VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+
+ --
+ -- Initialize empty rows
+ --
+ PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
+ VARIABLE i, j : INTEGER := 0;
+ BEGIN
+ IF Bank = "00" THEN
+ IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
+ Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access
+ FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
+ FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+ Bank0 (Row_index) (i) (j) := '0';
+ END LOOP;
+ END LOOP;
+ END IF;
+ ELSIF Bank = "01" THEN
+ IF Bank1 (Row_index) = NULL THEN
+ Bank1 (Row_index) := NEW Array_ram_type;
+ FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+ FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+ Bank1 (Row_index) (i) (j) := '0';
+ END LOOP;
+ END LOOP;
+ END IF;
+ ELSIF Bank = "10" THEN
+ IF Bank2 (Row_index) = NULL THEN
+ Bank2 (Row_index) := NEW Array_ram_type;
+ FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+ FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+ Bank2 (Row_index) (i) (j) := '0';
+ END LOOP;
+ END LOOP;
+ END IF;
+ ELSIF Bank = "11" THEN
+ IF Bank3 (Row_index) = NULL THEN
+ Bank3 (Row_index) := NEW Array_ram_type;
+ FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+ FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+ Bank3 (Row_index) (i) (j) := '0';
+ END LOOP;
+ END LOOP;
+ END IF;
+ END IF;
+ END;
+
+ --
+ -- Burst Counter
+ --
+ PROCEDURE Burst_decode IS
+ VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
+ BEGIN
+ -- Advance burst counter
+ Burst_counter := Burst_counter + 1;
+
+ -- Burst Type
+ IF Mode_reg (3) = '0' THEN
+ Cols_temp := Cols_addr + 1;
+ ELSIF Mode_reg (3) = '1' THEN
+ Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
+ Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
+ Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
+ END IF;
+
+ -- Burst Length
+ IF Burst_length_2 = '1' THEN
+ Cols_addr (0) := Cols_temp (0);
+ ELSIF Burst_length_4 = '1' THEN
+ Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
+ ELSIF Burst_length_8 = '1' THEN
+ Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
+ ELSE
+ Cols_addr := Cols_temp;
+ END IF;
+
+ -- Data counter
+ IF Burst_length_2 = '1' THEN
+ IF Burst_counter >= 2 THEN
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ ELSIF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+ ELSIF Burst_length_4 = '1' THEN
+ IF Burst_counter >= 4 THEN
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ ELSIF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+ ELSIF Burst_length_8 = '1' THEN
+ IF Burst_counter >= 8 THEN
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ ELSIF Data_out_enable = '1' THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+ END IF;
+ END;
+
+ BEGIN
+ WAIT ON Sys_clk;
+
+ --
+ -- Manual Precharge Pipeline
+ --
+ IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+ -- A10 Precharge Pipeline
+ A10_precharge(0) := A10_precharge(1);
+ A10_precharge(1) := A10_precharge(2);
+ A10_precharge(2) := A10_precharge(3);
+ A10_precharge(3) := A10_precharge(4);
+ A10_precharge(4) := A10_precharge(5);
+ A10_precharge(5) := A10_precharge(6);
+ A10_precharge(6) := A10_precharge(7);
+ A10_precharge(7) := A10_precharge(8);
+ A10_precharge(8) := '0';
+
+ -- Bank Precharge Pipeline
+ Bank_precharge(0) := Bank_precharge(1);
+ Bank_precharge(1) := Bank_precharge(2);
+ Bank_precharge(2) := Bank_precharge(3);
+ Bank_precharge(3) := Bank_precharge(4);
+ Bank_precharge(4) := Bank_precharge(5);
+ Bank_precharge(5) := Bank_precharge(6);
+ Bank_precharge(6) := Bank_precharge(7);
+ Bank_precharge(7) := Bank_precharge(8);
+ Bank_precharge(8) := "00";
+
+ -- Command Precharge Pipeline
+ Cmnd_precharge(0) := Cmnd_precharge(1);
+ Cmnd_precharge(1) := Cmnd_precharge(2);
+ Cmnd_precharge(2) := Cmnd_precharge(3);
+ Cmnd_precharge(3) := Cmnd_precharge(4);
+ Cmnd_precharge(4) := Cmnd_precharge(5);
+ Cmnd_precharge(5) := Cmnd_precharge(6);
+ Cmnd_precharge(6) := Cmnd_precharge(7);
+ Cmnd_precharge(7) := Cmnd_precharge(8);
+ Cmnd_precharge(8) := '0';
+
+ -- Terminate Read if same bank or all banks
+ IF ((Cmnd_precharge (0) = '1') AND
+ (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
+ (Data_out_enable = '1')) THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+
+ --
+ -- Burst Terminate Pipeline
+ --
+ IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+ -- Burst Terminate pipeline
+ Cmnd_bst (0) := Cmnd_bst (1);
+ Cmnd_bst (1) := Cmnd_bst (2);
+ Cmnd_bst (2) := Cmnd_bst (3);
+ Cmnd_bst (3) := Cmnd_bst (4);
+ Cmnd_bst (4) := Cmnd_bst (5);
+ Cmnd_bst (5) := Cmnd_bst (6);
+ Cmnd_bst (6) := Cmnd_bst (7);
+ Cmnd_bst (7) := Cmnd_bst (8);
+ Cmnd_bst (8) := '0';
+
+ -- Terminate current Read
+ IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN
+ Data_out_enable := '0';
+ END IF;
+ END IF;
+
+ --
+ -- Dq and Dqs Drivers
+ --
+ IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+ -- Read Command Pipeline
+ Read_cmnd (0) := Read_cmnd (1);
+ Read_cmnd (1) := Read_cmnd (2);
+ Read_cmnd (2) := Read_cmnd (3);
+ Read_cmnd (3) := Read_cmnd (4);
+ Read_cmnd (4) := Read_cmnd (5);
+ Read_cmnd (5) := Read_cmnd (6);
+ Read_cmnd (6) := Read_cmnd (7);
+ Read_cmnd (7) := Read_cmnd (8);
+ Read_cmnd (8) := '0';
+
+ -- Read Bank Pipeline
+ Read_bank (0) := Read_bank (1);
+ Read_bank (1) := Read_bank (2);
+ Read_bank (2) := Read_bank (3);
+ Read_bank (3) := Read_bank (4);
+ Read_bank (4) := Read_bank (5);
+ Read_bank (5) := Read_bank (6);
+ Read_bank (6) := Read_bank (7);
+ Read_bank (7) := Read_bank (8);
+ Read_bank (8) := "00";
+
+ -- Read Column Pipeline
+ Read_cols (0) := Read_cols (1);
+ Read_cols (1) := Read_cols (2);
+ Read_cols (2) := Read_cols (3);
+ Read_cols (3) := Read_cols (4);
+ Read_cols (4) := Read_cols (5);
+ Read_cols (5) := Read_cols (6);
+ Read_cols (6) := Read_cols (7);
+ Read_cols (7) := Read_cols (8);
+ Read_cols (8) := (OTHERS => '0');
+
+ -- Initialize Read command
+ IF Read_cmnd (0) = '1' THEN
+ Data_out_enable := '1';
+ Bank_addr := Read_bank (0);
+ Cols_addr := Read_cols (0);
+ Cols_brst := Cols_addr (2 DOWNTO 0);
+ Burst_counter := (OTHERS => '0');
+
+ -- Row address mux
+ CASE Bank_addr IS
+ WHEN "00" => Rows_addr := B0_row_addr;
+ WHEN "01" => Rows_addr := B1_row_addr;
+ WHEN "10" => Rows_addr := B2_row_addr;
+ WHEN OTHERS => Rows_addr := B3_row_addr;
+ END CASE;
+ END IF;
+
+ -- Toggle Dqs during Read command
+ IF Data_out_enable = '1' THEN
+ Dqs_int := '0';
+ IF Dqs_out = "00" THEN
+ Dqs_out <= "11";
+ ELSIF Dqs_out = "11" THEN
+ Dqs_out <= "00";
+ ELSE
+ Dqs_out <= "00";
+ END IF;
+ ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
+ Dqs_out <= "ZZ";
+ END IF;
+
+ -- Initialize Dqs for Read command
+ IF Read_cmnd (2) = '1' THEN
+ IF Data_out_enable = '0' THEN
+ Dqs_int := '1';
+ Dqs_out <= "00";
+ END IF;
+ END IF;
+
+ -- Read Latch
+ IF Data_out_enable = '1' THEN
+ -- Initialize Memory
+ Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
+
+ -- Output Data
+ CASE Bank_addr IS
+ WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ END CASE;
+
+ -- Increase Burst Counter
+ Burst_decode;
+ ELSE
+ Dq <= (OTHERS => 'Z');
+ END IF;
+ END IF;
+
+ --
+ -- Write FIFO and DM Mask Logic
+ --
+ IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+ -- Write command pipeline
+ Write_cmnd (0) := Write_cmnd (1);
+ Write_cmnd (1) := Write_cmnd (2);
+ Write_cmnd (2) := '0';
+
+ -- Write command pipeline
+ Write_bank (0) := Write_bank (1);
+ Write_bank (1) := Write_bank (2);
+ Write_bank (2) := "00";
+
+ -- Write column pipeline
+ Write_cols (0) := Write_cols (1);
+ Write_cols (1) := Write_cols (2);
+ Write_cols (2) := (OTHERS => '0');
+
+ -- Initialize Write command
+ IF Write_cmnd (0) = '1' THEN
+ Data_in_enable := '1';
+ Bank_addr := Write_bank (0);
+ Cols_addr := Write_cols (0);
+ Cols_brst := Cols_addr (2 DOWNTO 0);
+ Burst_counter := (OTHERS => '0');
+
+ -- Row address mux
+ CASE Bank_addr IS
+ WHEN "00" => Rows_addr := B0_row_addr;
+ WHEN "01" => Rows_addr := B1_row_addr;
+ WHEN "10" => Rows_addr := B2_row_addr;
+ WHEN OTHERS => Rows_addr := B3_row_addr;
+ END CASE;
+ END IF;
+
+ -- Write data
+ IF Data_in_enable = '1' THEN
+ -- Initialize memory
+ Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
+
+ -- Write first data
+ IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
+ -- Data Buffer
+ CASE Bank_addr IS
+ WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ END CASE;
+
+ -- Perform DM Mask
+ IF Dm_pair (0) = '0' THEN
+ Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
+ END IF;
+ IF Dm_pair (1) = '0' THEN
+ Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
+ END IF;
+
+ -- Write Data
+ CASE Bank_addr IS
+ WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+ WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+ WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+ WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+ END CASE;
+ END IF;
+
+ -- Increase Burst Counter
+ Burst_decode;
+
+ -- Write second data
+ IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
+ -- Data Buffer
+ CASE Bank_addr IS
+ WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+ END CASE;
+
+ -- Perform DM Mask
+ IF Dm_pair (2) = '0' THEN
+ Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
+ END IF;
+ IF Dm_pair (3) = '0' THEN
+ Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
+ END IF;
+
+ -- Write Data
+ CASE Bank_addr IS
+ WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+ WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+ WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+ WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+ END CASE;
+ END IF;
+
+ -- Increase Burst Counter
+ Burst_decode;
+
+ -- tWR start and tWTR check
+ IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
+ CASE Bank_addr IS
+ WHEN "00" => WR_chk0 := NOW;
+ WHEN "01" => WR_chk1 := NOW;
+ WHEN "10" => WR_chk2 := NOW;
+ WHEN OTHERS => WR_chk3 := NOW;
+ END CASE;
+
+ -- tWTR check
+ ASSERT (Read_enable = '0')
+ REPORT "tWTR violation during Read"
+ SEVERITY WARNING;
+ END IF;
+ END IF;
+ END IF;
+
+ --
+ -- Auto Precharge Calculation
+ --
+ IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+ -- Precharge counter
+ IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
+ Count_precharge (0) := Count_precharge (0) + 1;
+ END IF;
+ IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
+ Count_precharge (1) := Count_precharge (1) + 1;
+ END IF;
+ IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
+ Count_precharge (2) := Count_precharge (2) + 1;
+ END IF;
+ IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
+ Count_precharge (3) := Count_precharge (3) + 1;
+ END IF;
+
+ -- Read with AutoPrecharge Calculation
+ -- The device start internal precharge when:
+ -- 1. Meet tRAS requirement
+ -- 2. BL/2 cycles after command
+ IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
+ IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR
+ (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR
+ (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
+ Pc_b0 := '1';
+ Act_b0 := '0';
+ RP_chk0 := NOW;
+ Read_precharge(0) := '0';
+ END IF;
+ END IF;
+ IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
+ IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR
+ (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR
+ (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
+ Pc_b1 := '1';
+ Act_b1 := '0';
+ RP_chk1 := NOW;
+ Read_precharge(1) := '0';
+ END IF;
+ END IF;
+ IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
+ IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR
+ (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR
+ (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
+ Pc_b2 := '1';
+ Act_b2 := '0';
+ RP_chk2 := NOW;
+ Read_precharge(2) := '0';
+ END IF;
+ END IF;
+ IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
+ IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR
+ (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR
+ (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
+ Pc_b3 := '1';
+ Act_b3 := '0';
+ RP_chk3 := NOW;
+ Read_precharge(3) := '0';
+ END IF;
+ END IF;
+
+ -- Write with AutoPrecharge Calculation
+ -- The device start internal precharge when:
+ -- 1. Meet tRAS requirement
+ -- 2. Two clock after last burst
+ -- Since tWR is time base, the model will compensate tRP
+ IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
+ IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
+ (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
+ (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
+ Pc_b0 := '1';
+ Act_b0 := '0';
+ RP_chk0 := NOW - ((2 * tCK) - tWR);
+ Write_precharge(0) := '0';
+ END IF;
+ END IF;
+ IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
+ IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
+ (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
+ (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
+ Pc_b1 := '1';
+ Act_b1 := '0';
+ RP_chk1 := NOW - ((2 * tCK) - tWR);
+ Write_precharge(1) := '0';
+ END IF;
+ END IF;
+ IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
+ IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
+ (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
+ (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
+ Pc_b2 := '1';
+ Act_b2 := '0';
+ RP_chk2 := NOW - ((2 * tCK) - tWR);
+ Write_precharge(2) := '0';
+ END IF;
+ END IF;
+ IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
+ IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
+ (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
+ (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
+ Pc_b3 := '1';
+ Act_b3 := '0';
+ RP_chk3 := NOW - ((2 * tCK) - tWR);
+ Write_precharge(3) := '0';
+ END IF;
+ END IF;
+ END IF;
+
+ --
+ -- DLL Counter
+ --
+ IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+ IF (DLL_Reset = '1' AND DLL_done = '0') THEN
+ DLL_count := DLL_count + 1;
+ IF (DLL_count >= 200) THEN
+ DLL_done := '1';
+ END IF;
+ END IF;
+ END IF;
+
+ --
+ -- Control Logic
+ --
+ IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+ -- Auto Refresh
+ IF Aref_enable = '1' THEN
+ -- Auto Refresh to Auto Refresh
+ ASSERT (NOW - RFC_chk >= tRFC)
+ REPORT "tRFC violation during Auto Refresh"
+ SEVERITY WARNING;
+
+ -- Precharge to Auto Refresh
+ ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+ (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+ REPORT "tRP violation during Auto Refresh"
+ SEVERITY WARNING;
+
+ -- Precharge to Auto Refresh
+ ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+ REPORT "All banks must be Precharge before Auto Refresh"
+ SEVERITY WARNING;
+
+ -- Record current tRFC time
+ RFC_chk := NOW;
+ END IF;
+
+ -- Extended Load Mode Register
+ IF Ext_mode_enable = '1' THEN
+ IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
+ IF (Addr (0) = '0') THEN
+ DLL_enable := '1';
+ ELSE
+ DLL_enable := '0';
+ END IF;
+ END IF;
+
+ -- Precharge to EMR
+ ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+ REPORT "All bank must be Precharged before Extended Mode Register"
+ SEVERITY WARNING;
+
+ -- Precharge to EMR
+ ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+ (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+ REPORT "tRP violation during Extended Load Register"
+ SEVERITY WARNING;
+
+ -- LMR/EMR to EMR
+ ASSERT (NOW - MRD_chk >= tMRD)
+ REPORT "tMRD violation during Extended Mode Register"
+ SEVERITY WARNING;
+
+ -- Record current tMRD time
+ MRD_chk := NOW;
+ END IF;
+
+ -- Load Mode Register
+ IF Mode_reg_enable = '1' THEN
+ -- Register mode
+ Mode_reg <= Addr;
+
+ -- DLL Reset
+ IF (DLL_enable = '1' AND Addr (8) = '1') THEN
+ DLL_reset := '1';
+ DLL_done := '0';
+ DLL_count := 0;
+ ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
+ ASSERT (FALSE)
+ REPORT "DLL is ENABLE: DLL RESET is require"
+ SEVERITY WARNING;
+ ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
+ ASSERT (FALSE)
+ REPORT "DLL is DISABLE: DLL RESET will be ignored"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Precharge to LMR
+ ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+ REPORT "All bank must be Precharged before Load Mode Register"
+ SEVERITY WARNING;
+
+ -- Precharge to EMR
+ ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+ (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+ REPORT "tRP violation during Load Mode Register"
+ SEVERITY WARNING;
+
+ -- LMR/ELMR to LMR
+ ASSERT (NOW - MRD_chk >= tMRD)
+ REPORT "tMRD violation during Load Mode Register"
+ SEVERITY WARNING;
+
+ -- Check for invalid Burst Length
+ ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2
+ (Addr (2 DOWNTO 0) = "010") OR -- BL = 4
+ (Addr (2 DOWNTO 0) = "011")) -- BL = 8
+ REPORT "Invalid Burst Length during Load Mode Register"
+ SEVERITY WARNING;
+
+ -- Check for invalid CAS Latency
+ ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0
+ (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5
+ REPORT "Invalid CAS Latency during Load Mode Register"
+ SEVERITY WARNING;
+
+ -- Record current tMRD time
+ MRD_chk := NOW;
+ END IF;
+
+ -- Active Block (latch Bank and Row Address)
+ IF Active_enable = '1' THEN
+ -- Activate an OPEN bank can corrupt data
+ ASSERT ((Ba = "00" AND Act_b0 = '0') OR
+ (Ba = "01" AND Act_b1 = '0') OR
+ (Ba = "10" AND Act_b2 = '0') OR
+ (Ba = "11" AND Act_b3 = '0'))
+ REPORT "Bank is already activated - data can be corrupted"
+ SEVERITY WARNING;
+
+ -- Activate Bank 0
+ IF Ba = "00" AND Pc_b0 = '1' THEN
+ -- Activate to Activate (same bank)
+ ASSERT (NOW - RC_chk0 >= tRC)
+ REPORT "tRC violation during Activate Bank 0"
+ SEVERITY WARNING;
+
+ -- Precharge to Active
+ ASSERT (NOW - RP_chk0 >= tRP)
+ REPORT "tRP violation during Activate Bank 0"
+ SEVERITY WARNING;
+
+ -- Record Variables for checking violation
+ Act_b0 := '1';
+ Pc_b0 := '0';
+ B0_row_addr := Addr;
+ RC_chk0 := NOW;
+ RCD_chk0 := NOW;
+ RAS_chk0 := NOW;
+ RAP_chk0 := NOW;
+ END IF;
+
+ -- Activate Bank 1
+ IF Ba = "01" AND Pc_b1 = '1' THEN
+ -- Activate to Activate (same bank)
+ ASSERT (NOW - RC_chk1 >= tRC)
+ REPORT "tRC violation during Activate Bank 1"
+ SEVERITY WARNING;
+
+ -- Precharge to Active
+ ASSERT (NOW - RP_chk1 >= tRP)
+ REPORT "tRP violation during Activate Bank 1"
+ SEVERITY WARNING;
+
+ -- Record Variables for checking violation
+ Act_b1 := '1';
+ Pc_b1 := '0';
+ B1_row_addr := Addr;
+ RC_chk1 := NOW;
+ RCD_chk1 := NOW;
+ RAS_chk1 := NOW;
+ RAP_chk1 := NOW;
+ END IF;
+
+ -- Activate Bank 2
+ IF Ba = "10" AND Pc_b2 = '1' THEN
+ -- Activate to Activate (same bank)
+ ASSERT (NOW - RC_chk2 >= tRC)
+ REPORT "tRC violation during Activate Bank 2"
+ SEVERITY WARNING;
+
+ -- Precharge to Active
+ ASSERT (NOW - RP_chk2 >= tRP)
+ REPORT "tRP violation during Activate Bank 2"
+ SEVERITY WARNING;
+
+ -- Record Variables for checking violation
+ Act_b2 := '1';
+ Pc_b2 := '0';
+ B2_row_addr := Addr;
+ RC_chk2 := NOW;
+ RCD_chk2 := NOW;
+ RAS_chk2 := NOW;
+ RAP_chk2 := NOW;
+ END IF;
+
+ -- Activate Bank 3
+ IF Ba = "11" AND Pc_b3 = '1' THEN
+ -- Activate to Activate (same bank)
+ ASSERT (NOW - RC_chk3 >= tRC)
+ REPORT "tRC violation during Activate Bank 3"
+ SEVERITY WARNING;
+
+ -- Precharge to Active
+ ASSERT (NOW - RP_chk3 >= tRP)
+ REPORT "tRP violation during Activate Bank 3"
+ SEVERITY WARNING;
+
+ -- Record Variables for checking violation
+ Act_b3 := '1';
+ Pc_b3 := '0';
+ B3_row_addr := Addr;
+ RC_chk3 := NOW;
+ RCD_chk3 := NOW;
+ RAS_chk3 := NOW;
+ RAP_chk3 := NOW;
+ END IF;
+
+ -- Activate Bank A to Activate Bank B
+ IF (Prev_bank /= Ba) THEN
+ ASSERT (NOW - RRD_chk >= tRRD)
+ REPORT "tRRD violation during Activate"
+ SEVERITY WARNING;
+ END IF;
+
+ -- AutoRefresh to Activate
+ ASSERT (NOW - RFC_chk >= tRFC)
+ REPORT "tRFC violation during Activate"
+ SEVERITY WARNING;
+
+ -- Record Variables for Checking Violation
+ RRD_chk := NOW;
+ Prev_bank := Ba;
+ END IF;
+
+ -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
+ IF Prech_enable = '1' THEN
+ -- EMR or LMR to Precharge
+ ASSERT (NOW - MRD_chk >= tMRD)
+ REPORT "tMRD violation during Precharge"
+ SEVERITY WARNING;
+
+ -- Precharge Bank 0
+ IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
+ Act_b0 := '0';
+ Pc_b0 := '1';
+ RP_chk0 := NOW;
+
+ -- Activate to Precharge bank 0
+ ASSERT (NOW - RAS_chk0 >= tRAS)
+ REPORT "tRAS violation during Precharge"
+ SEVERITY WARNING;
+
+ -- tWR violation check for Write
+ ASSERT (NOW - WR_chk0 >= tWR)
+ REPORT "tWR violation during Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Precharge Bank 1
+ IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
+ Act_b1 := '0';
+ Pc_b1 := '1';
+ RP_chk1 := NOW;
+
+ -- Activate to Precharge
+ ASSERT (NOW - RAS_chk1 >= tRAS)
+ REPORT "tRAS violation during Precharge"
+ SEVERITY WARNING;
+
+ -- tWR violation check for Write
+ ASSERT (NOW - WR_chk1 >= tWR)
+ REPORT "tWR violation during Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Precharge Bank 2
+ IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
+ Act_b2 := '0';
+ Pc_b2 := '1';
+ RP_chk2 := NOW;
+
+ -- Activate to Precharge
+ ASSERT (NOW - RAS_chk2 >= tRAS)
+ REPORT "tRAS violation during Precharge"
+ SEVERITY WARNING;
+
+ -- tWR violation check for Write
+ ASSERT (NOW - WR_chk2 >= tWR)
+ REPORT "tWR violation during Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Precharge Bank 3
+ IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
+ Act_b3 := '0';
+ Pc_b3 := '1';
+ RP_chk3 := NOW;
+
+ -- Activate to Precharge
+ ASSERT (NOW - RAS_chk3 >= tRAS)
+ REPORT "tRAS violation during Precharge"
+ SEVERITY WARNING;
+
+ -- tWR violation check for Write
+ ASSERT (NOW - WR_chk3 >= tWR)
+ REPORT "tWR violation during Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Pipeline for READ
+ IF CAS_latency_15 = '1' THEN
+ A10_precharge (3) := Addr(10);
+ Bank_precharge (3) := Ba;
+ Cmnd_precharge (3) := '1';
+ ELSIF CAS_latency_2 = '1' THEN
+ A10_precharge (4) := Addr(10);
+ Bank_precharge (4) := Ba;
+ Cmnd_precharge (4) := '1';
+ ELSIF CAS_latency_25 = '1' THEN
+ A10_precharge (5) := Addr(10);
+ Bank_precharge (5) := Ba;
+ Cmnd_precharge (5) := '1';
+ ELSIF CAS_latency_3 = '1' THEN
+ A10_precharge (6) := Addr(10);
+ Bank_precharge (6) := Ba;
+ Cmnd_precharge (6) := '1';
+ ELSIF CAS_latency_4 = '1' THEN
+ A10_precharge (8) := Addr(10);
+ Bank_precharge (8) := Ba;
+ Cmnd_precharge (8) := '1';
+ END IF;
+ END IF;
+
+ -- Burst Terminate
+ IF Burst_term = '1' THEN
+ -- Pipeline for Read
+ IF CAS_latency_15 = '1' THEN
+ Cmnd_bst (3) := '1';
+ ELSIF CAS_latency_2 = '1' THEN
+ Cmnd_bst (4) := '1';
+ ELSIF CAS_latency_25 = '1' THEN
+ Cmnd_bst (5) := '1';
+ ELSIF CAS_latency_3 = '1' THEN
+ Cmnd_bst (6) := '1';
+ ELSIF CAS_latency_4 = '1' THEN
+ Cmnd_bst (8) := '1';
+ END IF;
+
+ -- Terminate Write
+ ASSERT (Data_in_enable = '0')
+ REPORT "It's illegal to Burst Terminate a Write"
+ SEVERITY WARNING;
+
+ -- Terminate Read with Auto Precharge
+ ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
+ Read_precharge (2) = '0' AND Read_precharge (3) = '0')
+ REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Read Command
+ IF Read_enable = '1' THEN
+ -- CAS Latency Pipeline
+ IF Cas_latency_15 = '1' THEN
+ Read_cmnd (3) := '1';
+ Read_bank (3) := Ba;
+ Read_cols (3) := Addr (8 DOWNTO 0);
+ ELSIF Cas_latency_2 = '1' THEN
+ Read_cmnd (4) := '1';
+ Read_bank (4) := Ba;
+ Read_cols (4) := Addr (8 DOWNTO 0);
+ ELSIF Cas_latency_25 = '1' THEN
+ Read_cmnd (5) := '1';
+ Read_bank (5) := Ba;
+ Read_cols (5) := Addr (8 DOWNTO 0);
+ ELSIF Cas_latency_3 = '1' THEN
+ Read_cmnd (6) := '1';
+ Read_bank (6) := Ba;
+ Read_cols (6) := Addr (8 DOWNTO 0);
+ ELSIF Cas_latency_4 = '1' THEN
+ Read_cmnd (8) := '1';
+ Read_bank (8) := Ba;
+ Read_cols (8) := Addr (8 DOWNTO 0);
+ END IF;
+
+ -- Write to Read: Terminate Write Immediately
+ IF Data_in_enable = '1' THEN
+ Data_in_enable := '0';
+ END IF;
+
+ -- Interrupting a Read with Auto Precharge (same bank only)
+ ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
+ REPORT "It's illegal to interrupt a Read with Auto Precharge"
+ SEVERITY WARNING;
+
+ -- Activate to Read
+ ASSERT ((Ba = "00" AND Act_b0 = '1') OR
+ (Ba = "01" AND Act_b1 = '1') OR
+ (Ba = "10" AND Act_b2 = '1') OR
+ (Ba = "11" AND Act_b3 = '1'))
+ REPORT "Bank is not Activated for Read"
+ SEVERITY WARNING;
+
+ -- Activate to Read without Auto Precharge
+ IF Addr (10) = '0' THEN
+ ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+ (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+ (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+ (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+ REPORT "tRCD violation during Read"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Activate to Read with Auto Precharge
+ IF Addr (10) = '1' THEN
+ ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
+ (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
+ (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
+ (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
+ REPORT "tRAP violation during Read"
+ SEVERITY WARNING;
+ END IF;
+
+ -- Auto precharge
+ IF Addr (10) = '1' THEN
+ Read_precharge (Conv_INTEGER(Ba)) := '1';
+ Count_precharge (Conv_INTEGER(Ba)) := 0;
+ END IF;
+
+ -- DLL Check
+ IF (DLL_reset = '1') THEN
+ ASSERT (DLL_done = '1')
+ REPORT "DLL RESET not complete"
+ SEVERITY WARNING;
+ END IF;
+ END IF;
+
+ -- Write Command
+ IF Write_enable = '1' THEN
+ -- Pipeline for Write
+ Write_cmnd (2) := '1';
+ Write_bank (2) := Ba;
+ Write_cols (2) := Addr (8 DOWNTO 0);
+
+ -- Interrupting a Write with Auto Precharge (same bank only)
+ ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
+ REPORT "It's illegal to interrupt a Write with Auto Precharge"
+ SEVERITY WARNING;
+
+ -- Activate to Write
+ ASSERT ((Ba = "00" AND Act_b0 = '1') OR
+ (Ba = "01" AND Act_b1 = '1') OR
+ (Ba = "10" AND Act_b2 = '1') OR
+ (Ba = "11" AND Act_b3 = '1'))
+ REPORT "Bank is not Activated for Write"
+ SEVERITY WARNING;
+
+ -- Activate to Write
+ ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+ (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+ (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+ (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+ REPORT "tRCD violation during Write"
+ SEVERITY WARNING;
+
+ -- Auto precharge
+ IF Addr (10) = '1' THEN
+ Write_precharge (Conv_INTEGER(Ba)) := '1';
+ Count_precharge (Conv_INTEGER(Ba)) := 0;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ --
+ -- Dqs Receiver
+ --
+ dqs_rcvrs : PROCESS
+ VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+ BEGIN
+ WAIT ON Dqs;
+ -- Latch data at posedge Dqs
+ IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
+ Dq_temp := Dq;
+ Dm_temp := Dm;
+ END IF;
+ -- Latch data at negedge Dqs
+ IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
+ Dq_pair <= (Dq & Dq_temp);
+ Dm_pair <= (Dm & Dm_temp);
+ END IF;
+ END PROCESS;
+
+ --
+ -- Setup timing checks
+ --
+ Setup_check : PROCESS
+ BEGIN
+ WAIT ON Sys_clk;
+ IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+ ASSERT(Cke'LAST_EVENT >= tIS)
+ REPORT "CKE Setup time violation -- tIS"
+ SEVERITY WARNING;
+ ASSERT(Cs_n'LAST_EVENT >= tIS)
+ REPORT "CS# Setup time violation -- tIS"
+ SEVERITY WARNING;
+ ASSERT(Cas_n'LAST_EVENT >= tIS)
+ REPORT "CAS# Setup time violation -- tIS"
+ SEVERITY WARNING;
+ ASSERT(Ras_n'LAST_EVENT >= tIS)
+ REPORT "RAS# Setup time violation -- tIS"
+ SEVERITY WARNING;
+ ASSERT(We_n'LAST_EVENT >= tIS)
+ REPORT "WE# Setup time violation -- tIS"
+ SEVERITY WARNING;
+ ASSERT(Addr'LAST_EVENT >= tIS)
+ REPORT "ADDR Setup time violation -- tIS"
+ SEVERITY WARNING;
+ ASSERT(Ba'LAST_EVENT >= tIS)
+ REPORT "BA Setup time violation -- tIS"
+ SEVERITY WARNING;
+ END IF;
+ END PROCESS;
+
+ --
+ -- Hold timing checks
+ --
+ Hold_check : PROCESS
+ BEGIN
+ WAIT ON Sys_clk'DELAYED (tIH);
+ IF Sys_clk'DELAYED (tIH) = '1' THEN
+ ASSERT(Cke'LAST_EVENT >= tIH)
+ REPORT "CKE Hold time violation -- tIH"
+ SEVERITY WARNING;
+ ASSERT(Cs_n'LAST_EVENT >= tIH)
+ REPORT "CS# Hold time violation -- tIH"
+ SEVERITY WARNING;
+ ASSERT(Cas_n'LAST_EVENT >= tIH)
+ REPORT "CAS# Hold time violation -- tIH"
+ SEVERITY WARNING;
+ ASSERT(Ras_n'LAST_EVENT >= tIH)
+ REPORT "RAS# Hold time violation -- tIH"
+ SEVERITY WARNING;
+ ASSERT(We_n'LAST_EVENT >= tIH)
+ REPORT "WE# Hold time violation -- tIH"
+ SEVERITY WARNING;
+ ASSERT(Addr'LAST_EVENT >= tIH)
+ REPORT "ADDR Hold time violation -- tIH"
+ SEVERITY WARNING;
+ ASSERT(Ba'LAST_EVENT >= tIH)
+ REPORT "BA Hold time violation -- tIH"
+ SEVERITY WARNING;
+ END IF;
+ END PROCESS;
+
+END behave;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd
new file mode 100644
index 0000000..4f799c5
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd
@@ -0,0 +1,111 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Reset generator (Virtex-4 specific)
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity reset is
+ port
+ (
+ clk : in std_logic;
+ rst_in : in std_logic;
+ rst_out : out std_logic
+ );
+end;
+
+architecture tech of reset is
+
+ signal rst : std_logic;
+ signal shift_pipe : std_logic_vector(3 downto 0);
+ attribute KEEP : string;
+ attribute KEEP of shift_pipe : signal is "TRUE";
+
+begin
+
+ rst <= shift_pipe(0);
+
+bufg_reset: bufg
+ port map
+ (
+ o => rst_out,
+ i => rst
+ );
+
+fdp0: fdp
+ generic map
+ (
+ init => '1'
+ )
+ port map
+ (
+ d => rst_in,
+ c => clk,
+ pre => '0',
+ q => shift_pipe(3)
+ );
+
+fdp1: fdp
+ generic map
+ (
+ init => '1'
+ )
+ port map
+ (
+
+ d => shift_pipe(3),
+ c => clk,
+ pre => '0',
+ q => shift_pipe(2)
+ );
+
+fdp2: fdp
+ generic map
+ (
+ init => '1'
+ )
+ port map
+ (
+ d => shift_pipe(2),
+ c => clk,
+ pre => '0',
+ q => shift_pipe(1)
+ );
+
+fdp3: fdp
+ generic map
+ (
+ init => '1'
+ )
+ port map
+ (
+
+ d => shift_pipe(1),
+ c => clk,
+ pre => '0',
+ q => shift_pipe(0)
+ );
+
+end tech;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd
new file mode 100644
index 0000000..a50b6e8
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd
@@ -0,0 +1,269 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: SDRAM command controller
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_cmd is
+ Generic (BL : natural := 2);
+ Port (
+ rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ enable : in STD_LOGIC;
+ u_tag_in : in user_tag_t;
+ u_tag_out : out user_tag_t;
+ phy_ctrl : out phy_ctrl_t;
+ cmd : in sdr_cmd_t;
+ cmd_we : in STD_LOGIC;
+ cmd_ack : out STD_LOGIC;
+ col_addr : in col_addr_t;
+ mode_word : in mode_word_t;
+ sdr_cmd_ctrl : out sdr_cmd_lines_t;
+ sdr_addr : out sdr_addr_t;
+ sdr_ba : out sdr_ba_t
+ );
+end sdram_cmd;
+
+architecture behaviour of sdram_cmd is
+
+ signal st_sdr, st_sdr_next : sdr_state_t;
+
+ signal cc_preset : natural range 0 to 10;
+ signal cc_load_en : std_logic;
+ signal cycle_finished : std_logic;
+
+ signal burst_preset : natural range 0 to 3;
+ signal burst_load_en : std_logic;
+ signal burst_finished : std_logic;
+
+begin
+
+ u_tag_out <= u_tag_in;
+
+------------------------------------------------------------------------------------------
+
+fsm_sdr_state:
+ process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
+ begin
+ st_sdr_next <= st_sdr;
+ sdr_cmd_ctrl <= COMMAND(SD_NOP);
+
+ cc_load_en <= '0';
+ cc_preset <= TIMING(cmd);
+ burst_load_en <= '0';
+ cmd_ack <= '0';
+ burst_preset <= BL/2-1;
+ phy_ctrl.re <= '0';
+ phy_ctrl.drive_en <= '0';
+ phy_ctrl.we <= '0';
+ phy_ctrl.utag_we <= '0';
+ sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
+ sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1);
+
+ case st_sdr is
+ when PWR_DOWN =>
+ sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
+ if enable = '1' then
+ st_sdr_next <= IDLE;
+ end if;
+
+ when PRECHARGE =>
+ if cycle_finished = '1' then
+ st_sdr_next <= IDLE;
+ end if;
+
+ when MODE =>
+ if cycle_finished = '1' then
+ st_sdr_next <= IDLE;
+ end if;
+
+ when IDLE =>
+ if cmd_we = '1' then
+ cmd_ack <= '1';
+ cc_load_en <= '1';
+ cc_preset <= TIMING(cmd);
+ sdr_cmd_ctrl <= COMMAND(cmd);
+ case cmd is
+ when SD_PRE =>
+ st_sdr_next <= PRECHARGE;
+ sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL);
+ when SD_LMR =>
+ st_sdr_next <= MODE;
+ when SD_ACT =>
+ st_sdr_next <= ROW_ACT;
+ when SD_AR =>
+ st_sdr_next <= AUTO_REF;
+ when others => null;
+ end case;
+ end if;
+
+ when ROW_ACT =>
+ if cycle_finished = '1' then
+ if cmd_we = '1' then
+ cmd_ack <= '1';
+ burst_load_en <= '1';
+ cc_load_en <= '1';
+ cc_preset <= TIMING(cmd);
+ sdr_cmd_ctrl <= COMMAND(cmd);
+ case cmd is
+ when SD_PRE =>
+ st_sdr_next <= PRECHARGE;
+ when SD_READ =>
+ phy_ctrl.utag_we <= '1';
+ st_sdr_next <= READ;
+ sdr_addr(col_addr_t'range) <= col_addr;
+ when SD_WRITE =>
+ phy_ctrl.utag_we <= '1';
+ phy_ctrl.drive_en <= '1';
+ st_sdr_next <= WRITE;
+ sdr_addr(col_addr_t'range) <= col_addr;
+ when others => null;
+ end case;
+ end if;
+ end if;
+
+ when WRITE =>
+ phy_ctrl.drive_en <= '1';
+ phy_ctrl.we <= '1';
+ if burst_finished = '1' then
+ if cmd_we = '1' and cmd = SD_WRITE then
+ sdr_addr(col_addr_t'range) <= col_addr;
+ cmd_ack <= '1';
+ burst_load_en <= '1';
+ sdr_cmd_ctrl <= COMMAND(cmd);
+ phy_ctrl.utag_we <= '1';
+ else
+ phy_ctrl.drive_en <= '0';
+ cc_load_en <= '1';
+ cc_preset <= TIMING(SD_WRITE)+1;
+ st_sdr_next <= ROW_ACT;
+ end if;
+ end if;
+
+ when READ =>
+ phy_ctrl.re <= '1';
+ if burst_finished = '1' then
+ if cmd_we = '1' and cmd = SD_READ then
+ sdr_addr(col_addr_t'range) <= col_addr;
+ cmd_ack <= '1';
+ burst_load_en <= '1';
+ sdr_cmd_ctrl <= COMMAND(cmd);
+ phy_ctrl.utag_we <= '1';
+ else
+ cc_load_en <= '1';
+ cc_preset <= TIMING(SD_READ);
+ st_sdr_next <= ROW_ACT;
+ end if;
+ end if;
+
+ when WRITE_A => -- not implemented yet
+ cmd_ack <= '1';
+ st_sdr_next <= IDLE;
+
+ when READ_A => -- not implemented yet
+ cmd_ack <= '1';
+ st_sdr_next <= IDLE;
+
+ when BURST_STOP => -- not implemented yet
+ cmd_ack <= '1';
+ st_sdr_next <= IDLE;
+
+ when SELF_REF => -- not implemented yet
+ cmd_ack <= '1';
+ st_sdr_next <= IDLE;
+
+ when PRE_PWR_DOWN => -- not implemented yet
+ cmd_ack <= '1';
+ st_sdr_next <= IDLE;
+
+ when ACT_PWR_DOWN => -- not implemented yet
+ cmd_ack <= '1';
+ st_sdr_next <= IDLE;
+
+ when AUTO_REF =>
+ if cycle_finished = '1' then
+ st_sdr_next <= IDLE;
+ end if;
+
+ when others =>
+ st_sdr_next <= IDLE;
+ end case;
+
+ end process;
+
+fsm_sdr_state_next:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ st_sdr <= PWR_DOWN;
+ elsif rising_edge(clk) then
+ st_sdr <= st_sdr_next;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+cycle_counter:
+ process (rst, clk)
+ variable cycle_cnt : natural range 0 to 10;
+ begin
+ if rst = '1' then
+ cycle_cnt := 0;
+ cycle_finished <= '0';
+ elsif rising_edge(clk) then
+ cycle_finished <= '0';
+ if cc_load_en = '1' then
+ cycle_cnt := cc_preset;
+ elsif cycle_cnt /= 0 then
+ cycle_cnt := cycle_cnt - 1;
+ else
+ cycle_finished <= '1';
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+burst_counter:
+ process (rst, clk)
+ variable burst_cnt : natural range 0 to 3;
+ begin
+ if rst = '1' then
+ burst_cnt := 0;
+ elsif rising_edge(clk) then
+ burst_finished <= '0';
+ if burst_load_en = '1' then
+ burst_cnt := burst_preset;
+ elsif burst_cnt /= 0 then
+ burst_cnt := burst_cnt - 1;
+ end if;
+ if burst_cnt = 0 then
+ burst_finished <= '1';
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+end behaviour;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd
new file mode 100644
index 0000000..b62e085
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd
@@ -0,0 +1,74 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: User SDRAM component adjustments
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package sdram_config is
+
+ constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width
+ constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
+ constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
+ constant DDR_ROW_ADDR_WIDTH : positive := 13; --
+ constant DDR_COL_ADDR_WIDTH : positive := 9; --
+
+ constant LMR_REG_BASE : natural := 0;
+ constant LMR_REG_EXTENDED : natural := 1;
+ constant LMR_OP_NORMAL : natural := 0;
+ constant LMR_OP_RES_DLL : natural := 2;
+ constant LMR_BT_SEQ : natural := 0;
+ constant LMR_BT_ILVD : natural := 1;
+ constant LMR_BL2 : natural := 1;
+ constant LMR_BL4 : natural := 2;
+ constant LMR_BL8 : natural := 3;
+ constant LMR_CL2 : natural := 2;
+ constant LMR_CL3 : natural := 3;
+ constant LMR_CL2_5 : natural := 6;
+
+ -- DDR SDRAM Hardware defined constants
+ constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
+ constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
+ constant ENABLE_PRE_ALL : std_logic := '1';
+ constant ENABLE_AUTO_PRE : std_logic := '0';
+
+ -- DDR-SDR TIMING constants ------------------------------------------------------------------
+ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
+ constant REFRESH_INTERVAL : real := 7.8125; -- us
+
+ -- These values are for your SDRAM part (see datasheet)
+ constant TCAS : positive := 2; -- CAS latency [clocks]
+ constant TRP : positive := 2; -- precharge command period
+ constant TRAS : positive := 4; -- active to precharge delay
+ constant TRFC : positive := 8; -- auto refresh command period
+ constant TMRD : positive := 2; -- load mode register command cylce time
+ constant TRCD : positive := 2; -- active to read or write delay !
+ constant TWR : positive := 2; -- write recovery time
+
+ constant PWR_UP_WAIT : natural := 1; -- µs
+
+ subtype user_tag_t is unsigned(3 downto 0);
+
+ ----------------------------------------------------------------------------------------------
+
+end sdram_config;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd
new file mode 100644
index 0000000..dbb5b80
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd
@@ -0,0 +1,487 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: SDRAM main controller and user I/F
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.utils_pkg.all;
+
+entity sdram_ctrl is
+ Generic
+ (
+ f_sysclk : natural := 100E6;
+ BL : natural := 2
+ );
+ Port (
+ rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ u_busy : out STD_LOGIC;
+ u_tag_in : in user_tag_t;
+ u_tag_out : out user_tag_t;
+ u_addr : in user_addr_t;
+ u_cmd : in user_cmd_t;
+ u_cmd_we : in STD_LOGIC;
+ col_addr : out col_addr_t;
+ sdr_cmd_busy : in STD_LOGIC;
+ sdr_cmd : out sdr_cmd_t;
+ sdr_cmd_we : out STD_LOGIC;
+ sdr_mode : out mode_word_t;
+ sdr_cke : out STD_LOGIC
+ );
+end sdram_ctrl;
+
+architecture behaviour of sdram_ctrl is
+
+ constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL);
+
+ type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH);
+ signal st_ctrl, st_ctrl_next : ctrl_state_t;
+
+ constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
+ signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
+ signal pwr_up_cnt_rst : std_logic;
+ signal pwr_up_finished : std_logic;
+
+ signal cycle_cnt : natural range 0 to 255;
+ signal cc_preset : natural range 0 to 255;
+ signal cc_load_en : std_logic;
+ signal cycle_finished : std_logic;
+
+ signal seq_cnt : natural range 0 to 31;
+ signal seq_rst_en : std_logic;
+ signal seq_cnt_en : std_logic;
+
+ constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
+ signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
+ signal refresh_request : std_logic;
+ signal refresh_cnt_rst : std_logic;
+
+ signal addr_reg_load_en : std_logic;
+
+ signal u_tag_reg : user_tag_t;
+ signal bank_addr_reg : bank_addr_t;
+ signal row_addr_reg : row_addr_t;
+ signal col_addr_reg : col_addr_t;
+
+ signal u_bank_addr : bank_addr_t;
+ signal u_row_addr : row_addr_t;
+ signal u_col_addr : col_addr_t;
+
+ signal act_request : std_logic;
+ signal act_request_set : std_logic;
+ signal act_request_clr : std_logic;
+
+ type init_seq_rom_t is array (0 to 14) of init_seq_t;
+
+ constant init_seq_rom : init_seq_rom_t :=
+ (
+ (
+ cmd => SD_NOP,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_PRE,
+ mode_word => "000010000000000",
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_NOP,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_LMR,
+ mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_NOP,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_LMR,
+ mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
+ wait_cycle => 200
+ ),
+ (
+ cmd => SD_NOP,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_PRE,
+ mode_word => "000010000000000",
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_NOP,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_AR,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_NOP,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_AR,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_NOP,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ ),
+ (
+ cmd => SD_LMR,
+ mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
+ wait_cycle => 200
+ ),
+ (
+ cmd => SD_NOP,
+ mode_word => (others => '0'),
+ wait_cycle => 0
+ )
+
+ );
+
+begin
+
+ u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
+ u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
+ u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
+
+------------------------------------------------------------------------------------------
+fsm_ctrl_state:
+ process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request)
+ begin
+
+ u_busy <= '1';
+ pwr_up_cnt_rst <= '0';
+ cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
+ cc_load_en <= '0';
+ sdr_cmd <= init_seq_rom(seq_cnt).cmd;
+ sdr_cmd_we <= '0';
+ sdr_mode <= bank_addr_reg & row_addr_reg;
+ col_addr <= col_addr_reg;
+ sdr_cke <= '1';
+ seq_cnt_en <= '0';
+ seq_rst_en <= '0';
+ addr_reg_load_en <= '0';
+ refresh_cnt_rst <= '0';
+ act_request_set <= '0';
+ act_request_clr <= '0';
+ u_tag_out <= u_tag_reg;
+
+ st_ctrl_next <= st_ctrl;
+ case st_ctrl is
+ when RESET =>
+ sdr_cke <= '0';
+ pwr_up_cnt_rst <= '1';
+ st_ctrl_next <= POWER_WAIT;
+
+ when POWER_WAIT =>
+ sdr_cke <= '0';
+ if pwr_up_finished = '1' then
+ seq_rst_en <= '1';
+ st_ctrl_next <= INIT;
+ end if;
+
+ when INIT =>
+ sdr_mode <= init_seq_rom(seq_cnt).mode_word;
+ sdr_cmd <= init_seq_rom(seq_cnt).cmd;
+ cc_preset <= init_seq_rom(seq_cnt).wait_cycle;
+ if seq_cnt = init_seq_rom_t'high then
+ act_request_set <= '1';
+ refresh_cnt_rst <= '1';
+ st_ctrl_next <= USER_READY;
+ elsif sdr_cmd_busy = '0' then
+ cc_load_en <= '1';
+ sdr_cmd_we <= '1';
+ st_ctrl_next <= INIT_WAIT;
+ end if;
+
+ when INIT_WAIT =>
+ if sdr_cmd_busy = '0' and cycle_finished = '1' then
+ seq_cnt_en <= '1';
+ st_ctrl_next <= INIT;
+ end if;
+
+ when USER_READY =>
+ if sdr_cmd_busy = '0' then
+ if refresh_request = '1' then
+ sdr_mode(BIT_PRE_ALL) <= '1';
+ sdr_cmd_we <= '1';
+ sdr_cmd <= SD_PRE;
+ st_ctrl_next <= REFRESH;
+ else
+ u_busy <= '0';
+ if u_cmd_we = '1' then
+ case u_cmd is
+ when UCMD_NOP =>
+ sdr_cmd <= SD_NOP;
+ when UCMD_LMR =>
+ sdr_cmd <= SD_NOP;
+ when UCMD_WRITE =>
+ col_addr <= u_col_addr;
+ u_tag_out <= u_tag_in;
+ sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
+ addr_reg_load_en <= '1';
+ act_request_clr <= '1';
+ sdr_cmd <= SD_WRITE;
+ if (u_row_addr /= row_addr_reg) or act_request = '1' then
+ st_ctrl_next <= USER_WRITE_PRE;
+ elsif (u_bank_addr /= bank_addr_reg) then
+ if ENABLE_PRE_ALL = '1' then
+ st_ctrl_next <= USER_WRITE_ACT;
+ else
+ st_ctrl_next <= USER_WRITE_PRE;
+ end if;
+ elsif sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ else
+ st_ctrl_next <= USER_WRITE;
+ end if;
+ when UCMD_READ =>
+ col_addr <= u_col_addr;
+ u_tag_out <= u_tag_in;
+ sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
+ addr_reg_load_en <= '1';
+ act_request_clr <= '1';
+ sdr_cmd <= SD_READ;
+ if (u_row_addr /= row_addr_reg) or act_request = '1' then
+ st_ctrl_next <= USER_READ_PRE;
+ elsif (u_bank_addr /= bank_addr_reg) then
+ if ENABLE_PRE_ALL = '1' then
+ st_ctrl_next <= USER_READ_ACT;
+ else
+ st_ctrl_next <= USER_READ_PRE;
+ end if;
+ elsif sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ else
+ st_ctrl_next <= USER_READ;
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end if;
+
+ when USER_WRITE_PRE =>
+ sdr_cmd <= SD_PRE;
+ sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
+ if sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ st_ctrl_next <= USER_WRITE_ACT;
+ end if;
+
+ when USER_WRITE_ACT =>
+ sdr_cmd <= SD_ACT;
+ if sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ st_ctrl_next <= USER_WRITE;
+ end if;
+
+ when USER_WRITE =>
+ sdr_cmd <= SD_WRITE;
+ sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
+ if sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ st_ctrl_next <= USER_READY;
+ end if;
+
+ when USER_READ_PRE =>
+ sdr_cmd <= SD_PRE;
+ sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
+ if sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ st_ctrl_next <= USER_READ_ACT;
+ end if;
+
+ when USER_READ_ACT =>
+ sdr_cmd <= SD_ACT;
+ if sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ st_ctrl_next <= USER_READ;
+ end if;
+
+ when USER_READ =>
+ sdr_cmd <= SD_READ;
+ sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
+ if sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ st_ctrl_next <= USER_READY;
+ end if;
+
+ when REFRESH =>
+ sdr_cmd <= SD_AR;
+ if sdr_cmd_busy = '0' then
+ sdr_cmd_we <= '1';
+ st_ctrl_next <= USER_READY;
+ refresh_cnt_rst <= '1';
+ act_request_set <= '1';
+ end if;
+
+ when others =>
+ st_ctrl_next <= RESET;
+ end case;
+
+ end process;
+
+fsm_ctrl_state_next:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ st_ctrl <= RESET;
+ elsif rising_edge(clk) then
+ st_ctrl <= st_ctrl_next;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+act_request_register:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ act_request <= '1';
+ elsif rising_edge(clk) then
+ if act_request_set = '1' then
+ act_request <= '1';
+ elsif act_request_clr = '1' then
+ act_request <= '0';
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+user_addr_register:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ bank_addr_reg <= (others => '0');
+ row_addr_reg <= (others => '0');
+ col_addr_reg <= (others => '0');
+ u_tag_reg <= (others => '0');
+ elsif rising_edge(clk) then
+ if addr_reg_load_en = '1' then
+ bank_addr_reg <= u_bank_addr;
+ row_addr_reg <= u_row_addr;
+ col_addr_reg <= u_col_addr;
+ u_tag_reg <= u_tag_in;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+power_up_counter:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ pwr_up_cnt <= 0;
+ pwr_up_finished <= '0';
+ elsif rising_edge(clk) then
+ pwr_up_finished <= '0';
+ if pwr_up_cnt_rst = '1' then
+ pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1;
+ else
+ if pwr_up_cnt /= 0 then
+ pwr_up_cnt <= pwr_up_cnt - 1;
+ else
+ pwr_up_finished <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+------------------------------------------------------------------------------------------
+refresh_counter:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ refresh_cnt <= 0;
+ refresh_request <= '0';
+ elsif rising_edge(clk) then
+ refresh_request <= '0';
+ if refresh_cnt_rst = '1' then
+ refresh_cnt <= REFRESH_CLOCK_INTERVAL-1;
+ else
+ if refresh_cnt /= 0 then
+ refresh_cnt <= refresh_cnt - 1;
+ else
+ refresh_request <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+cycle_counter:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ cycle_cnt <= 0;
+ cycle_finished <= '0';
+ elsif rising_edge(clk) then
+ cycle_finished <= '0';
+ if cc_load_en = '1' then
+ cycle_cnt <= cc_preset;
+ elsif cycle_cnt /= 0 then
+ cycle_cnt <= cycle_cnt - 1;
+ else
+ cycle_finished <= '1';
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+seq_counter:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ seq_cnt <= 0;
+ elsif rising_edge(clk) then
+ if seq_rst_en = '1' then
+ seq_cnt <= 0;
+ elsif seq_cnt_en = '1' then
+ if seq_cnt /= init_seq_rom_t'high then
+ seq_cnt <= seq_cnt + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+end behaviour;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd
new file mode 100644
index 0000000..98dea2a
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd
@@ -0,0 +1,277 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_ctrl_frontend is
+ Generic
+ (
+ BL : natural := 2;
+ f_sysclk : natural := 100E6;
+ read_phaseshift : integer := 0;
+ fifo_depth : integer := 4
+ );
+ Port
+ (
+ sys_rst_in : in STD_LOGIC;
+ sys_clk_in : in STD_LOGIC;
+ sys_rst_out : out STD_LOGIC;
+ sys_clk_out : out STD_LOGIC;
+ sys_clk_fb : in STD_LOGIC;
+
+ -- User interface
+ busy : out STD_LOGIC;
+ en : in STD_LOGIC;
+ r_wn : in STD_LOGIC;
+ be : in unsigned(SDR_DM_WIDTH-1 downto 0);
+ addr : in user_addr_t;
+ din : in unsigned(SDR_DATA_WIDTH-1 downto 0);
+ dout : out unsigned(SDR_DATA_WIDTH-1 downto 0);
+ dout_re : in STD_LOGIC;
+ dout_vld : out STD_LOGIC;
+
+ -- SDRAM signals
+ sd_clk_p : out STD_LOGIC;
+ sd_clk_n : out STD_LOGIC;
+ sd_cke : out STD_LOGIC;
+ sd_cs_n : out STD_LOGIC;
+ sd_cas_n : out STD_LOGIC;
+ sd_ras_n : out STD_LOGIC;
+ sd_we_n : out STD_LOGIC;
+ sd_addr : out sdr_addr_t;
+ sd_ba : out sdr_ba_t;
+ sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
+ sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+ sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
+
+ );
+end sdram_ctrl_frontend;
+
+architecture struct of sdram_ctrl_frontend is
+
+ -- Number of user data words for simulation
+ signal rst_out : std_logic;
+ signal clk_out : std_logic;
+
+ signal u_addr : user_addr_t;
+ signal u_tag_in : user_tag_t;
+ signal u_tag_rd : user_tag_t;
+ signal u_tag_wr : user_tag_t;
+ signal u_cmd : user_cmd_t;
+ signal u_cmd_we : std_logic;
+ signal u_busy : std_logic;
+ signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal u_dm : unsigned(SDR_DM_WIDTH-1 downto 0);
+ signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal u_data_vld : std_logic;
+ signal u_req_wr : std_logic;
+
+ constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
+ signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0);
+ signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0);
+ signal cat_fifo_re : std_logic;
+ signal cat_fifo_we : std_logic;
+ signal cat_fifo_full : std_logic;
+ signal cat_fifo_empty : std_logic;
+-- signal cat_fifo_almost_full : std_logic;
+-- signal cat_fifo_almost_empty : std_logic;
+
+ signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
+ signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
+ signal write_fifo_re : std_logic;
+ signal write_fifo_we : std_logic;
+ signal write_fifo_full : std_logic;
+ signal write_fifo_empty : std_logic;
+-- signal write_fifo_almost_full : std_logic;
+-- signal write_fifo_almost_empty : std_logic;
+
+ signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0);
+ signal read_fifo_re : std_logic;
+ signal read_fifo_we : std_logic;
+ signal read_fifo_full : std_logic;
+ signal read_fifo_empty : std_logic;
+-- signal read_fifo_almost_full : std_logic;
+-- signal read_fifo_almost_empty : std_logic;
+
+ alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+ alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+ alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+ alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
+ alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
+ alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
+ alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH);
+ alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0);
+ alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH);
+ alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0);
+
+begin
+
+ -- Instantiate synchronous FIFO
+ inst_cat_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => fifo_depth,
+ data_width => CAT_FIFO_WIDTH
+ )
+ PORT MAP
+ (
+ rst => rst_out,
+ clk => clk_out,
+ we => cat_fifo_we,
+ re => cat_fifo_re,
+ fifo_full => cat_fifo_full,
+ fifo_empty => cat_fifo_empty,
+ fifo_afull => open,
+ fifo_aempty => open,
+ data_w => cat_fifo_din,
+ data_r => cat_fifo_dout
+ );
+
+ -- Instantiate synchronous FIFO
+ inst_write_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => fifo_depth,
+ data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH
+ )
+ PORT MAP
+ (
+ rst => rst_out,
+ clk => clk_out,
+ we => write_fifo_we,
+ re => write_fifo_re,
+ fifo_full => write_fifo_full,
+ fifo_empty => write_fifo_empty,
+ fifo_afull => open,
+ fifo_aempty => open,
+ data_w => write_fifo_din,
+ data_r => write_fifo_dout
+ );
+
+ -- Instantiate synchronous FIFO
+ inst_read_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => fifo_depth,
+ data_width => 2*DDR_DATA_WIDTH
+ )
+ PORT MAP
+ (
+ rst => rst_out,
+ clk => clk_out,
+ we => read_fifo_we,
+ re => read_fifo_re,
+ fifo_full => read_fifo_full,
+ fifo_empty => read_fifo_empty,
+ fifo_afull => open,
+ fifo_aempty => open,
+ data_w => read_fifo_din,
+ data_r => read_fifo_dout
+ );
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl : entity work.sdram_ctrl_top
+ Generic map
+ (
+ BL => BL,
+ read_phaseshift => read_phaseshift,
+ f_sysclk => f_sysclk
+ )
+ Port map
+ (
+
+ sys_rst_in => sys_rst_in,
+ sys_clk_in => sys_clk_in,
+
+ sys_rst_out => rst_out,
+ sys_clk_out => clk_out,
+ sys_clk_fb => sys_clk_fb,
+
+ -- User interface
+ u_data_vld => u_data_vld,
+ u_data_req_w => u_req_wr,
+ u_data_req_r => open,
+ u_tag_in => u_tag_in,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ u_busy => u_busy,
+ u_addr => u_addr,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_data_wr => u_data_w,
+ u_data_rd => u_data_r,
+ u_dm => u_dm,
+
+ -- SDRAM signals
+ sd_clk_p => sd_clk_p,
+ sd_clk_n => sd_clk_n,
+ sd_cke => sd_cke,
+ sd_cs_n => sd_cs_n,
+ sd_cas_n => sd_cas_n,
+ sd_ras_n => sd_ras_n,
+ sd_we_n => sd_we_n,
+ sd_addr => sd_addr,
+ sd_ba => sd_ba,
+ sd_dm => sd_dm,
+ sd_dqs => sd_dqs,
+ sd_data => sd_data
+
+ );
+
+------------------------------------------------------------------------------------------
+ sys_rst_out <= rst_out;
+ sys_clk_out <= clk_out;
+
+ busy <= cat_fifo_full or write_fifo_full or read_fifo_full;
+ write_fifo_we <= en and not r_wn and not write_fifo_full and not cat_fifo_full and not read_fifo_full;
+ write_fifo_data_in <= din;
+ write_fifo_dm_in <= not be;
+ cat_fifo_we <= en and not cat_fifo_full and not write_fifo_full and not read_fifo_full;
+ cmd_fifo_in <= UCMD_WRITE when r_wn = '0' else UCMD_READ;
+ addr_fifo_in <= addr;
+ tag_fifo_in <= (others=>'0');
+ dout <= read_fifo_dout;
+ dout_vld <= not read_fifo_empty;
+
+ u_cmd_we <= (not cat_fifo_empty) and (not u_busy);
+ u_cmd <= cmd_fifo_out;
+ u_addr <= addr_fifo_out;
+ u_dm <= write_fifo_dm_out;
+ u_tag_in <= tag_fifo_out;
+
+ write_fifo_re <= u_req_wr and (not write_fifo_empty);
+ cat_fifo_re <= u_cmd_we;
+ u_data_w <= write_fifo_data_out;
+ read_fifo_re <= (not read_fifo_empty) and dout_re;
+ read_fifo_we <= u_data_vld;
+ read_fifo_din <= u_data_r;
+
+
+end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd
new file mode 100644
index 0000000..ba9ee71
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd
@@ -0,0 +1,285 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Top-level put all together
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity sdram_ctrl_top is
+ Generic
+ (
+ BL : natural := 2;
+ f_sysclk : natural := 100E6;
+ read_phaseshift : integer := 0
+ );
+ Port
+ (
+ sys_rst_in : in STD_LOGIC;
+ sys_clk_in : in STD_LOGIC;
+ sys_rst_out : out STD_LOGIC;
+ sys_clk_out : out STD_LOGIC;
+ sys_clk_fb : in STD_LOGIC;
+
+ -- User interface
+ u_data_vld : out STD_LOGIC;
+ u_data_req_w : out STD_LOGIC;
+ u_data_req_r : out STD_LOGIC;
+ u_busy : out STD_LOGIC;
+ u_tag_in : in user_tag_t;
+ u_tag_rd : out user_tag_t;
+ u_tag_wr : out user_tag_t;
+ u_addr : in user_addr_t;
+ u_cmd : in user_cmd_t;
+ u_cmd_we : in STD_LOGIC;
+ u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0);
+ u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0);
+ u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0);
+
+ -- SDRAM signals
+ sd_clk_p : out STD_LOGIC;
+ sd_clk_n : out STD_LOGIC;
+ sd_cke : out STD_LOGIC;
+ sd_cs_n : out STD_LOGIC;
+ sd_cas_n : out STD_LOGIC;
+ sd_ras_n : out STD_LOGIC;
+ sd_we_n : out STD_LOGIC;
+ sd_addr : out sdr_addr_t;
+ sd_ba : out sdr_ba_t;
+ sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0);
+ sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0);
+ sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0)
+
+ );
+end sdram_ctrl_top;
+
+architecture rtl of sdram_ctrl_top is
+
+ signal clk0 : std_logic;
+ signal clk270 : std_logic;
+ signal read_clk270 : std_logic;
+
+ signal phy_ctrl : phy_ctrl_t;
+
+ signal u_tag : user_tag_t;
+ signal sd_cmd_in : sdr_cmd_t;
+ signal sd_cmd : sdr_cmd_t;
+ signal sd_cmd_we : std_logic;
+ signal cmd_ctrl : sdr_cmd_lines_t;
+ signal cke : std_logic;
+ signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
+ signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
+
+ -- Clock generator
+
+ signal cg_rst : std_logic;
+ signal cg_read_clk0 : std_logic;
+ signal cg_read_clk270 : std_logic;
+ signal cg_sys_clk0 : std_logic;
+ signal cg_sys_clk270 : std_logic;
+ signal cg_locked : std_logic;
+ signal cg_error : std_logic;
+ signal ctrl_rst : std_logic;
+ signal part_ctrl : part_ctrl_t;
+
+ -- SD command FIFO
+
+ constant CMD_FIFO_ADDR_WIDTH : positive := 2;
+ constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
+ signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
+ signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
+ signal cmd_fifo_re : std_logic;
+ signal cmd_fifo_we : std_logic;
+ signal cmd_fifo_full : std_logic;
+ signal cmd_fifo_empty : std_logic;
+
+ alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
+ alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
+ alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
+ alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
+
+ alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
+ alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
+ alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
+ alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
+
+begin
+
+ ---------------------------------
+ clk0 <= cg_sys_clk0;
+ clk270 <= cg_sys_clk270;
+ read_clk270 <= cg_read_clk270;
+ cg_rst <= not cg_locked;
+
+ ---------------------------------
+ sys_clk_out <= cg_sys_clk0;
+ sys_rst_out <= ctrl_rst;
+
+ ---------------------------------
+ part_ctrl.cmd <= cmd_ctrl;
+ part_ctrl.ba <= ba;
+ part_ctrl.addr <= addr;
+ part_ctrl.cke <= cke;
+
+ ---------------------------------
+ sd_cmd_we <= not cmd_fifo_empty;
+ cmd_fifo_in <= to_unsigned(sd_cmd_in, 4);
+ sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out));
+
+ ---------------------------------
+ inst_reset: entity work.reset
+ port map
+ (
+ clk => clk0,
+ rst_in => cg_rst,
+ rst_out => ctrl_rst
+ );
+
+ inst_clockgen : entity work.clockgen
+ generic map
+ (
+ read_phaseshift => read_phaseshift,
+ frequency_hz => f_sysclk
+ )
+ port map
+ (
+ rst => sys_rst_in,
+ clk_in => sys_clk_in,
+ clk_fb_in => sys_clk_fb,
+ read_clk0_out => cg_read_clk0,
+ read_clk270_out => cg_read_clk270,
+ sys_clk0_out => cg_sys_clk0,
+ sys_clk270_out => cg_sys_clk270,
+ locked_out => cg_locked,
+ error_out => cg_error
+ );
+
+ -- Main controller
+ inst_sdram_ctrl : entity work.sdram_ctrl
+ Generic map
+ (
+ f_sysclk => 100E6,
+ BL => BL
+ )
+ Port map
+ (
+ rst => ctrl_rst,
+ clk => clk0,
+ u_busy => u_busy,
+ u_tag_in => u_tag_in,
+ u_tag_out => tag_fifo_in,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_addr => u_addr,
+ sdr_cmd_busy => cmd_fifo_full,
+ sdr_cmd => sd_cmd_in,
+ sdr_cmd_we => cmd_fifo_we,
+ col_addr => col_fifo_in,
+ sdr_mode => mode_fifo_in,
+ sdr_cke => cke
+ );
+
+ -- Instantiate synchronous FIFO
+ inst_sd_cmd_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => CMD_FIFO_ADDR_WIDTH,
+ data_width => CMD_FIFO_DATA_WIDTH,
+ almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1),
+ almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1)
+ )
+ PORT MAP
+ (
+ rst => ctrl_rst,
+ clk => clk0,
+ we => cmd_fifo_we,
+ re => cmd_fifo_re,
+ fifo_full => cmd_fifo_full,
+ fifo_empty => cmd_fifo_empty,
+ fifo_afull => open,
+ fifo_aempty => open,
+ data_w => cmd_fifo_din,
+ data_r => cmd_fifo_dout
+ );
+
+ -- DDR SDRAM command fsm
+ inst_sdram_cmd : entity work.sdram_cmd
+ Generic map
+ (
+ BL => BL
+ )
+ Port map
+ (
+ rst => ctrl_rst,
+ clk => clk0,
+ u_tag_in => tag_fifo_out,
+ u_tag_out => u_tag,
+ phy_ctrl => phy_ctrl,
+ enable => cke,
+ cmd => sd_cmd,
+ cmd_we => sd_cmd_we,
+ cmd_ack => cmd_fifo_re,
+ sdr_cmd_ctrl => cmd_ctrl,
+ col_addr => col_fifo_out,
+ mode_word => mode_fifo_out,
+ sdr_ba => ba,
+ sdr_addr => addr
+ );
+
+ -- DDR phy
+ inst_ddr_phy : entity work.ddr_phy
+ Port map
+ (
+ sys_rst => ctrl_rst,
+ sys_clk0 => clk0,
+ sys_clk270 => clk270,
+ u_tag_in => u_tag,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ read_clk => read_clk270,
+ phy_ctrl => phy_ctrl,
+ part_ctrl => part_ctrl,
+ sdr_data_req_w => u_data_req_w,
+ sdr_data_req_r => u_data_req_r,
+ sdr_data_w => u_data_wr,
+ sdr_dm => u_dm,
+ sdr_data_r => u_data_rd,
+ sdr_data_vld => u_data_vld,
+ part_clk_p => sd_clk_p,
+ part_clk_n => sd_clk_n,
+ part_addr => sd_addr,
+ part_ba => sd_ba,
+ part_dm => sd_dm,
+ part_dqs => sd_dqs,
+ part_data => sd_data,
+ part_cs_n => sd_cs_n,
+ part_we_n => sd_we_n,
+ part_cas_n => sd_cas_n,
+ part_ras_n => sd_ras_n,
+ part_cke => sd_cke
+ );
+
+end architecture rtl;
+
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd
new file mode 100644
index 0000000..d235d75
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd
@@ -0,0 +1,133 @@
+-------------------------------------------------------------------------
+-- Project: SDRAM controller
+-- This file: Type definitions
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.sdram_config.all;
+
+package sdram_types is
+
+ -----------------------------------------------------------------------------------------
+ -- Table of Timing Parameters as a function of operation
+
+ -- Derived constants from sdram_config
+
+ constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
+ constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
+ constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; --
+ constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; --
+
+ subtype user_cmd_t is unsigned(1 downto 0);
+ constant UCMD_NOP : user_cmd_t := "00";
+ constant UCMD_READ : user_cmd_t := "01";
+ constant UCMD_WRITE : user_cmd_t := "10";
+ constant UCMD_LMR : user_cmd_t := "11";
+
+ subtype sdr_cmd_t is natural range 0 to 9;
+ constant SD_DESELECT : sdr_cmd_t := 0;
+ constant SD_NOP : sdr_cmd_t := 1;
+ constant SD_LMR : sdr_cmd_t := 2;
+ constant SD_ACT : sdr_cmd_t := 3;
+ constant SD_READ : sdr_cmd_t := 4;
+ constant SD_WRITE : sdr_cmd_t := 5;
+ constant SD_PRE : sdr_cmd_t := 6;
+ constant SD_BST : sdr_cmd_t := 7;
+ constant SD_AR : sdr_cmd_t := 8;
+ constant SD_SR : sdr_cmd_t := 9;
+
+ type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
+ subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
+ subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
+ subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
+ subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
+
+ subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
+ subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
+ subtype col_addr_t is unsigned(8 downto 0);
+
+ subtype cycle_cnt_t is natural range 0 to 10;
+
+ type phy_ctrl_t is
+ record
+ drive_en : std_logic;
+ re : std_logic;
+ we : std_logic;
+ utag_we : std_logic;
+ end record phy_ctrl_t;
+
+ type sdr_cmd_lines_t is
+ record
+ cs_n : std_logic;
+ ras_n : std_logic;
+ cas_n : std_logic;
+ we_n : std_logic;
+ end record sdr_cmd_lines_t;
+
+ type part_ctrl_t is
+ record
+ cmd : sdr_cmd_lines_t;
+ ba : unsigned(DDR_BANK_WIDTH-1 downto 0);
+ addr : unsigned(DDR_ADDR_WIDTH-1 downto 0);
+ cke : std_logic;
+ end record part_ctrl_t;
+
+ type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
+ constant COMMAND : part_cmd_array_t :=
+ -- command cs_n ras_qn cas_qn we_qn
+ ( SD_DESELECT => ( '1', '1', '1', '1'),
+ SD_NOP => ( '0', '1', '1', '1'),
+ SD_LMR => ( '0', '0', '0', '0'),
+ SD_ACT => ( '0', '0', '1', '1'),
+ SD_READ => ( '0', '1', '0', '1'),
+ SD_WRITE => ( '0', '1', '0', '0'),
+ SD_PRE => ( '0', '0', '1', '0'),
+ SD_BST => ( '0', '1', '1', '0'),
+ SD_AR => ( '0', '0', '0', '1'),
+ SD_SR => ( '0', '0', '0', '1')
+ );
+
+ type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
+ constant TIMING : part_timing_array_t :=
+ -- command cycle_cnt
+ ( SD_DESELECT => ( 0 ),
+ SD_NOP => ( 0 ),
+ SD_LMR => ( TMRD-1 ),
+ SD_ACT => ( TRCD-1 ),
+ SD_READ => ( TCAS-1 ),
+ SD_WRITE => ( TWR-1 ),
+ SD_PRE => ( TRP-1 ),
+ SD_BST => ( 0 ),
+ SD_AR => ( TRFC-1 ),
+ SD_SR => ( TRFC-1 )
+ );
+
+ type init_seq_t is
+ record
+ cmd : sdr_cmd_t;
+ mode_word : mode_word_t;
+ wait_cycle : natural;
+ end record init_seq_t;
+
+end sdram_types;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd
new file mode 100644
index 0000000..cc18253
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd
@@ -0,0 +1,332 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.utils_pkg.all;
+
+entity tb_sdr_ctrl is
+end;
+
+architecture struct of tb_sdr_ctrl is
+
+ -- Number of user data words for simulation
+ constant CLK_PERIOD : time := 10 ns;
+ constant BURST_LEN : natural := 8;
+
+ signal rst : std_logic := '1';
+ signal clk : std_logic := '0';
+ signal rst_out : std_logic;
+ signal clk_out : std_logic;
+ signal clk_fb : std_logic;
+ signal part_clk_p : std_logic;
+ signal part_clk_n : std_logic;
+ signal part_cke : std_logic;
+ signal part_cs_n : std_logic;
+ signal part_we_n : std_logic;
+ signal part_ras_n : std_logic;
+ signal part_cas_n : std_logic;
+ signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+ signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+ signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+ signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ signal u_addr : user_addr_t := (others => '0');
+ signal u_tag_in : user_tag_t := "0000";
+ signal u_tag_rd : user_tag_t;
+ signal u_tag_wr : user_tag_t;
+ signal u_cmd : user_cmd_t := UCMD_NOP;
+ signal u_cmd_we : std_logic := '0';
+ signal u_busy : std_logic;
+ signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+ signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_data_vld : std_logic;
+ signal u_req_wr : std_logic;
+ signal u_req_rd : std_logic;
+ signal u_read_en : std_logic := '0';
+ signal u_write_en : std_logic := '0';
+ signal u_addr_cnt_en : std_logic := '0';
+ signal u_addr_load : std_logic := '0';
+ signal u_addr_preset : user_addr_t := (others => '0');
+ signal u_addr_end : user_addr_t := (others => '0');
+ signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
+ signal test_phase : test_phase_t := IDLE;
+
+ type u_addr_mode_t is (MONOTONIC, RANDOM);
+ signal u_addr_mode : u_addr_mode_t := MONOTONIC;
+ signal cycle_cnt : natural := 1;
+ signal data_cnt : natural := 0;
+ signal efficiency : real := 0.0;
+
+begin
+
+ clk_fb <= part_clk_p after 1 ns;
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl : entity work.sdram_ctrl_top
+ Generic map
+ (
+ BL => BURST_LEN,
+ read_phaseshift => 0,
+ f_sysclk => 100E6
+ )
+ Port map
+ (
+
+ sys_rst_in => rst,
+ sys_clk_in => clk,
+
+ sys_rst_out => rst_out,
+ sys_clk_out => clk_out,
+ sys_clk_fb => clk_fb,
+
+ -- User interface
+ u_data_vld => u_data_vld,
+ u_data_req_w => u_req_wr,
+ u_data_req_r => u_req_rd,
+ u_tag_in => u_tag_in,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ u_busy => u_busy,
+ u_addr => u_addr,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_data_wr => u_data_w,
+ u_data_rd => u_data_r,
+ u_dm => u_dm,
+
+ -- SDRAM signals
+ sd_clk_p => part_clk_p,
+ sd_clk_n => part_clk_n,
+ sd_cke => part_cke,
+ sd_cs_n => part_cs_n,
+ sd_cas_n => part_cas_n,
+ sd_ras_n => part_ras_n,
+ sd_we_n => part_we_n,
+ sd_addr => part_addr,
+ sd_ba => part_ba,
+ sd_dm => part_dm,
+ sd_dqs => part_dqs,
+ sd_data => part_data
+
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+ i_mt46v16m16_0 : entity work.mt46v16m16
+ port map (
+ dq => std_logic_vector(part_data),
+ dqs => std_logic_vector(part_dqs),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm)
+ );
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+------------------------------------------------------------------------------------------
+
+R_DATA_COMPARE:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_data_vld='1' then
+ if u_read_en = '1' then
+ assert (ref_data = u_data_r) report "Error on read!" severity failure;
+ end if;
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ elsif u_read_en = '0' then
+ last_data := (others => '0');
+ ref_data <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+W_DATA_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_req_wr = '1' then
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ elsif u_write_en = '0' then
+ last_data := (others => '0');
+ u_data_w <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+ADDR_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_addr_load = '1' then
+ u_addr <= u_addr_preset;
+ elsif u_addr_cnt_en = '1' then
+ if u_addr_mode = MONOTONIC then
+ u_addr <= u_addr + BURST_LEN;
+ else
+ if u_addr(u_addr'left) = '1' then
+ if BURST_LEN = 2 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
+ elsif BURST_LEN = 4 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
+ elsif BURST_LEN = 8 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
+ end if;
+ else
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+performance_count:
+ process(clk_out)
+ begin
+ if rising_edge(clk_out) then
+ if u_write_en = '1' or u_read_en = '1' then
+ cycle_cnt <= cycle_cnt + 1;
+ if u_req_wr = '1' or u_req_rd = '1' then
+ data_cnt <= data_cnt + 1;
+ end if;
+ else
+ cycle_cnt <= 1;
+ data_cnt <= 0;
+ end if;
+ end if;
+ end process;
+
+ u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
+
+ efficiency <= real(data_cnt)/real(cycle_cnt);
+ u_cmd_we <= (u_write_en or u_read_en) and (not u_busy);
+ u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
+
+ process
+ begin
+
+ -- Write MAX_WORDS to DDR SDRAM Controller
+ wait for 4*CLK_PERIOD;
+ rst <= '0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ wait for 137*CLK_PERIOD;
+
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ u_addr_preset <= X"000000";
+ u_addr_end <= X"008000"-BURST_LEN;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_cmd <= UCMD_WRITE;
+ u_write_en <= '1';
+ while u_addr /= u_addr_end loop
+ wait until rising_edge(clk_out);
+ end loop;
+ u_write_en <= '0';
+ wait until rising_edge(clk_out) and u_req_wr='0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 1
+ u_addr_preset <= X"400000";
+ u_addr_end <= X"408000"-BURST_LEN;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_cmd <= UCMD_WRITE;
+ u_write_en <= '1';
+ while u_addr /= u_addr_end loop
+ wait until rising_edge(clk_out);
+ end loop;
+ u_write_en <= '0';
+ wait until rising_edge(clk_out) and u_req_wr='0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ u_addr_preset <= X"000000";
+ u_addr_end <= X"008000"-BURST_LEN;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_cmd <= UCMD_READ;
+ u_read_en <= '1';
+ while u_addr /= u_addr_end loop
+ wait until rising_edge(clk_out);
+ end loop;
+ u_read_en <= '0';
+ wait until rising_edge(clk_out) and u_data_vld='0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 1
+ u_addr_preset <= X"400000";
+ u_addr_end <= X"408000"-BURST_LEN;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_cmd <= UCMD_READ;
+ u_read_en <= '1';
+ while u_addr /= u_addr_end loop
+ wait until rising_edge(clk_out);
+ end loop;
+ u_read_en <= '0';
+ wait until rising_edge(clk_out) and u_data_vld='0';
+
+ wait;
+
+ end process;
+
+end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd
new file mode 100644
index 0000000..6a2a9da
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd
@@ -0,0 +1,416 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity tb_sdr_ctrl_fifo is
+end;
+
+architecture struct of tb_sdr_ctrl_fifo is
+
+ -- Number of user data words for simulation
+ constant CLK_PERIOD : time := 10 ns;
+ constant BURST_LEN : natural := 2;
+
+ signal rst : std_logic := '1';
+ signal clk : std_logic := '0';
+ signal rst_out : std_logic;
+ signal clk_out : std_logic;
+ signal clk_fb : std_logic;
+ signal part_clk_p : std_logic;
+ signal part_clk_n : std_logic;
+ signal part_cke : std_logic;
+ signal part_cs_n : std_logic;
+ signal part_we_n : std_logic;
+ signal part_ras_n : std_logic;
+ signal part_cas_n : std_logic;
+ signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+ signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+ signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+ signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ signal u_addr : user_addr_t := (others => '0');
+ signal u_tag_in : user_tag_t := "0000";
+ signal u_tag_rd : user_tag_t;
+ signal u_tag_wr : user_tag_t;
+ signal u_cmd : user_cmd_t := UCMD_NOP;
+ signal u_cmd_we : std_logic := '0';
+ signal u_busy : std_logic;
+ signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+ signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_data_vld : std_logic;
+ signal u_req_wr : std_logic;
+ signal u_req_rd : std_logic;
+ signal u_read_en : std_logic := '0';
+ signal u_write_en : std_logic := '0';
+
+ signal cmd_fifo_din : unsigned(25 downto 0) := (others => '0');
+ signal cmd_fifo_dout : unsigned(25 downto 0) := (others => '0');
+ signal cmd_fifo_re : std_logic := '0';
+ signal cmd_fifo_we : std_logic := '0';
+ signal cmd_fifo_full : std_logic := '0';
+ signal cmd_fifo_empty : std_logic := '0';
+ signal cmd_fifo_almost_full : std_logic := '0';
+ signal cmd_fifo_almost_empty : std_logic := '0';
+
+ signal write_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal write_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal write_fifo_re : std_logic := '0';
+ signal write_fifo_we : std_logic := '0';
+ signal write_fifo_full : std_logic := '0';
+ signal write_fifo_empty : std_logic := '0';
+ signal write_fifo_almost_full : std_logic := '0';
+ signal write_fifo_almost_empty : std_logic := '0';
+
+ signal read_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal read_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal read_fifo_re : std_logic := '0';
+ signal read_fifo_we : std_logic := '0';
+ signal read_fifo_full : std_logic := '0';
+ signal read_fifo_empty : std_logic := '0';
+ signal read_fifo_almost_full : std_logic := '0';
+ signal read_fifo_almost_empty : std_logic := '0';
+
+ signal write_start : std_logic := '1';
+ signal read_start : std_logic := '1';
+
+ alias cmd_fifo_in is cmd_fifo_din(25 downto 24);
+ alias addr_fifo_in is cmd_fifo_din(23 downto 0);
+ alias cmd_fifo_out is cmd_fifo_dout(25 downto 24);
+ alias addr_fifo_out is cmd_fifo_dout(23 downto 0);
+
+begin
+
+ clk_fb <= part_clk_p after 1 ns;
+
+ -- Instantiate synchronous FIFO
+ inst_command_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => 8,
+ data_width => 2+24
+ )
+ PORT MAP
+ (
+ rst => rst_out,
+ clk => clk_out,
+ we => cmd_fifo_we,
+ re => cmd_fifo_re,
+ fifo_full => cmd_fifo_full,
+ fifo_empty => cmd_fifo_empty,
+ fifo_afull => cmd_fifo_almost_full,
+ fifo_aempty => cmd_fifo_almost_empty,
+ data_w => cmd_fifo_din,
+ data_r => cmd_fifo_dout
+ );
+
+ -- Instantiate synchronous FIFO
+ inst_write_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => 8,
+ data_width => 2*DDR_DATA_WIDTH
+ )
+ PORT MAP
+ (
+ rst => rst_out,
+ clk => clk_out,
+ we => write_fifo_we,
+ re => write_fifo_re,
+ fifo_full => write_fifo_full,
+ fifo_empty => write_fifo_empty,
+ fifo_afull => write_fifo_almost_full,
+ fifo_aempty => write_fifo_almost_empty,
+ data_w => write_fifo_din,
+ data_r => write_fifo_dout
+ );
+
+ -- Instantiate synchronous FIFO
+ inst_read_fifo: entity work.fifo_sync
+ GENERIC MAP
+ (
+ addr_width => 8,
+ data_width => 2*DDR_DATA_WIDTH
+ )
+ PORT MAP
+ (
+ rst => rst_out,
+ clk => clk_out,
+ we => read_fifo_we,
+ re => read_fifo_re,
+ fifo_full => read_fifo_full,
+ fifo_empty => read_fifo_empty,
+ fifo_afull => read_fifo_almost_full,
+ fifo_aempty => read_fifo_almost_empty,
+ data_w => read_fifo_din,
+ data_r => read_fifo_dout
+ );
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl : entity work.sdram_ctrl_top
+ Generic map
+ (
+ BL => BURST_LEN,
+ read_phaseshift => 0,
+ f_sysclk => 100E6
+ )
+ Port map
+ (
+
+ sys_rst_in => rst,
+ sys_clk_in => clk,
+
+ sys_rst_out => rst_out,
+ sys_clk_out => clk_out,
+ sys_clk_fb => clk_fb,
+
+ -- User interface
+ u_data_vld => u_data_vld,
+ u_data_req_w => u_req_wr,
+ u_data_req_r => u_req_rd,
+ u_tag_in => u_tag_in,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ u_busy => u_busy,
+ u_addr => u_addr,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_data_wr => u_data_w,
+ u_data_rd => u_data_r,
+ u_dm => u_dm,
+
+ -- SDRAM signals
+ sd_clk_p => part_clk_p,
+ sd_clk_n => part_clk_n,
+ sd_cke => part_cke,
+ sd_cs_n => part_cs_n,
+ sd_cas_n => part_cas_n,
+ sd_ras_n => part_ras_n,
+ sd_we_n => part_we_n,
+ sd_addr => part_addr,
+ sd_ba => part_ba,
+ sd_dm => part_dm,
+ sd_dqs => part_dqs,
+ sd_data => part_data
+
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+ i_mt46v16m16_0 : entity work.mt46v16m16
+ port map (
+ dq => std_logic_vector(part_data),
+ dqs => std_logic_vector(part_dqs),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm)
+ );
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+------------------------------------------------------------------------------------------
+ u_cmd_we <= (not cmd_fifo_empty) and write_start and (not u_busy);
+ u_cmd <= cmd_fifo_out;
+ u_addr <= addr_fifo_out;
+
+ write_fifo_re <= u_req_wr and (not write_fifo_empty);
+ cmd_fifo_re <= u_cmd_we;
+ u_data_w <= write_fifo_dout;
+ read_fifo_re <= (not read_fifo_empty) and read_start;
+ read_fifo_we <= u_data_vld;
+ read_fifo_din <= u_data_r;
+
+ process
+ begin
+
+ -- Write MAX_WORDS to DDR SDRAM Controller
+ wait for 4*CLK_PERIOD;
+ rst <= '0';
+
+ wait for 4*CLK_PERIOD;
+ wait until rising_edge(clk_out) and rst_out='0';
+
+
write_fifo_we <= '1';
+ cmd_fifo_we <= '1';
+ write_fifo_din <= X"01020304";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000000";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"05060708";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000002";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"00001111";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000004";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"22223333";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000006";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"44445555";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000008";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"66667777";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"00000a";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"88889999";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"00000c";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"AAAABBBB";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"00000e";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"CCCCDDDD";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000010";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"EEEEFFFF";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000012";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '0';
+ cmd_fifo_we <= '0';
+
+-- wait until rising_edge(clk_out) and u_busy='0';
+-- write_start <= '1';
+-- wait until rising_edge(clk_out) and write_fifo_empty='1';
+
+ write_fifo_we <= '1';
+ cmd_fifo_we <= '1';
+ write_fifo_din <= X"01234567";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000014";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '0';
+ cmd_fifo_in <= UCMD_READ;
+ addr_fifo_in <= X"000014";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"89ABCDEF";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000016";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"11223344";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000018";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '0';
+ cmd_fifo_in <= UCMD_READ;
+ addr_fifo_in <= X"000010";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"55667788";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"00001a";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"99990000";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"00001c";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '1';
+ write_fifo_din <= X"AAAA5555";
+ cmd_fifo_in <= UCMD_WRITE;
+ addr_fifo_in <= X"000020";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '0';
+ cmd_fifo_in <= UCMD_READ;
+ addr_fifo_in <= X"000000";
+
+ wait until rising_edge(clk_out);
+ cmd_fifo_in <= UCMD_READ;
+ addr_fifo_in <= X"000018";
+
+ wait until rising_edge(clk_out);
+ cmd_fifo_in <= UCMD_READ;
+ addr_fifo_in <= X"00001A";
+
+ wait until rising_edge(clk_out);
+ cmd_fifo_in <= UCMD_READ;
+ addr_fifo_in <= X"00001C";
+
+ wait until rising_edge(clk_out);
+ cmd_fifo_in <= UCMD_READ;
+ addr_fifo_in <= X"000020";
+
+ wait until rising_edge(clk_out);
+ write_fifo_we <= '0';
+ cmd_fifo_we <= '0';
+
+ wait for 40*CLK_PERIOD;
+ read_start <= '1';
+ wait;
+
+ end process;
+
+end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd
new file mode 100644
index 0000000..3ab72bd
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd
@@ -0,0 +1,318 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.utils_pkg.all;
+
+entity tb_sdr_ctrl is
+end;
+
+architecture struct of tb_sdr_ctrl is
+
+ -- Number of user data words for simulation
+ constant CLK_PERIOD : time := 10 ns;
+ constant BURST_LEN : natural := 8;
+
+ signal rst : std_logic := '1';
+ signal clk : std_logic := '0';
+ signal rst_out : std_logic;
+ signal clk_out : std_logic;
+ signal clk_fb : std_logic;
+ signal part_clk_p : std_logic;
+ signal part_clk_n : std_logic;
+ signal part_cke : std_logic;
+ signal part_cs_n : std_logic;
+ signal part_we_n : std_logic;
+ signal part_ras_n : std_logic;
+ signal part_cas_n : std_logic;
+ signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+ signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+ signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+ signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ signal u_addr : user_addr_t := (others => '0');
+ signal lin_addr : user_addr_t := (others => '0');
+ signal rand_gen : unsigned(7 downto 0) := (others => '0');
+ signal u_tag_in : user_tag_t := "0000";
+ signal u_tag_rd : user_tag_t;
+ signal u_tag_wr : user_tag_t;
+ signal u_cmd : user_cmd_t := UCMD_NOP;
+ signal u_cmd_we : std_logic := '0';
+ signal u_busy : std_logic;
+ signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+ signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_data_vld : std_logic;
+ signal u_req_wr : std_logic;
+ signal u_req_rd : std_logic;
+ signal u_read_en : std_logic := '0';
+ signal u_write_en : std_logic := '0';
+ signal rw_null_en : std_logic := '0';
+ signal u_addr_cnt_en : std_logic := '0';
+ signal u_addr_load : std_logic := '0';
+ signal u_addr_preset : user_addr_t := (others => '0');
+ signal u_addr_end : user_addr_t := (others => '0');
+ signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
+ signal test_phase : test_phase_t := IDLE;
+
+ type u_addr_mode_t is (MONOTONIC, RANDOM);
+ signal u_addr_mode : u_addr_mode_t := MONOTONIC;
+ signal cycle_cnt : natural := 1;
+ signal data_cnt : natural := 0;
+ signal efficiency : real := 0.0;
+
+begin
+
+ clk_fb <= part_clk_p after 1 ns;
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl : entity work.sdram_ctrl_top
+ Generic map
+ (
+ BL => BURST_LEN,
+ read_phaseshift => 0,
+ f_sysclk => 100E6
+ )
+ Port map
+ (
+
+ sys_rst_in => rst,
+ sys_clk_in => clk,
+
+ sys_rst_out => rst_out,
+ sys_clk_out => clk_out,
+ sys_clk_fb => clk_fb,
+
+ -- User interface
+ u_data_vld => u_data_vld,
+ u_data_req_w => u_req_wr,
+ u_data_req_r => u_req_rd,
+ u_tag_in => u_tag_in,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ u_busy => u_busy,
+ u_addr => u_addr,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_data_wr => u_data_w,
+ u_data_rd => u_data_r,
+ u_dm => u_dm,
+
+ -- SDRAM signals
+ sd_clk_p => part_clk_p,
+ sd_clk_n => part_clk_n,
+ sd_cke => part_cke,
+ sd_cs_n => part_cs_n,
+ sd_cas_n => part_cas_n,
+ sd_ras_n => part_ras_n,
+ sd_we_n => part_we_n,
+ sd_addr => part_addr,
+ sd_ba => part_ba,
+ sd_dm => part_dm,
+ sd_dqs => part_dqs,
+ sd_data => part_data
+
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+ i_mt46v16m16_0 : entity work.mt46v16m16
+ port map (
+ dq => std_logic_vector(part_data),
+ dqs => std_logic_vector(part_dqs),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm)
+ );
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+------------------------------------------------------------------------------------------
+
+R_DATA_COMPARE:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_data_vld='1' then
+ if u_read_en = '1' and u_tag_rd = "0000" then
+ assert (ref_data = u_data_r) report "Error on read!" severity failure;
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ end if;
+ elsif u_read_en = '0' and rw_null_en = '0' then
+ last_data := (others => '0');
+ ref_data <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+W_DATA_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_req_wr = '1' and u_tag_wr = "0000" then
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ elsif u_write_en = '0' and rw_null_en = '0' then
+ last_data := (others => '0');
+ u_data_w <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+ADDR_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_addr_load = '1' then
+ lin_addr <= u_addr_preset;
+ rand_gen <= X"80";
+ elsif u_addr_cnt_en = '1' then
+ lin_addr <= lin_addr + BURST_LEN;
+ if rand_gen(rand_gen'left) = '1' then
+ rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010";
+ else
+ rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left);
+ end if;
+ end if;
+ end if;
+ end process;
+
+performance_count:
+ process(clk_out)
+ begin
+ if rising_edge(clk_out) then
+ if u_write_en = '1' or u_read_en = '1' then
+ cycle_cnt <= cycle_cnt + 1;
+ if u_req_wr = '1' or u_req_rd = '1' then
+ data_cnt <= data_cnt + 1;
+ end if;
+ else
+ cycle_cnt <= 1;
+ data_cnt <= 0;
+ end if;
+ end if;
+ end process;
+
+ u_tag_in <= "000" & rw_null_en;
+
+ efficiency <= real(data_cnt)/real(cycle_cnt);
+ u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
+ u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0';
+ u_addr <= (rand_gen(7) and (not rw_null_en)) & lin_addr(lin_addr'left-1 downto 0);
+ process
+ begin
+
+ -- Write MAX_WORDS to DDR SDRAM Controller
+ wait for 4*CLK_PERIOD;
+ rst <= '0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ wait for 137*CLK_PERIOD;
+
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ test_phase <= WRITE_MULTI;
+ u_addr_preset <= X"000000";
+ u_addr_end <= X"010000"-BURST_LEN;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_cmd <= UCMD_READ;
+ u_write_en <= '1';
+ rw_null_en <= '1';
+ while lin_addr /= u_addr_end loop
+ u_cmd <= UCMD_READ;
+ rw_null_en <= '1';
+ if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
+ if rand_gen(1) = '1' or rand_gen(7) = '1' then
+ u_cmd <= UCMD_WRITE;
+ end if;
+ rw_null_en <= '0';
+ end if;
+ wait until rising_edge(clk_out);
+ end loop;
+ u_write_en <= '0';
+ rw_null_en <= '0';
+ wait until rising_edge(clk_out) and u_req_wr='0';
+ wait for 200*CLK_PERIOD;
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ test_phase <= READ_MULTI;
+ u_addr_preset <= X"000000";
+ u_addr_end <= X"010000"-BURST_LEN;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_cmd <= UCMD_WRITE;
+ u_read_en <= '1';
+ rw_null_en <= '1';
+ while lin_addr /= u_addr_end loop
+ u_cmd <= UCMD_WRITE;
+ rw_null_en <= '1';
+ if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
+ if rand_gen(1) = '1' or rand_gen(7) = '1' then
+ u_cmd <= UCMD_READ;
+ end if;
+ rw_null_en <= '0';
+ end if;
+ wait until rising_edge(clk_out);
+ end loop;
+ u_read_en <= '0';
+ rw_null_en <= '0';
+ wait until rising_edge(clk_out) and u_data_vld='0';
+
+ wait;
+
+ end process;
+
+end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd
new file mode 100644
index 0000000..312d2a8
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd
@@ -0,0 +1,316 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.utils_pkg.all;
+
+entity tb_sdr_ctrl is
+end;
+
+architecture struct of tb_sdr_ctrl is
+
+ -- Number of user data words for simulation
+ constant CLK_PERIOD : time := 10 ns;
+ constant BURST_LEN : natural := 8;
+
+ signal rst : std_logic := '1';
+ signal clk : std_logic := '0';
+ signal rst_out : std_logic;
+ signal clk_out : std_logic;
+ signal clk_fb : std_logic;
+ signal part_clk_p : std_logic;
+ signal part_clk_n : std_logic;
+ signal part_cke : std_logic;
+ signal part_cs_n : std_logic;
+ signal part_we_n : std_logic;
+ signal part_ras_n : std_logic;
+ signal part_cas_n : std_logic;
+ signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+ signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+ signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+ signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ signal u_addr : user_addr_t := (others => '0');
+ signal lin_addr : user_addr_t := (others => '0');
+ signal rand_gen : unsigned(7 downto 0) := (others => '0');
+ signal u_tag_in : user_tag_t := "0000";
+ signal u_tag_rd : user_tag_t;
+ signal u_tag_wr : user_tag_t;
+ signal u_cmd : user_cmd_t := UCMD_NOP;
+ signal u_cmd_we : std_logic := '0';
+ signal u_busy : std_logic;
+ signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+ signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_data_vld : std_logic;
+ signal u_req_wr : std_logic;
+ signal u_req_rd : std_logic;
+ signal u_read_en : std_logic := '0';
+ signal u_write_en : std_logic := '0';
+ signal rw_null_en : std_logic := '0';
+ signal u_addr_cnt_en : std_logic := '0';
+ signal u_addr_load : std_logic := '0';
+ signal u_addr_preset : user_addr_t := (others => '0');
+ signal u_addr_end : user_addr_t := (others => '0');
+ signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
+ signal test_phase : test_phase_t := IDLE;
+
+ type u_addr_mode_t is (MONOTONIC, RANDOM);
+ signal u_addr_mode : u_addr_mode_t := MONOTONIC;
+ signal cycle_cnt : natural := 1;
+ signal data_cnt : natural := 0;
+ signal efficiency : real := 0.0;
+
+begin
+
+ clk_fb <= part_clk_p after 1 ns;
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl : entity work.sdram_ctrl_top
+ Generic map
+ (
+ BL => BURST_LEN,
+ read_phaseshift => 0,
+ f_sysclk => 100E6
+ )
+ Port map
+ (
+
+ sys_rst_in => rst,
+ sys_clk_in => clk,
+
+ sys_rst_out => rst_out,
+ sys_clk_out => clk_out,
+ sys_clk_fb => clk_fb,
+
+ -- User interface
+ u_data_vld => u_data_vld,
+ u_data_req_w => u_req_wr,
+ u_data_req_r => u_req_rd,
+ u_tag_in => u_tag_in,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ u_busy => u_busy,
+ u_addr => u_addr,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_data_wr => u_data_w,
+ u_data_rd => u_data_r,
+ u_dm => u_dm,
+
+ -- SDRAM signals
+ sd_clk_p => part_clk_p,
+ sd_clk_n => part_clk_n,
+ sd_cke => part_cke,
+ sd_cs_n => part_cs_n,
+ sd_cas_n => part_cas_n,
+ sd_ras_n => part_ras_n,
+ sd_we_n => part_we_n,
+ sd_addr => part_addr,
+ sd_ba => part_ba,
+ sd_dm => part_dm,
+ sd_dqs => part_dqs,
+ sd_data => part_data
+
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+ i_mt46v16m16_0 : entity work.mt46v16m16
+ port map (
+ dq => std_logic_vector(part_data),
+ dqs => std_logic_vector(part_dqs),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm)
+ );
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+------------------------------------------------------------------------------------------
+
+R_DATA_COMPARE:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_data_vld='1' then
+ if u_read_en = '1' and u_tag_rd = "0000" then
+ assert (ref_data = u_data_r) report "Error on read!" severity failure;
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ end if;
+ elsif u_read_en = '0' and rw_null_en = '0' then
+ last_data := (others => '0');
+ ref_data <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+W_DATA_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_req_wr = '1' and u_tag_wr = "0000" then
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ elsif u_write_en = '0' and rw_null_en = '0' then
+ last_data := (others => '0');
+ u_data_w <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+ADDR_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_addr_load = '1' then
+ lin_addr <= u_addr_preset;
+ rand_gen <= X"80";
+ elsif u_addr_cnt_en = '1' then
+ lin_addr <= lin_addr + BURST_LEN;
+ if rand_gen(rand_gen'left) = '1' then
+ rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010";
+ else
+ rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left);
+ end if;
+ end if;
+ end if;
+ end process;
+
+performance_count:
+ process(clk_out)
+ begin
+ if rising_edge(clk_out) then
+ if u_write_en = '1' or u_read_en = '1' then
+ cycle_cnt <= cycle_cnt + 1;
+ if u_req_wr = '1' or u_req_rd = '1' then
+ data_cnt <= data_cnt + 1;
+ end if;
+ else
+ cycle_cnt <= 1;
+ data_cnt <= 0;
+ end if;
+ end if;
+ end process;
+
+ u_tag_in <= "000" & rw_null_en;
+
+ efficiency <= real(data_cnt)/real(cycle_cnt);
+ u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
+ u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0';
+ u_addr <= (rand_gen(7) and (rw_null_en)) & lin_addr(lin_addr'left-1 downto 0);
+ process
+ begin
+
+ -- Write MAX_WORDS to DDR SDRAM Controller
+ wait for 4*CLK_PERIOD;
+ rst <= '0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ wait for 137*CLK_PERIOD;
+
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ test_phase <= WRITE_MULTI;
+ u_addr_preset <= X"000000";
+ u_addr_end <= X"010000"-BURST_LEN;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_cmd <= UCMD_WRITE;
+ u_write_en <= '1';
+ while lin_addr /= u_addr_end loop
+ u_cmd <= UCMD_WRITE;
+ rw_null_en <= '0';
+ if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
+ if rand_gen(1) = '1' or rand_gen(7) = '1' then
+ u_cmd <= UCMD_READ;
+ end if;
+ rw_null_en <= '1';
+ end if;
+ wait until rising_edge(clk_out);
+ end loop;
+ u_write_en <= '0';
+ rw_null_en <= '0';
+ wait until rising_edge(clk_out) and u_req_wr='0';
+ wait for 200*CLK_PERIOD;
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ test_phase <= READ_MULTI;
+ u_addr_preset <= X"000000";
+ u_addr_end <= X"010000"-BURST_LEN;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_cmd <= UCMD_READ;
+ u_read_en <= '1';
+ while lin_addr /= u_addr_end loop
+ u_cmd <= UCMD_READ;
+ rw_null_en <= '0';
+ if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
+ if rand_gen(1) = '1' or rand_gen(7) = '1' then
+ u_cmd <= UCMD_WRITE;
+ end if;
+ rw_null_en <= '1';
+ end if;
+ wait until rising_edge(clk_out);
+ end loop;
+ u_read_en <= '0';
+ rw_null_en <= '0';
+ wait until rising_edge(clk_out) and u_data_vld='0';
+
+ wait;
+
+ end process;
+
+end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd
new file mode 100644
index 0000000..e20e4af
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd
@@ -0,0 +1,315 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.utils_pkg.all;
+
+entity tb_sdr_ctrl is
+end;
+
+architecture struct of tb_sdr_ctrl is
+
+ -- Number of user data words for simulation
+ constant CLK_PERIOD : time := 10 ns;
+ constant BURST_LEN : natural := 8;
+
+ signal rst : std_logic := '1';
+ signal clk : std_logic := '0';
+ signal rst_out : std_logic;
+ signal clk_out : std_logic;
+ signal clk_fb : std_logic;
+ signal part_clk_p : std_logic;
+ signal part_clk_n : std_logic;
+ signal part_cke : std_logic;
+ signal part_cs_n : std_logic;
+ signal part_we_n : std_logic;
+ signal part_ras_n : std_logic;
+ signal part_cas_n : std_logic;
+ signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+ signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+ signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+ signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ signal u_addr : user_addr_t := (others => '0');
+ signal u_tag_in : user_tag_t := "0000";
+ signal u_tag_rd : user_tag_t;
+ signal u_tag_wr : user_tag_t;
+ signal u_cmd : user_cmd_t := UCMD_NOP;
+ signal u_cmd_we : std_logic := '0';
+ signal u_busy : std_logic;
+ signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+ signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_data_vld : std_logic;
+ signal u_req_wr : std_logic;
+ signal u_req_rd : std_logic;
+ signal u_read_en : std_logic := '0';
+ signal u_write_en : std_logic := '0';
+ signal u_addr_cnt_en : std_logic := '0';
+ signal u_addr_load : std_logic := '0';
+ signal u_addr_preset : user_addr_t := (others => '0');
+ signal u_addr_end : user_addr_t := (others => '0');
+ signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
+ signal test_phase : test_phase_t := IDLE;
+
+ type u_addr_mode_t is (MONOTONIC, RANDOM);
+ signal u_addr_mode : u_addr_mode_t := MONOTONIC;
+ signal cycle_cnt : natural := 1;
+ signal data_cnt : natural := 0;
+ signal efficiency : real := 0.0;
+
+begin
+
+ clk_fb <= part_clk_p after 1 ns;
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl : entity work.sdram_ctrl_top
+ Generic map
+ (
+ BL => BURST_LEN,
+ read_phaseshift => 0,
+ f_sysclk => 100E6
+ )
+ Port map
+ (
+
+ sys_rst_in => rst,
+ sys_clk_in => clk,
+
+ sys_rst_out => rst_out,
+ sys_clk_out => clk_out,
+ sys_clk_fb => clk_fb,
+
+ -- User interface
+ u_data_vld => u_data_vld,
+ u_data_req_w => u_req_wr,
+ u_data_req_r => u_req_rd,
+ u_tag_in => u_tag_in,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ u_busy => u_busy,
+ u_addr => u_addr,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_data_wr => u_data_w,
+ u_data_rd => u_data_r,
+ u_dm => u_dm,
+
+ -- SDRAM signals
+ sd_clk_p => part_clk_p,
+ sd_clk_n => part_clk_n,
+ sd_cke => part_cke,
+ sd_cs_n => part_cs_n,
+ sd_cas_n => part_cas_n,
+ sd_ras_n => part_ras_n,
+ sd_we_n => part_we_n,
+ sd_addr => part_addr,
+ sd_ba => part_ba,
+ sd_dm => part_dm,
+ sd_dqs => part_dqs,
+ sd_data => part_data
+
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+ i_mt46v16m16_0 : entity work.mt46v16m16
+ port map (
+ dq => std_logic_vector(part_data),
+ dqs => std_logic_vector(part_dqs),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm)
+ );
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+------------------------------------------------------------------------------------------
+
+R_DATA_COMPARE:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_data_vld='1' then
+ if u_read_en = '1' then
+ assert (ref_data = u_data_r) report "Error on read!" severity failure;
+ end if;
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ elsif u_read_en = '0' then
+ last_data := (others => '0');
+ ref_data <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+W_DATA_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_req_wr = '1' then
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ elsif u_write_en = '0' then
+ last_data := (others => '0');
+ u_data_w <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+ADDR_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_addr_load = '1' then
+ u_addr <= u_addr_preset;
+ elsif u_addr_cnt_en = '1' then
+ if u_addr_mode = MONOTONIC then
+ u_addr <= u_addr + BURST_LEN;
+ else
+ if u_addr(u_addr'left) = '1' then
+ if BURST_LEN = 2 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
+ elsif BURST_LEN = 4 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
+ elsif BURST_LEN = 8 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
+ end if;
+ else
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+performance_count:
+ process(clk_out)
+ begin
+ if rising_edge(clk_out) then
+ if u_write_en = '1' or u_read_en = '1' then
+ cycle_cnt <= cycle_cnt + 1;
+ if u_req_wr = '1' or u_req_rd = '1' then
+ data_cnt <= data_cnt + 1;
+ end if;
+ else
+ cycle_cnt <= 1;
+ data_cnt <= 0;
+ end if;
+ end if;
+ end process;
+
+ u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
+
+ efficiency <= real(data_cnt)/real(cycle_cnt);
+ u_cmd_we <= (u_write_en or u_read_en) and (not u_busy);
+ u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
+
+ process
+ begin
+
+ -- Write MAX_WORDS to DDR SDRAM Controller
+ wait for 4*CLK_PERIOD;
+ rst <= '0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ wait for 137*CLK_PERIOD;
+
+
wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ test_phase <= WRITE_MULTI;
+ u_addr_preset <= X"800000";
+ if BURST_LEN = 2 then
+ u_addr_end <= X"5E2330";
+ elsif BURST_LEN = 4 then
+ u_addr_end <= X"7DEDD0";
+ elsif BURST_LEN = 8 then
+ u_addr_end <= X"5666B0";
+ end if;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_addr_mode <= RANDOM;
+ u_cmd <= UCMD_WRITE;
+ u_write_en <= '1';
+ while u_addr /= u_addr_end loop
+ wait until rising_edge(clk_out);
+ end loop;
+ u_write_en <= '0';
+ wait until rising_edge(clk_out) and u_req_wr='0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ test_phase <= READ_MULTI;
+ u_addr_preset <= X"800000";
+ if BURST_LEN = 2 then
+ u_addr_end <= X"5E2330";
+ elsif BURST_LEN = 4 then
+ u_addr_end <= X"7DEDD0";
+ elsif BURST_LEN = 8 then
+ u_addr_end <= X"5666B0";
+ end if;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_addr_mode <= RANDOM;
+ u_cmd <= UCMD_READ;
+ u_read_en <= '1';
+ while u_addr /= u_addr_end loop
+ wait until rising_edge(clk_out);
+ end loop;
+ u_read_en <= '0';
+ wait until rising_edge(clk_out) and u_data_vld='0';
+
+ wait;
+
+ end process;
+
+end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd
new file mode 100644
index 0000000..26c8b9b
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd
@@ -0,0 +1,329 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.sdram_config.all;
+use work.sdram_types.all;
+use work.utils_pkg.all;
+
+entity tb_sdr_ctrl is
+end;
+
+architecture struct of tb_sdr_ctrl is
+
+ -- Number of user data words for simulation
+ constant CLK_PERIOD : time := 10 ns;
+ constant BURST_LEN : natural := 2;
+
+ signal rst : std_logic := '1';
+ signal clk : std_logic := '0';
+ signal rst_out : std_logic;
+ signal clk_out : std_logic;
+ signal clk_fb : std_logic;
+ signal part_clk_p : std_logic;
+ signal part_clk_n : std_logic;
+ signal part_cke : std_logic;
+ signal part_cs_n : std_logic;
+ signal part_we_n : std_logic;
+ signal part_ras_n : std_logic;
+ signal part_cas_n : std_logic;
+ signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+ signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+ signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+ signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ signal u_addr : user_addr_t := (others => '0');
+ signal u_tag_in : user_tag_t := "0000";
+ signal u_tag_rd : user_tag_t;
+ signal u_tag_wr : user_tag_t;
+ signal u_cmd : user_cmd_t := UCMD_NOP;
+ signal u_cmd_we : std_logic := '0';
+ signal u_busy : std_logic;
+ signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
+ signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal u_data_vld : std_logic;
+ signal u_req_wr : std_logic;
+ signal u_req_rd : std_logic;
+ signal u_read_en : std_logic := '0';
+ signal u_write_en : std_logic := '0';
+ signal rw_null_en : std_logic := '0';
+ signal u_addr_cnt_en : std_logic := '0';
+ signal u_addr_load : std_logic := '0';
+ signal u_addr_preset : user_addr_t := (others => '0');
+ signal u_addr_end : user_addr_t := (others => '0');
+ signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
+ signal test_phase : test_phase_t := IDLE;
+
+ type u_addr_mode_t is (MONOTONIC, RANDOM);
+ signal u_addr_mode : u_addr_mode_t := MONOTONIC;
+ signal cycle_cnt : natural := 1;
+ signal data_cnt : natural := 0;
+ signal efficiency : real := 0.0;
+
+begin
+
+ clk_fb <= part_clk_p after 1 ns;
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl : entity work.sdram_ctrl_top
+ Generic map
+ (
+ BL => BURST_LEN,
+ read_phaseshift => 0,
+ f_sysclk => 100E6
+ )
+ Port map
+ (
+
+ sys_rst_in => rst,
+ sys_clk_in => clk,
+
+ sys_rst_out => rst_out,
+ sys_clk_out => clk_out,
+ sys_clk_fb => clk_fb,
+
+ -- User interface
+ u_data_vld => u_data_vld,
+ u_data_req_w => u_req_wr,
+ u_data_req_r => u_req_rd,
+ u_tag_in => u_tag_in,
+ u_tag_rd => u_tag_rd,
+ u_tag_wr => u_tag_wr,
+ u_busy => u_busy,
+ u_addr => u_addr,
+ u_cmd => u_cmd,
+ u_cmd_we => u_cmd_we,
+ u_data_wr => u_data_w,
+ u_data_rd => u_data_r,
+ u_dm => u_dm,
+
+ -- SDRAM signals
+ sd_clk_p => part_clk_p,
+ sd_clk_n => part_clk_n,
+ sd_cke => part_cke,
+ sd_cs_n => part_cs_n,
+ sd_cas_n => part_cas_n,
+ sd_ras_n => part_ras_n,
+ sd_we_n => part_we_n,
+ sd_addr => part_addr,
+ sd_ba => part_ba,
+ sd_dm => part_dm,
+ sd_dqs => part_dqs,
+ sd_data => part_data
+
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+ i_mt46v16m16_0 : entity work.mt46v16m16
+ port map (
+ dq => std_logic_vector(part_data),
+ dqs => std_logic_vector(part_dqs),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm)
+ );
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+------------------------------------------------------------------------------------------
+
+R_DATA_COMPARE:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_data_vld='1' then
+ if u_read_en = '1' then
+ assert (ref_data = u_data_r) report "Error on read!" severity failure;
+ end if;
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ elsif u_read_en = '0' and rw_null_en = '0' then
+ last_data := (others => '0');
+ ref_data <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+W_DATA_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_req_wr = '1' then
+ for i in 0 to DDR_DATA_WIDTH/4-1 loop
+ u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
+ end loop;
+ last_data := last_data + DDR_DATA_WIDTH/4;
+ elsif u_write_en = '0' and rw_null_en = '0' then
+ last_data := (others => '0');
+ u_data_w <= (others => '0');
+ end if;
+ end if;
+ end process;
+
+ADDR_GEN:
+ process(clk_out)
+ variable last_data : unsigned(7 downto 0) := (others => '0');
+ begin
+ if rising_edge(clk_out) then
+ if u_addr_load = '1' then
+ u_addr <= u_addr_preset;
+ elsif u_addr_cnt_en = '1' then
+ if u_addr_mode = MONOTONIC then
+ u_addr <= u_addr + BURST_LEN;
+ else
+ if u_addr(u_addr'left) = '1' then
+ if BURST_LEN = 2 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
+ elsif BURST_LEN = 4 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
+ elsif BURST_LEN = 8 then
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
+ end if;
+ else
+ u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+performance_count:
+ process(clk_out)
+ begin
+ if rising_edge(clk_out) then
+ if u_write_en = '1' or u_read_en = '1' then
+ cycle_cnt <= cycle_cnt + 1;
+ if u_req_wr = '1' or u_req_rd = '1' then
+ data_cnt <= data_cnt + 1;
+ end if;
+ else
+ cycle_cnt <= 1;
+ data_cnt <= 0;
+ end if;
+ end if;
+ end process;
+
+ u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
+
+ efficiency <= real(data_cnt)/real(cycle_cnt);
+ u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
+ u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
+
+ process
+ begin
+
+ -- Write MAX_WORDS to DDR SDRAM Controller
+ wait for 4*CLK_PERIOD;
+ rst <= '0';
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ wait for 137*CLK_PERIOD;
+
+ -- Bank 0
+ test_phase <= WRITE_MULTI;
+ u_addr_preset <= X"800000";
+ if BURST_LEN = 2 then
+ u_addr_end <= X"646808";
+ elsif BURST_LEN = 4 then
+ u_addr_end <= X"7DEDD0";
+ elsif BURST_LEN = 8 then
+ u_addr_end <= X"5666B0";
+ end if;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_addr_mode <= RANDOM;
+ while u_addr /= u_addr_end loop
+ u_cmd <= UCMD_WRITE;
+ u_write_en <= '1';
+ rw_null_en <= '0';
+ if u_addr(20) = '0' then
+ u_cmd <= UCMD_READ;
+ u_write_en <= '0';
+ rw_null_en <= '1';
+ end if;
+ wait until rising_edge(clk_out);
+ end loop;
+ u_write_en <= '0';
+ rw_null_en <= '0';
+ wait for 200*CLK_PERIOD;
+
+ wait until rising_edge(clk_out) and u_busy='0';
+ -- Bank 0
+ test_phase <= READ_MULTI;
+ u_addr_preset <= X"800000";
+ if BURST_LEN = 2 then
+ u_addr_end <= X"646808";
+ elsif BURST_LEN = 4 then
+ u_addr_end <= X"7DEDD0";
+ elsif BURST_LEN = 8 then
+ u_addr_end <= X"5666B0";
+ end if;
+ u_addr_load <= '1';
+ wait until rising_edge(clk_out);
+ u_addr_load <= '0';
+ wait until rising_edge(clk_out);
+ u_addr_mode <= RANDOM;
+ while u_addr /= u_addr_end loop
+ u_cmd <= UCMD_READ;
+ u_read_en <= '1';
+ rw_null_en <= '0';
+ if u_addr(20) = '0' then
+ u_cmd <= UCMD_WRITE;
+ u_read_en <= '0';
+ rw_null_en <= '1';
+ end if;
+ wait until rising_edge(clk_out);
+ end loop;
+ u_read_en <= '0';
+ rw_null_en <= '0';
+ wait until rising_edge(clk_out) and u_data_vld='0';
+
+ wait;
+
+ end process;
+
+end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd
new file mode 100644
index 0000000..95ffa58
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd
@@ -0,0 +1,385 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.fifo_ctrl_pkg.all;
+use work.sdram_config.all;
+use work.sdram_types.all;
+
+entity tb_sdram_ctrl_frontend is
+end;
+
+architecture struct of tb_sdram_ctrl_frontend is
+
+ -- Number of user data words for simulation
+ constant CLK_PERIOD : time := 10 ns;
+ constant BURST_LEN : natural := 2;
+
+ signal rst : std_logic := '1';
+ signal clk : std_logic := '0';
+ signal rst_out : std_logic;
+ signal clk_out : std_logic;
+ signal clk_fb : std_logic;
+ signal part_clk_p : std_logic;
+ signal part_clk_n : std_logic;
+ signal part_cke : std_logic;
+ signal part_cs_n : std_logic;
+ signal part_we_n : std_logic;
+ signal part_ras_n : std_logic;
+ signal part_cas_n : std_logic;
+ signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
+ signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
+ signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
+ signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
+ signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+ signal addr : user_addr_t := (others => '0');
+ signal r_wn : std_logic := '0';
+ signal en : std_logic := '0';
+ signal busy : std_logic;
+ signal din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal be : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "1111";
+ signal dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal dout_vld : std_logic;
+ signal dout_re : std_logic;
+ signal dout_reg : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
+
+begin
+
+ clk_fb <= part_clk_p after 1 ns;
+
+ -- DDR SDRAM Controller Core
+ inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend
+ Generic map
+ (
+ BL => BURST_LEN,
+ read_phaseshift => 0,
+ f_sysclk => 100E6,
+ fifo_depth => 4
+ )
+ Port map
+ (
+
+ sys_rst_in => rst,
+ sys_clk_in => clk,
+
+ sys_rst_out => rst_out,
+ sys_clk_out => clk_out,
+ sys_clk_fb => clk_fb,
+
+ busy => busy,
+ en => en,
+ r_wn => r_wn,
+ be => be,
+ addr => addr,
+ din => din,
+ dout => dout,
+ dout_re => dout_re,
+ dout_vld => dout_vld,
+
+ -- SDRAM signals
+ sd_clk_p => part_clk_p,
+ sd_clk_n => part_clk_n,
+ sd_cke => part_cke,
+ sd_cs_n => part_cs_n,
+ sd_cas_n => part_cas_n,
+ sd_ras_n => part_ras_n,
+ sd_we_n => part_we_n,
+ sd_addr => part_addr,
+ sd_ba => part_ba,
+ sd_dm => part_dm,
+ sd_dqs => part_dqs,
+ sd_data => part_data
+
+ );
+
+ -- MICRON DDR SDRAM Simulation Model
+ i_mt46v16m16_0 : entity work.mt46v16m16
+ port map (
+ dq => std_logic_vector(part_data),
+ dqs => std_logic_vector(part_dqs),
+ addr => std_logic_vector(part_addr),
+ ba => std_logic_vector(part_ba),
+ clk => part_clk_p,
+ clk_n => part_clk_n,
+ cke => part_cke,
+ cs_n => part_cs_n,
+ ras_n => part_ras_n,
+ cas_n => part_cas_n,
+ we_n => part_we_n,
+ dm => std_logic_vector(part_dm)
+ );
+
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+read_register:
+ process(clk_out)
+ begin
+ if rising_edge(clk_out) then
+ if dout_vld = '1' then
+ dout_reg <= dout;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------------------------------
+ dout_re <= dout_vld;
+
+ process
+ begin
+
+ -- Write MAX_WORDS to DDR SDRAM Controller
+ wait for 4*CLK_PERIOD;
+ rst <= '0';
+
+ wait for 4*CLK_PERIOD;
+ wait until rising_edge(clk_out) and rst_out='0';
+
+ for i in 0 to 999 loop
+
en <= '1';
+ r_wn <= '0';
+ din <= to_unsigned(i, 32);
+ addr <= to_unsigned(2*i, 24);
+ wait until rising_edge(clk_out) and busy = '0';
+ end loop;
+
+ for i in 0 to 999 loop
+ en <= '1';
+ r_wn <= '1';
+ din <= to_unsigned(i, 32);
+ addr <= to_unsigned(2*i, 24);
+ wait until rising_edge(clk_out) and busy = '0';
+ end loop;
+
+ en <= '1';
+ r_wn <= '0';
+ din <= X"01020304";
+ addr <= X"000000";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"05060708";
+ addr <= X"000002";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"00001111";
+ addr <= X"000004";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"22223333";
+ addr <= X"000006";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"44445555";
+ addr <= X"000008";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"66667777";
+ addr <= X"00000a";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"88889999";
+ addr <= X"00000c";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"AAAABBBB";
+ addr <= X"00000e";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"CCCCDDDD";
+ addr <= X"000010";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"EEEEFFFF";
+ addr <= X"000012";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"FFFFFFFF";
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '1';
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"87CCCCCC";
+ be <= "1000";
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '1';
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"CC65CCCC";
+ be <= "0100";
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '1';
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"CCCC43CC";
+ be <= "0010";
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '1';
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"89ABCDEF";
+ addr <= X"000016";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"CCCCCC21";
+ be <= "0001";
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '1';
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"55555555";
+ be <= "1010";
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '1';
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"AAAAAAAA";
+ be <= "0101";
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '1';
+ addr <= X"000014";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ be <= "1111";
+ en <= '1';
+ r_wn <= '0';
+ din <= X"11223344";
+ addr <= X"000018";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ r_wn <= '1';
+ addr <= X"000010";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"55667788";
+ addr <= X"00001a";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"99990000";
+ addr <= X"00001c";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '1';
+ r_wn <= '0';
+ din <= X"AAAA5555";
+ addr <= X"000020";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ r_wn <= '1';
+ addr <= X"000000";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ r_wn <= '1';
+ addr <= X"000018";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ r_wn <= '1';
+ addr <= X"00001A";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ r_wn <= '1';
+ addr <= X"00001C";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ r_wn <= '1';
+ addr <= X"000020";
+
+ wait until rising_edge(clk_out) and busy = '0';
+ en <= '0';
+
+ wait;
+
+ end process;
+
+end architecture struct;
diff --git a/lib/VGA_ctrl/src/char_gen.vhd b/lib/VGA_ctrl/src/char_gen.vhd
new file mode 100644
index 0000000..5d82fc9
--- /dev/null
+++ b/lib/VGA_ctrl/src/char_gen.vhd
@@ -0,0 +1,546 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:25:45 10/15/05
+-- Design Name:
+-- Module Name: char_gen - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity char_gen is
+ Generic
+ (
+ tsvga : vga_timespec_t := ts_vga_800_600_72;
+
+ -- User supplied parameters
+ CHARACTER_SCALE : natural := 1;
+ CHAR_ROM_SIZE_X : natural := 8; -- Pixels
+ CHAR_ROM_SIZE_Y : natural := 16; -- Pixels
+ CHAR_ROM_DEPTH : natural := 256; -- Chars
+ MAX_CHAR_PER_LINE : natural := 32; -- Chars
+ MAX_LINE_PER_FRAME : natural := 16; -- Chars
+ CHAR_SPACING_X : natural := 0; -- Pixels
+ CHAR_SPACING_Y : natural := 0; -- Pixels
+ SCREEN_OFFSET_X : natural := 16; -- Pixels
+ SCREEN_OFFSET_Y : natural := 16 -- Pixels
+ );
+ Port
+ (
+ -- System signals
+ rst : in std_logic;
+ vga_clk : in std_logic;
+ sys_clk : in std_logic;
+ ce : in std_logic;
+ frame_pulse : in std_logic;
+
+
+ -- Host Signals
+ clr_screen : in std_logic;
+ clr_line : in std_logic;
+ ascii_data : in unsigned(7 downto 0);
+ ascii_data_we : in std_logic;
+ ascii_posy_we : in std_logic;
+ ascii_posx_we : in std_logic;
+ ready : out std_logic;
+
+ -- Control signals
+ pos_x : in natural range 0 to tsvga.ts_h.ncyc_scan-1;
+ pos_y : in natural range 0 to tsvga.ts_v.ncyc_scan-1;
+
+ -- Output
+ char_draw_en : out std_logic
+
+ );
+end char_gen;
+
+architecture Behavioral of char_gen is
+
+ constant A_RAM_ADDR_WIDTH : integer := 12;
+ constant A_RAM_DATA_WIDTH : integer := 8;
+
+ type offset_rom_t is array (0 to MAX_LINE_PER_FRAME-1) of unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
+
+
+
+ function gen_offset_rom(num_char_per_line, num_lines : natural) return offset_rom_t is
+ variable result : offset_rom_t;
+
+ variable offset : unsigned(A_RAM_ADDR_WIDTH-1 downto 0) := (others => '0');
+ begin
+ for i in 0 to num_lines-1 loop
+ result(i) := offset;
+ offset := offset + to_unsigned(num_char_per_line, A_RAM_ADDR_WIDTH-1);
+ end loop;
+ return result;
+ end gen_offset_rom;
+
+ constant offset_rom : offset_rom_t := gen_offset_rom(MAX_CHAR_PER_LINE, MAX_LINE_PER_FRAME);
+
+ -- Calculated parameters
+ type cg_state_t is (cg_init, cg_ready, cg_clr_line, cg_clr_screen);
+ signal s, sn : cg_state_t;
+
+ constant CELL_SIZE_X : natural := (CHAR_ROM_SIZE_X+CHAR_SPACING_X)*CHARACTER_SCALE;
+ constant CELL_SIZE_Y : natural := (CHAR_ROM_SIZE_Y+CHAR_SPACING_Y)*CHARACTER_SCALE;
+ constant CHAR_SIZE_X : natural := CHAR_ROM_SIZE_X*CHARACTER_SCALE;
+ constant CHAR_SIZE_Y : natural := CHAR_ROM_SIZE_Y*CHARACTER_SCALE;
+
+ signal line_offset : natural range 0 to MAX_LINE_PER_FRAME-1;
+ signal cell_x_cnt : natural range 0 to MAX_CHAR_PER_LINE-1;
+ signal cell_y_cnt : natural range 0 to MAX_LINE_PER_FRAME-1;
+ signal char_x_cnt : natural range 0 to CELL_SIZE_X-1;
+ signal char_y_cnt : natural range 0 to CELL_SIZE_Y-1;
+ signal char_rom_row : unsigned(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto 0);
+ signal char_rom_addr : unsigned(NextExpBaseTwo(CHAR_ROM_DEPTH*CHAR_ROM_SIZE_Y)-1 downto 0);
+ signal char_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0);
+ signal char_reg : unsigned((CHARACTER_SCALE*CHAR_ROM_SIZE_X)-1 downto 0);
+
+ signal a_addr_rd : unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
+ signal a_addr_wr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
+ signal a_data_rd : unsigned(A_RAM_DATA_WIDTH-1 downto 0);
+ signal a_data_wr : unsigned(A_RAM_DATA_WIDTH-1 downto 0);
+ signal a_ram_we : std_logic;
+ signal a_cnt : natural range 0 to 2**A_RAM_ADDR_WIDTH-1;
+ signal a_cnt_rst : std_logic;
+ signal a_cnt_en : std_logic;
+ signal csr_posx_reg : natural range 0 to MAX_CHAR_PER_LINE-1;
+ signal csr_posy_reg : natural range 0 to MAX_LINE_PER_FRAME-1;
+ signal a_data_reg : unsigned(A_RAM_DATA_WIDTH-1 downto 0);
+ signal a_data_we : std_logic;
+ signal csr_posx_overflow : std_logic;
+ signal csr_posx_cnt_din : natural range 0 to MAX_CHAR_PER_LINE-1;
+ signal csr_posx_cnt_set : std_logic;
+ signal csr_posx_cnt_en : std_logic;
+ signal csr_posy_overflow : std_logic;
+ signal csr_posy_cnt_din : natural range 0 to MAX_LINE_PER_FRAME-1;
+ signal csr_posy_cnt_set : std_logic;
+ signal csr_posy_cnt_en : std_logic;
+
+ signal line_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
+ signal char_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
+
+ -- Visible Cursor
+ constant CURSOR_BLINK_INTERVAL : natural := tsvga.nfps/2;
+
+ type cursor_rom_t is array (0 to 2*CHAR_ROM_SIZE_Y-1) of unsigned (CHAR_ROM_SIZE_X-1 downto 0);
+ constant cursor_rom : cursor_rom_t :=
+ (
+ -- Cursor off
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "00000000",
+ "11111111",
+ "11111111",
+ "11111111",
+
+ -- Cursor on
+ "00000000",
+ "00000000",
+ "11111111",
+ "11111111",
+ "11111111",
+ "11111111",
+ "11111111",
+ "11111111",
+ "11111111",
+ "11111111",
+ "11111111",
+ "11111111",
+ "11111111",
+ "00000000",
+ "00000000",
+ "00000000"
+
+ );
+ signal cursor_rom_addr : unsigned(NextExpBaseTwo(2*CHAR_ROM_SIZE_Y)-1 downto 0);
+ signal cursor_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0);
+ signal cursor_visible : std_logic;
+ signal cursor_cnt : natural range 0 to CURSOR_BLINK_INTERVAL-1;
+ signal csr_posx_synced : natural range 0 to MAX_CHAR_PER_LINE-1;
+ signal csr_posy_synced : natural range 0 to MAX_LINE_PER_FRAME-1;
+
+ -- Scrolling
+ signal scroll_offset : natural range 0 to MAX_CHAR_PER_LINE-1;
+ signal scroll_active : std_logic;
+
+
+begin
+
+ a_addr_rd <= to_unsigned(cell_x_cnt, a_addr_rd'length) + offset_rom(line_offset);
+ line_addr <= offset_rom(csr_posy_reg);
+ char_addr <= to_unsigned(csr_posx_reg, char_addr'length);
+ char_rom_addr <= a_data_rd & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1));
+ cursor_rom_addr <= cursor_visible & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1));
+
+ inst_char_rom : entity work.char_rom
+ PORT MAP
+ (
+ CLK => vga_clk,
+ ADDR => char_rom_addr,
+ DATA => char_rom_data
+ );
+
+ inst_ascii_ram: entity work.dpram
+ GENERIC MAP (
+ addr_width => A_RAM_ADDR_WIDTH,
+ data_width => A_RAM_DATA_WIDTH
+ )
+ PORT MAP(
+ clka => sys_clk,
+ clkb => vga_clk,
+ en_a => '1',
+ en_b => '1',
+ we_a => a_ram_we,
+ addr_a => a_addr_wr,
+ addr_b => a_addr_rd,
+ din_a => a_data_wr,
+ dout_b => a_data_rd
+ );
+
+ ---------------------------------------------------------------------------------------------
+ --- ASCII RAM control
+ ---------------------------------------------------------------------------------------------
+ asci_ram_fsm:
+ process (s, a_cnt, clr_line, clr_screen, a_data_we, a_data_reg, char_addr, line_addr)
+ begin
+ sn <= s;
+ a_cnt_rst <= '0';
+ a_cnt_en <= '0';
+ a_ram_we <= '0';
+ a_data_wr <= a_data_reg;
+ a_addr_wr <= char_addr + line_addr;
+ ready <= '0';
+
+ case s is
+
+ when cg_init =>
+ sn <= cg_clr_screen;
+ a_cnt_rst <= '1';
+ when cg_ready =>
+ ready <= '1';
+ a_ram_we <= a_data_we;
+ if clr_screen = '1' then
+ a_cnt_rst <= '1';
+ sn <= cg_clr_screen;
+ elsif clr_line = '1' then
+ a_cnt_rst <= '1';
+ sn <= cg_clr_line;
+ end if;
+ when cg_clr_line =>
+ a_ram_we <= '1';
+ a_cnt_en <= '1';
+ a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH);
+ a_addr_wr <= to_unsigned(a_cnt + to_integer(line_addr), A_RAM_ADDR_WIDTH);
+ if a_cnt = MAX_CHAR_PER_LINE-1 then
+ sn <= cg_ready;
+ end if;
+ when cg_clr_screen =>
+ a_ram_we <= '1';
+ a_cnt_en <= '1';
+ a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH);
+ a_addr_wr <= to_unsigned(a_cnt, A_RAM_ADDR_WIDTH);
+ if a_cnt = (2**A_RAM_ADDR_WIDTH-1) then
+ sn <= cg_ready;
+ end if;
+
+ when others =>
+ sn <= cg_ready;
+
+ end case;
+ end process;
+
+ asci_ram_fsm_next: process (rst, sys_clk)
+ begin
+ if rst = '1' then
+ s <= cg_init;
+ elsif rising_edge(sys_clk) then
+ s <= sn;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+ asci_ram_cnt: process (rst, sys_clk)
+ begin
+ if rst = '1' then
+ a_cnt <= 0;
+ elsif rising_edge(sys_clk) then
+ if a_cnt_rst = '1' then
+ a_cnt <= 0;
+ elsif a_cnt_en = '1' then
+ if a_cnt < (2**A_RAM_ADDR_WIDTH-1) then
+ a_cnt <= a_cnt + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+ asci_addr_reg: process (rst, sys_clk)
+ begin
+ if rst = '1' then
+ csr_posx_cnt_en <= '0';
+ csr_posx_cnt_set <= '0';
+ csr_posy_cnt_en <= '0';
+ csr_posy_cnt_set <= '0';
+ a_data_reg <= (others => '0');
+ a_data_we <= '0';
+ elsif rising_edge(sys_clk) then
+ a_data_we <= '0';
+ csr_posx_cnt_en <= '0';
+ csr_posx_cnt_set <= '0';
+ csr_posy_cnt_en <= '0';
+ csr_posy_cnt_set <= '0';
+ if ascii_posy_we = '1' then
+ csr_posy_cnt_din <= to_integer(ascii_data);
+ csr_posy_cnt_set <= '1';
+ elsif ascii_posx_we = '1' then
+ csr_posx_cnt_din <= to_integer(ascii_data);
+ csr_posx_cnt_set <= '1';
+ elsif ascii_data_we = '1' then
+ if ascii_data < X"20" then
+ if ascii_data = X"0D" then
+ csr_posx_cnt_din <= 0;
+ csr_posx_cnt_set <= '1';
+ elsif ascii_data = X"0A" then
+ csr_posy_cnt_en <= '1';
+ end if;
+ else
+ a_data_reg <= ascii_data - X"20";
+ a_data_we <= '1';
+ csr_posx_cnt_en <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ asci_csr_posx_counter:
+ process (rst, sys_clk)
+ begin
+ if rst = '1' then
+ csr_posx_reg <= 0;
+ csr_posx_overflow <= '0';
+ elsif rising_edge(sys_clk) then
+ csr_posx_overflow <= '0';
+ if csr_posx_cnt_set = '1' then
+ csr_posx_reg <= csr_posx_cnt_din;
+ elsif csr_posx_cnt_en = '1' then
+ if csr_posx_reg < MAX_CHAR_PER_LINE-1 then
+ csr_posx_reg <= csr_posx_reg + 1;
+ else
+ csr_posx_reg <= 0;
+ csr_posx_overflow <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ asci_csr_posy_counter:
+ process (rst, sys_clk)
+ begin
+ if rst = '1' then
+ csr_posy_reg <= 0;
+ csr_posy_overflow <= '0';
+ elsif rising_edge(sys_clk) then
+ csr_posy_overflow <= '0';
+ if csr_posy_cnt_set = '1' then
+ csr_posy_reg <= csr_posy_cnt_din;
+ elsif csr_posy_cnt_en = '1' or csr_posx_overflow = '1' then
+ if csr_posy_reg < MAX_LINE_PER_FRAME-1 then
+ csr_posy_reg <= csr_posy_reg + 1;
+ else
+ csr_posy_reg <= 0;
+ csr_posy_overflow <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ scroll_gen: process (rst, sys_clk)
+ begin
+ if rst = '1' then
+ scroll_offset <= 0;
+ scroll_active <= '0';
+ elsif rising_edge(sys_clk) then
+ if clr_screen = '1' then
+ scroll_offset <= 0;
+ scroll_active <= '0';
+ elsif csr_posy_overflow = '1' then
+ scroll_active <= '1';
+ scroll_offset <= 1;
+ end if;
+ if (csr_posy_cnt_en = '1' or csr_posx_overflow = '1') and scroll_active = '1' then
+ scroll_offset <= scroll_offset + 1;
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+ --- Cursor generator
+ ---------------------------------------------------------------------------------------------
+ proc_sync_csr_posx:
+ process(vga_clk)
+ variable p1, p2 : natural range 0 to MAX_CHAR_PER_LINE-1;
+ begin
+ if rising_edge(vga_clk) then
+ csr_posx_synced <= p2;
+ p2 := p1;
+ p1 := csr_posx_reg;
+ end if;
+ end process;
+
+ proc_sync_csr_posy:
+ process(vga_clk)
+ variable p1, p2 : natural range 0 to MAX_LINE_PER_FRAME-1;
+ begin
+ if rising_edge(vga_clk) then
+ csr_posy_synced <= p2;
+ p2 := p1;
+ p1 := csr_posy_reg;
+ end if;
+ end process;
+
+ csr_blink_cnt: process (rst, vga_clk)
+ begin
+ if rst = '1' then
+ cursor_cnt <= 0;
+ cursor_visible <= '0';
+ elsif rising_edge(vga_clk) then
+ if frame_pulse = '1' then
+ if cursor_cnt < CURSOR_BLINK_INTERVAL-1 then
+ cursor_cnt <= cursor_cnt + 1;
+ else
+ cursor_cnt <= 0;
+ cursor_visible <= not cursor_visible;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ cursor_rom_read: process (vga_clk)
+ begin
+ if rising_edge(vga_clk) then
+ cursor_rom_data <= (others => '0');
+ if (cell_x_cnt = csr_posx_synced) and (line_offset = csr_posy_synced) then
+ cursor_rom_data <= cursor_rom(to_integer(cursor_rom_addr));
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+ --- Character generator
+ ---------------------------------------------------------------------------------------------
+ char_rom_ctrl: process (vga_clk)
+ begin
+ if rising_edge(vga_clk) then
+ char_rom_row <= to_unsigned(char_y_cnt, char_rom_row'length);
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+ char_reg_ctrl: process (vga_clk)
+ begin
+ if rising_edge(vga_clk) and ce = '1' then
+ if char_x_cnt = 2 then -- +2 delay for ASCII-RAM access and CHAR-ROM access
+ for i in 0 to CHAR_ROM_SIZE_X-1 loop
+ for j in 0 to CHARACTER_SCALE-1 loop
+ char_reg(i*CHARACTER_SCALE + j) <= char_rom_data(i) xor cursor_rom_data(i);
+ end loop;
+ end loop;
+ else
+ char_reg <= char_reg(char_reg'left-1 downto 0) & '0';
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+ cg_ctrl: process (rst, vga_clk)
+ variable enable_x : std_logic;
+ variable enable_y : std_logic;
+ variable char_en : std_logic;
+ variable char_en2 : std_logic;
+ begin
+
+ if (rst = '1') then
+ enable_x := '0';
+ enable_y := '0';
+ line_offset <= 0;
+ cell_x_cnt <= 0;
+ cell_y_cnt <= 0;
+ char_x_cnt <= 0;
+ char_y_cnt <= 0;
+ char_en := '0';
+ elsif rising_edge(vga_clk) and ce = '1' then
+ char_draw_en <= char_en2 and char_reg(char_reg'left);
+ char_en2 := char_en;
+ char_en := '0';
+ if pos_y = SCREEN_OFFSET_Y then
+ enable_y := '1';
+ cell_y_cnt <= 0;
+ char_x_cnt <= 0;
+ line_offset <= scroll_offset;
+ end if;
+ if pos_x = SCREEN_OFFSET_X and enable_y = '1' then
+ enable_x := '1';
+ cell_x_cnt <= 0;
+ char_x_cnt <= 0;
+ elsif enable_x = '1' and enable_y = '1' then
+ if char_x_cnt < CELL_SIZE_X-1 then
+ char_x_cnt <= char_x_cnt + 1;
+ else
+ char_x_cnt <= 0;
+ if cell_x_cnt < MAX_CHAR_PER_LINE-1 then
+ cell_x_cnt <= cell_x_cnt + 1;
+ else
+ enable_x := '0';
+ if char_y_cnt < CELL_SIZE_Y-1 then
+ char_y_cnt <= char_y_cnt + 1;
+ else
+ char_y_cnt <= 0;
+ if cell_y_cnt < MAX_LINE_PER_FRAME-1 then
+ cell_y_cnt <= cell_y_cnt + 1;
+ else
+ enable_y := '0';
+ end if;
+ if line_offset < MAX_LINE_PER_FRAME-1 then
+ line_offset <= line_offset + 1;
+ else
+ line_offset <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+ if (char_x_cnt < CHAR_SIZE_X) and (char_y_cnt < CHAR_SIZE_Y) then
+ char_en := '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+end Behavioral;
diff --git a/lib/VGA_ctrl/src/clkgen_virtex4.vhd b/lib/VGA_ctrl/src/clkgen_virtex4.vhd
new file mode 100644
index 0000000..0b58baf
--- /dev/null
+++ b/lib/VGA_ctrl/src/clkgen_virtex4.vhd
@@ -0,0 +1,105 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:25:45 10/15/05
+-- Design Name:
+-- Module Name: vga_ctrl_core - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clkgen is
+ Generic
+ (
+ sys_freq : integer := 100E6;
+ tsvga : vga_timespec_t := ts_vga_800_600_72
+ );
+ Port
+ (
+ rst : in std_logic;
+ clk : in std_logic;
+ vga_clk : out std_logic;
+ dcm_locked : out std_logic
+ );
+end clkgen;
+
+architecture tech of clkgen is
+
+ signal vga_clk0 : std_logic;
+ signal dcm_clk0 : std_logic;
+ signal dcm_clk_fb : std_logic;
+
+ begin
+
+ -- Compnent instantiation
+ DCM_VGA_CLK_inst : DCM_BASE
+ generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => DCM_FREQ_D(sys_freq, tsvga.f_pxl_clk), -- Can be any interger from 1 to 32
+ CLKFX_MULTIPLY => DCM_FREQ_M(sys_freq, tsvga.f_pxl_clk), -- Can be any integer from 2 to 32
+ CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => DCM_PERIOD(sys_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
+ CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
+ CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
+ DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ -- an integer from 0 to 15
+ DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
+ DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
+ PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
+ STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ port map (
+ CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput
+ CLK180 => open, -- 180 degree DCM CLK output
+ CLK270 => open, -- 270 degree DCM CLK output
+ CLK2X => open, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => open, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => vga_clk0, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => dcm_locked, -- DCM LOCK status output
+ CLKFB => dcm_clk_fb, -- DCM clock feedback
+ CLKIN => clk, -- Clock input (from IBUFG, BUFG or DCM)
+ RST => rst -- DCM asynchronous reset input
+ );
+
+ BUFG_dcm_clk_fb : BUFG
+ port map
+ (
+ O => dcm_clk_fb, -- Clock buffer output
+ I => dcm_clk0 -- Clock buffer input
+ );
+
+ BUFG_vga_clk : BUFG
+ port map
+ (
+ O => vga_clk, -- Clock buffer output
+ I => vga_clk0 -- Clock buffer input
+ );
+
+
+end tech;
diff --git a/lib/VGA_ctrl/src/dpram.vhd b/lib/VGA_ctrl/src/dpram.vhd
new file mode 100644
index 0000000..b6c5419
--- /dev/null
+++ b/lib/VGA_ctrl/src/dpram.vhd
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram is
+ Generic
+ (
+ addr_width : integer := 3;
+ data_width : integer := 8
+ );
+ Port
+ (
+ clka : in STD_LOGIC;
+ clkb : in STD_LOGIC;
+ en_a : in STD_LOGIC;
+ en_b : in STD_LOGIC;
+ we_a : in STD_LOGIC;
+ addr_a : in unsigned (addr_width-1 downto 0);
+ addr_b : in unsigned (addr_width-1 downto 0);
+ din_a : in unsigned (data_width-1 downto 0);
+ dout_b : out unsigned (data_width-1 downto 0)
+ );
+end dpram;
+
+architecture Behavioral of dpram is
+
+ constant depth : integer := 2**addr_width;
+ type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+ signal RAM : RAMtype;
+
+begin
+
+process (clka)
+ begin
+ if clka'event and clka = '1' then
+ if en_a = '1' then
+ if we_a = '1' then
+ RAM(to_integer(addr_a)) <= din_a;
+ end if;
+ end if;
+ end if;
+end process;
+
+process (clkb)
+ begin
+ if clkb'event and clkb = '1' then
+ if en_b = '1' then
+ dout_b <= RAM(to_integer(addr_b));
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff
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index 0000000..a1d2353
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diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff
new file mode 100644
index 0000000..b5c16cc
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diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff
new file mode 100644
index 0000000..158e99f
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diff --git a/lib/VGA_ctrl/src/fonts/System_16x16.bff b/lib/VGA_ctrl/src/fonts/System_16x16.bff
new file mode 100644
index 0000000..4ca2523
Binary files /dev/null and b/lib/VGA_ctrl/src/fonts/System_16x16.bff differ
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd b/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd
new file mode 100644
index 0000000..5a544d0
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd
@@ -0,0 +1,540 @@
+-- generated with romgen v3.0 by MikeJ
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(7 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
+ constant ROM : ROM_ARRAY := (
+ x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0000
+ x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0008
+ x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0010
+ x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0018
+ x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0020
+ x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0028
+ x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0030
+ x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0038
+ x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0040
+ x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0048
+ x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0050
+ x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0058
+ x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0060
+ x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0068
+ x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0070
+ x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0078
+ x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0080
+ x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0088
+ x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0090
+ x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0098
+ x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x00A0
+ x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x00A8
+ x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0
+ x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x00B8
+ x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x00C0
+ x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8
+ x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x00D0
+ x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8
+ x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x00E0
+ x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8
+ x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0
+ x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
+ x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0108
+ x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0110
+ x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0118
+ x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0120
+ x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0128
+ x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130
+ x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0138
+ x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140
+ x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148
+ x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0150
+ x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
+ x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
+ x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178
+ x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0180
+ x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0188
+ x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0190
+ x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198
+ x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x01A0
+ x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8
+ x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0
+ x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x01B8
+ x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0
+ x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x01C8
+ x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0
+ x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8
+ x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
+ x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
+ x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
+ x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x01F8
+ x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200
+ x"08",x"1C",x"3E",x"7F",x"7F",x"1C",x"3E",x"00", -- 0x0208
+ x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0210
+ x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0218
+ x"00",x"00",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0220
+ x"00",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0228
+ x"00",x"00",x"00",x"00",x"FF",x"FF",x"00",x"00", -- 0x0230
+ x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0238
+ x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C", -- 0x0240
+ x"00",x"00",x"00",x"E0",x"F0",x"38",x"18",x"18", -- 0x0248
+ x"18",x"18",x"1C",x"0F",x"07",x"00",x"00",x"00", -- 0x0250
+ x"18",x"18",x"38",x"F0",x"E0",x"00",x"00",x"00", -- 0x0258
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FF",x"FF", -- 0x0260
+ x"C0",x"E0",x"70",x"38",x"1C",x"0E",x"07",x"03", -- 0x0268
+ x"03",x"07",x"0E",x"1C",x"38",x"70",x"E0",x"C0", -- 0x0270
+ x"FF",x"FF",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0278
+ x"FF",x"FF",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0280
+ x"00",x"3C",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288
+ x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"00", -- 0x0290
+ x"36",x"7F",x"7F",x"7F",x"3E",x"1C",x"08",x"00", -- 0x0298
+ x"60",x"60",x"60",x"60",x"60",x"60",x"60",x"60", -- 0x02A0
+ x"00",x"00",x"00",x"07",x"0F",x"1C",x"18",x"18", -- 0x02A8
+ x"C3",x"E7",x"7E",x"3C",x"3C",x"7E",x"E7",x"C3", -- 0x02B0
+ x"00",x"3C",x"7E",x"66",x"66",x"7E",x"3C",x"00", -- 0x02B8
+ x"18",x"18",x"66",x"66",x"18",x"18",x"3C",x"00", -- 0x02C0
+ x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x02C8
+ x"08",x"1C",x"3E",x"7F",x"3E",x"1C",x"08",x"00", -- 0x02D0
+ x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x02D8
+ x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x02E0
+ x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02E8
+ x"00",x"00",x"03",x"3E",x"76",x"36",x"36",x"00", -- 0x02F0
+ x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
+ x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308
+ x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310
+ x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0328
+ x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0330
+ x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0338
+ x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0340
+ x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348
+ x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350
+ x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0358
+ x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360
+ x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0368
+ x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0370
+ x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378
+ x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0380
+ x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0388
+ x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0390
+ x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0398
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0
+ x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8
+ x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0
+ x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
+ x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
+ x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8
+ x"03",x"03",x"03",x"03",x"03",x"03",x"FF",x"FF", -- 0x03D0
+ x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8
+ x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0
+ x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x03E8
+ x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0
+ x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8
+ x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0400
+ x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0408
+ x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0410
+ x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0418
+ x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0420
+ x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428
+ x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430
+ x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0438
+ x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0440
+ x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0448
+ x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0450
+ x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0458
+ x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460
+ x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0468
+ x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0470
+ x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0478
+ x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0480
+ x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0488
+ x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0490
+ x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0498
+ x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0
+ x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x04A8
+ x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x04B0
+ x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x04B8
+ x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x04C0
+ x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8
+ x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x04D0
+ x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8
+ x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x04E0
+ x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8
+ x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x04F0
+ x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x04F8
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500
+ x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0508
+ x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0510
+ x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0518
+ x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0520
+ x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0528
+ x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0530
+ x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0538
+ x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0540
+ x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0548
+ x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0550
+ x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0558
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0560
+ x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0568
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570
+ x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0578
+ x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0580
+ x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0588
+ x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0590
+ x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0598
+ x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x05A0
+ x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x05A8
+ x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x05B0
+ x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8
+ x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x05C0
+ x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x05C8
+ x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x05D0
+ x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x05D8
+ x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0
+ x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x05E8
+ x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0
+ x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x05F8
+ x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0600
+ x"F7",x"E3",x"C1",x"80",x"80",x"E3",x"C1",x"FF", -- 0x0608
+ x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0610
+ x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0618
+ x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0620
+ x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628
+ x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF", -- 0x0630
+ x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0638
+ x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0640
+ x"FF",x"FF",x"FF",x"1F",x"0F",x"C7",x"E7",x"E7", -- 0x0648
+ x"E7",x"E7",x"E3",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0650
+ x"E7",x"E7",x"C7",x"0F",x"1F",x"FF",x"FF",x"FF", -- 0x0658
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"00",x"00", -- 0x0660
+ x"3F",x"1F",x"8F",x"C7",x"E3",x"F1",x"F8",x"FC", -- 0x0668
+ x"FC",x"F8",x"F1",x"E3",x"C7",x"8F",x"1F",x"3F", -- 0x0670
+ x"00",x"00",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0678
+ x"00",x"00",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0680
+ x"FF",x"C3",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF", -- 0x0690
+ x"C9",x"80",x"80",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x0698
+ x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F", -- 0x06A0
+ x"FF",x"FF",x"FF",x"F8",x"F0",x"E3",x"E7",x"E7", -- 0x06A8
+ x"3C",x"18",x"81",x"C3",x"C3",x"81",x"18",x"3C", -- 0x06B0
+ x"FF",x"C3",x"81",x"99",x"99",x"81",x"C3",x"FF", -- 0x06B8
+ x"E7",x"E7",x"99",x"99",x"E7",x"E7",x"C3",x"FF", -- 0x06C0
+ x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x06C8
+ x"F7",x"E3",x"C1",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x06D0
+ x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x06D8
+ x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x06E0
+ x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x06E8
+ x"FF",x"FF",x"FC",x"C1",x"89",x"C9",x"C9",x"FF", -- 0x06F0
+ x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700
+ x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708
+ x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710
+ x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0728
+ x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0730
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0738
+ x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0740
+ x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750
+ x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0758
+ x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760
+ x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0768
+ x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0770
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778
+ x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0780
+ x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0788
+ x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0790
+ x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0798
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0
+ x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8
+ x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0
+ x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8
+ x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"00",x"00", -- 0x07D0
+ x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8
+ x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0
+ x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x07E8
+ x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0
+ x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0", -- 0x07F8
+ x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0800
+ x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0808
+ x"00",x"60",x"60",x"7C",x"66",x"66",x"7C",x"00", -- 0x0810
+ x"00",x"00",x"3C",x"60",x"60",x"60",x"3C",x"00", -- 0x0818
+ x"00",x"06",x"06",x"3E",x"66",x"66",x"3E",x"00", -- 0x0820
+ x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0828
+ x"00",x"0E",x"18",x"3E",x"18",x"18",x"18",x"00", -- 0x0830
+ x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"7C", -- 0x0838
+ x"00",x"60",x"60",x"7C",x"66",x"66",x"66",x"00", -- 0x0840
+ x"00",x"18",x"00",x"38",x"18",x"18",x"3C",x"00", -- 0x0848
+ x"00",x"06",x"00",x"06",x"06",x"06",x"06",x"3C", -- 0x0850
+ x"00",x"60",x"60",x"6C",x"78",x"6C",x"66",x"00", -- 0x0858
+ x"00",x"38",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0860
+ x"00",x"00",x"66",x"7F",x"7F",x"6B",x"63",x"00", -- 0x0868
+ x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0870
+ x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0878
+ x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0880
+ x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"06", -- 0x0888
+ x"00",x"00",x"7C",x"66",x"60",x"60",x"60",x"00", -- 0x0890
+ x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0898
+ x"00",x"18",x"7E",x"18",x"18",x"18",x"0E",x"00", -- 0x08A0
+ x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x08A8
+ x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x08B0
+ x"00",x"00",x"63",x"6B",x"7F",x"3E",x"36",x"00", -- 0x08B8
+ x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x08C0
+ x"00",x"00",x"66",x"66",x"66",x"3E",x"0C",x"78", -- 0x08C8
+ x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x08D0
+ x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x08D8
+ x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x08E0
+ x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x08E8
+ x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x08F0
+ x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x08F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
+ x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0908
+ x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0910
+ x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0918
+ x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0920
+ x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0928
+ x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0930
+ x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0938
+ x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0940
+ x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0948
+ x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0950
+ x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0958
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0960
+ x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0968
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0970
+ x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0978
+ x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0980
+ x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0988
+ x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0990
+ x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0998
+ x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x09A0
+ x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x09A8
+ x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x09B0
+ x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x09B8
+ x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x09C0
+ x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x09C8
+ x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x09D0
+ x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x09D8
+ x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x09E0
+ x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x09E8
+ x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x09F0
+ x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x09F8
+ x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0A00
+ x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A08
+ x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0A10
+ x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0A18
+ x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0A20
+ x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0A28
+ x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0A30
+ x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0A38
+ x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A40
+ x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0A48
+ x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0A50
+ x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0A58
+ x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0A60
+ x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0A68
+ x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0A70
+ x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0A78
+ x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0A80
+ x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0A88
+ x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0A90
+ x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0A98
+ x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x0AA0
+ x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0AA8
+ x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x0AB0
+ x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x0AB8
+ x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x0AC0
+ x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x0AC8
+ x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x0AD0
+ x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x0AD8
+ x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x0AE0
+ x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0AE8
+ x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0AF0
+ x"33",x"99",x"CC",x"66",x"33",x"99",x"CC",x"66", -- 0x0AF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
+ x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0B08
+ x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0B10
+ x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0B20
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0B28
+ x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0B30
+ x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B38
+ x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0B40
+ x"CC",x"99",x"33",x"66",x"CC",x"99",x"33",x"66", -- 0x0B48
+ x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B50
+ x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B58
+ x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0B60
+ x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0B68
+ x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0B78
+ x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B80
+ x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0B88
+ x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0B90
+ x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B98
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0BA0
+ x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0BA8
+ x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0BB0
+ x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
+ x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
+ x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0BC8
+ x"01",x"03",x"06",x"6C",x"78",x"70",x"60",x"00", -- 0x0BD0
+ x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x0BD8
+ x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x0BE0
+ x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x0BE8
+ x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x0BF0
+ x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x0BF8
+ x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0C00
+ x"FF",x"FF",x"C3",x"F9",x"C1",x"99",x"C1",x"FF", -- 0x0C08
+ x"FF",x"9F",x"9F",x"83",x"99",x"99",x"83",x"FF", -- 0x0C10
+ x"FF",x"FF",x"C3",x"9F",x"9F",x"9F",x"C3",x"FF", -- 0x0C18
+ x"FF",x"F9",x"F9",x"C1",x"99",x"99",x"C1",x"FF", -- 0x0C20
+ x"FF",x"FF",x"C3",x"99",x"81",x"9F",x"C3",x"FF", -- 0x0C28
+ x"FF",x"F1",x"E7",x"C1",x"E7",x"E7",x"E7",x"FF", -- 0x0C30
+ x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"83", -- 0x0C38
+ x"FF",x"9F",x"9F",x"83",x"99",x"99",x"99",x"FF", -- 0x0C40
+ x"FF",x"E7",x"FF",x"C7",x"E7",x"E7",x"C3",x"FF", -- 0x0C48
+ x"FF",x"F9",x"FF",x"F9",x"F9",x"F9",x"F9",x"C3", -- 0x0C50
+ x"FF",x"9F",x"9F",x"93",x"87",x"93",x"99",x"FF", -- 0x0C58
+ x"FF",x"C7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0C60
+ x"FF",x"FF",x"99",x"80",x"80",x"94",x"9C",x"FF", -- 0x0C68
+ x"FF",x"FF",x"83",x"99",x"99",x"99",x"99",x"FF", -- 0x0C70
+ x"FF",x"FF",x"C3",x"99",x"99",x"99",x"C3",x"FF", -- 0x0C78
+ x"FF",x"FF",x"83",x"99",x"99",x"83",x"9F",x"9F", -- 0x0C80
+ x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"F9", -- 0x0C88
+ x"FF",x"FF",x"83",x"99",x"9F",x"9F",x"9F",x"FF", -- 0x0C90
+ x"FF",x"FF",x"C1",x"9F",x"C3",x"F9",x"83",x"FF", -- 0x0C98
+ x"FF",x"E7",x"81",x"E7",x"E7",x"E7",x"F1",x"FF", -- 0x0CA0
+ x"FF",x"FF",x"99",x"99",x"99",x"99",x"C1",x"FF", -- 0x0CA8
+ x"FF",x"FF",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0CB0
+ x"FF",x"FF",x"9C",x"94",x"80",x"C1",x"C9",x"FF", -- 0x0CB8
+ x"FF",x"FF",x"99",x"C3",x"E7",x"C3",x"99",x"FF", -- 0x0CC0
+ x"FF",x"FF",x"99",x"99",x"99",x"C1",x"F3",x"87", -- 0x0CC8
+ x"FF",x"FF",x"81",x"F3",x"E7",x"CF",x"81",x"FF", -- 0x0CD0
+ x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x0CD8
+ x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x0CE0
+ x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x0CE8
+ x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x0CF0
+ x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x0CF8
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00
+ x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0D08
+ x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10
+ x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0D18
+ x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0D20
+ x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0D28
+ x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0D30
+ x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38
+ x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0D40
+ x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0D48
+ x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0D50
+ x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0D58
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0D60
+ x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0D68
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0D70
+ x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0D78
+ x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0D80
+ x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0D88
+ x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0D90
+ x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0D98
+ x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x0DA0
+ x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x0DA8
+ x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x0DB0
+ x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0DB8
+ x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x0DC0
+ x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x0DC8
+ x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x0DD0
+ x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0DD8
+ x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x0DE0
+ x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x0DE8
+ x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x0DF0
+ x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x0DF8
+ x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0E00
+ x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E08
+ x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0E10
+ x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0E18
+ x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0E20
+ x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0E28
+ x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0E30
+ x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0E38
+ x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E40
+ x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0E48
+ x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0E50
+ x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0E58
+ x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0E60
+ x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0E68
+ x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0E70
+ x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0E78
+ x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0E80
+ x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0E88
+ x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0E90
+ x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0E98
+ x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0EA0
+ x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0EA8
+ x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0EB0
+ x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x0EB8
+ x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x0EC0
+ x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x0EC8
+ x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x0ED0
+ x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0ED8
+ x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x0EE0
+ x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0EE8
+ x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0EF0
+ x"CC",x"66",x"33",x"99",x"CC",x"66",x"33",x"99", -- 0x0EF8
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00
+ x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0F08
+ x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0F10
+ x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0F20
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0F28
+ x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0F30
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F38
+ x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0F40
+ x"33",x"66",x"CC",x"99",x"33",x"66",x"CC",x"99", -- 0x0F48
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F50
+ x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F58
+ x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0F60
+ x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0F68
+ x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F70
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0F78
+ x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F80
+ x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0F88
+ x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0F90
+ x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F98
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0FA0
+ x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x0FA8
+ x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0FB0
+ x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8
+ x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x0FC8
+ x"FE",x"FC",x"F9",x"93",x"87",x"8F",x"9F",x"FF", -- 0x0FD0
+ x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x0FD8
+ x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0
+ x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x0FE8
+ x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0
+ x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0" -- 0x0FF8
+ );
+
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd b/lib/VGA_ctrl/src/fonts/char_rom_data.vhd
new file mode 100644
index 0000000..c52e7f7
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_data.vhd
@@ -0,0 +1,539 @@
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(7 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
+ constant ROM : ROM_ARRAY := (
+ x"7C",x"40",x"7C",x"44",x"7C",x"0C",x"0C",x"7C", -- 0x0000
+ x"3C",x"24",x"7E",x"62",x"62",x"62",x"62",x"00", -- 0x0008
+ x"7C",x"24",x"3E",x"32",x"32",x"32",x"7E",x"00", -- 0x0010
+ x"7E",x"42",x"40",x"60",x"60",x"62",x"7E",x"00", -- 0x0018
+ x"7E",x"22",x"22",x"32",x"32",x"32",x"7E",x"00", -- 0x0020
+ x"7E",x"40",x"40",x"78",x"60",x"60",x"7E",x"00", -- 0x0028
+ x"7E",x"40",x"40",x"78",x"60",x"60",x"60",x"00", -- 0x0030
+ x"7E",x"42",x"40",x"6E",x"62",x"62",x"7E",x"00", -- 0x0038
+ x"42",x"42",x"42",x"7E",x"62",x"62",x"62",x"00", -- 0x0040
+ x"10",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x0048
+ x"02",x"02",x"02",x"06",x"06",x"46",x"3C",x"00", -- 0x0050
+ x"42",x"44",x"48",x"7E",x"62",x"62",x"62",x"00", -- 0x0058
+ x"40",x"40",x"40",x"60",x"60",x"60",x"7E",x"00", -- 0x0060
+ x"66",x"5A",x"42",x"62",x"62",x"62",x"62",x"00", -- 0x0068
+ x"72",x"4A",x"4A",x"6A",x"6A",x"6A",x"66",x"00", -- 0x0070
+ x"7E",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x0078
+ x"7E",x"42",x"42",x"7E",x"60",x"60",x"60",x"00", -- 0x0080
+ x"7E",x"42",x"42",x"62",x"6A",x"64",x"7A",x"00", -- 0x0088
+ x"7E",x"42",x"42",x"7E",x"64",x"62",x"62",x"00", -- 0x0090
+ x"7E",x"42",x"40",x"7E",x"06",x"46",x"7E",x"00", -- 0x0098
+ x"7C",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x00A0
+ x"42",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x00A8
+ x"42",x"42",x"42",x"24",x"24",x"18",x"18",x"00", -- 0x00B0
+ x"62",x"62",x"62",x"62",x"42",x"5A",x"66",x"00", -- 0x00B8
+ x"42",x"24",x"18",x"7C",x"62",x"62",x"62",x"00", -- 0x00C0
+ x"42",x"42",x"42",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8
+ x"7E",x"02",x"1C",x"60",x"60",x"60",x"7E",x"00", -- 0x00D0
+ x"3C",x"20",x"20",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8
+ x"18",x"20",x"20",x"78",x"60",x"60",x"7C",x"00", -- 0x00E0
+ x"3C",x"04",x"04",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8
+ x"08",x"1C",x"2A",x"08",x"08",x"08",x"08",x"00", -- 0x00F0
+ x"00",x"20",x"40",x"FE",x"40",x"20",x"00",x"00", -- 0x00F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
+ x"18",x"18",x"1C",x"1C",x"1C",x"00",x"1C",x"00", -- 0x0108
+ x"36",x"36",x"12",x"12",x"00",x"00",x"00",x"00", -- 0x0110
+ x"24",x"24",x"7E",x"34",x"7E",x"34",x"34",x"00", -- 0x0118
+ x"08",x"3E",x"28",x"3E",x"1A",x"3E",x"18",x"00", -- 0x0120
+ x"70",x"52",x"74",x"08",x"1E",x"2A",x"4E",x"00", -- 0x0128
+ x"78",x"48",x"30",x"70",x"6A",x"64",x"7A",x"00", -- 0x0130
+ x"38",x"38",x"08",x"08",x"00",x"00",x"00",x"00", -- 0x0138
+ x"0C",x"10",x"20",x"30",x"30",x"10",x"0C",x"00", -- 0x0140
+ x"30",x"08",x"04",x"0C",x"0C",x"08",x"30",x"00", -- 0x0148
+ x"08",x"2A",x"1C",x"3E",x"1C",x"2A",x"08",x"00", -- 0x0150
+ x"00",x"08",x"08",x"3E",x"3E",x"0C",x"0C",x"00", -- 0x0158
+ x"00",x"00",x"00",x"00",x"1C",x"1C",x"04",x"04", -- 0x0160
+ x"00",x"00",x"00",x"7E",x"7E",x"00",x"00",x"00", -- 0x0168
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
+ x"00",x"02",x"04",x"08",x"10",x"20",x"40",x"00", -- 0x0178
+ x"7E",x"42",x"46",x"6A",x"72",x"62",x"7E",x"00", -- 0x0180
+ x"38",x"08",x"08",x"18",x"18",x"18",x"3C",x"00", -- 0x0188
+ x"7E",x"42",x"02",x"7E",x"60",x"60",x"7E",x"00", -- 0x0190
+ x"3E",x"02",x"02",x"1E",x"06",x"06",x"7E",x"00", -- 0x0198
+ x"40",x"40",x"44",x"44",x"7E",x"0C",x"0C",x"00", -- 0x01A0
+ x"3E",x"20",x"20",x"3E",x"06",x"46",x"7E",x"00", -- 0x01A8
+ x"7E",x"40",x"40",x"7E",x"62",x"62",x"7E",x"00", -- 0x01B0
+ x"7E",x"42",x"04",x"08",x"18",x"18",x"18",x"00", -- 0x01B8
+ x"3C",x"24",x"24",x"7E",x"62",x"62",x"7E",x"00", -- 0x01C0
+ x"7E",x"42",x"42",x"7E",x"06",x"06",x"7E",x"00", -- 0x01C8
+ x"00",x"00",x"18",x"00",x"18",x"18",x"00",x"00", -- 0x01D0
+ x"00",x"00",x"1C",x"00",x"1C",x"1C",x"04",x"04", -- 0x01D8
+ x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
+ x"00",x"00",x"7E",x"00",x"7E",x"7E",x"00",x"00", -- 0x01E8
+ x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
+ x"7E",x"42",x"02",x"3E",x"30",x"00",x"30",x"00", -- 0x01F8
+ x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x0200
+ x"18",x"3C",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x0208
+ x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"10", -- 0x0210
+ x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"00", -- 0x0218
+ x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0220
+ x"00",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228
+ x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00", -- 0x0230
+ x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x0238
+ x"04",x"04",x"04",x"04",x"04",x"04",x"04",x"04", -- 0x0240
+ x"00",x"00",x"00",x"C0",x"30",x"10",x"08",x"08", -- 0x0248
+ x"10",x"10",x"08",x"0C",x"03",x"00",x"00",x"00", -- 0x0250
+ x"08",x"08",x"10",x"30",x"C0",x"00",x"00",x"00", -- 0x0258
+ x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"FF", -- 0x0260
+ x"80",x"40",x"20",x"10",x"08",x"04",x"02",x"01", -- 0x0268
+ x"01",x"02",x"04",x"08",x"10",x"20",x"40",x"80", -- 0x0270
+ x"FF",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0278
+ x"FF",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0280
+ x"3C",x"7E",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288
+ x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00", -- 0x0290
+ x"24",x"7E",x"7E",x"7E",x"3C",x"18",x"18",x"00", -- 0x0298
+ x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x02A0
+ x"00",x"00",x"00",x"03",x"0C",x"08",x"10",x"10", -- 0x02A8
+ x"81",x"42",x"24",x"18",x"18",x"24",x"42",x"81", -- 0x02B0
+ x"3C",x"7E",x"66",x"42",x"66",x"7E",x"3C",x"00", -- 0x02B8
+ x"18",x"18",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x02C0
+ x"02",x"02",x"02",x"02",x"02",x"02",x"02",x"02", -- 0x02C8
+ x"00",x"18",x"3C",x"7E",x"7E",x"3C",x"18",x"00", -- 0x02D0
+ x"08",x"08",x"08",x"FF",x"08",x"08",x"08",x"08", -- 0x02D8
+ x"C0",x"30",x"C0",x"30",x"C0",x"30",x"C0",x"30", -- 0x02E0
+ x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x02E8
+ x"00",x"00",x"7C",x"24",x"64",x"64",x"66",x"00", -- 0x02F0
+ x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
+ x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308
+ x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310
+ x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320
+ x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0328
+ x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33", -- 0x0330
+ x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0338
+ x"00",x"00",x"00",x"00",x"CC",x"33",x"CC",x"33", -- 0x0340
+ x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348
+ x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350
+ x"08",x"08",x"08",x"0F",x"08",x"08",x"08",x"08", -- 0x0358
+ x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360
+ x"08",x"08",x"08",x"0F",x"00",x"00",x"00",x"00", -- 0x0368
+ x"00",x"00",x"00",x"F8",x"08",x"08",x"08",x"08", -- 0x0370
+ x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378
+ x"00",x"00",x"00",x"0F",x"08",x"08",x"08",x"08", -- 0x0380
+ x"08",x"08",x"08",x"FF",x"00",x"00",x"00",x"00", -- 0x0388
+ x"00",x"00",x"00",x"FF",x"08",x"08",x"08",x"08", -- 0x0390
+ x"08",x"08",x"08",x"F8",x"08",x"08",x"08",x"08", -- 0x0398
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0
+ x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8
+ x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0
+ x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
+ x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
+ x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8
+ x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"FF", -- 0x03D0
+ x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8
+ x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0
+ x"08",x"08",x"08",x"F8",x"00",x"00",x"00",x"00", -- 0x03E8
+ x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0
+ x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8
+ x"83",x"BF",x"83",x"BB",x"83",x"F3",x"F3",x"83", -- 0x0400
+ x"C3",x"DB",x"81",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0408
+ x"83",x"DB",x"C1",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0410
+ x"81",x"BD",x"BF",x"9F",x"9F",x"9D",x"81",x"FF", -- 0x0418
+ x"81",x"DD",x"DD",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0420
+ x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428
+ x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430
+ x"81",x"BD",x"BF",x"91",x"9D",x"9D",x"81",x"FF", -- 0x0438
+ x"BD",x"BD",x"BD",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0440
+ x"EF",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0448
+ x"FD",x"FD",x"FD",x"F9",x"F9",x"B9",x"C3",x"FF", -- 0x0450
+ x"BD",x"BB",x"B7",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0458
+ x"BF",x"BF",x"BF",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460
+ x"99",x"A5",x"BD",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0468
+ x"8D",x"B5",x"B5",x"95",x"95",x"95",x"99",x"FF", -- 0x0470
+ x"81",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x0478
+ x"81",x"BD",x"BD",x"81",x"9F",x"9F",x"9F",x"FF", -- 0x0480
+ x"81",x"BD",x"BD",x"9D",x"95",x"9B",x"85",x"FF", -- 0x0488
+ x"81",x"BD",x"BD",x"81",x"9B",x"9D",x"9D",x"FF", -- 0x0490
+ x"81",x"BD",x"BF",x"81",x"F9",x"B9",x"81",x"FF", -- 0x0498
+ x"83",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0
+ x"BD",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x04A8
+ x"BD",x"BD",x"BD",x"DB",x"DB",x"E7",x"E7",x"FF", -- 0x04B0
+ x"9D",x"9D",x"9D",x"9D",x"BD",x"A5",x"99",x"FF", -- 0x04B8
+ x"BD",x"DB",x"E7",x"83",x"9D",x"9D",x"9D",x"FF", -- 0x04C0
+ x"BD",x"BD",x"BD",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8
+ x"81",x"FD",x"E3",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x04D0
+ x"C3",x"DF",x"DF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8
+ x"E7",x"DF",x"DF",x"87",x"9F",x"9F",x"83",x"FF", -- 0x04E0
+ x"C3",x"FB",x"FB",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8
+ x"F7",x"E3",x"D5",x"F7",x"F7",x"F7",x"F7",x"FF", -- 0x04F0
+ x"FF",x"DF",x"BF",x"01",x"BF",x"DF",x"FF",x"FF", -- 0x04F8
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500
+ x"E7",x"E7",x"E3",x"E3",x"E3",x"FF",x"E3",x"FF", -- 0x0508
+ x"C9",x"C9",x"ED",x"ED",x"FF",x"FF",x"FF",x"FF", -- 0x0510
+ x"DB",x"DB",x"81",x"CB",x"81",x"CB",x"CB",x"FF", -- 0x0518
+ x"F7",x"C1",x"D7",x"C1",x"E5",x"C1",x"E7",x"FF", -- 0x0520
+ x"8F",x"AD",x"8B",x"F7",x"E1",x"D5",x"B1",x"FF", -- 0x0528
+ x"87",x"B7",x"CF",x"8F",x"95",x"9B",x"85",x"FF", -- 0x0530
+ x"C7",x"C7",x"F7",x"F7",x"FF",x"FF",x"FF",x"FF", -- 0x0538
+ x"F3",x"EF",x"DF",x"CF",x"CF",x"EF",x"F3",x"FF", -- 0x0540
+ x"CF",x"F7",x"FB",x"F3",x"F3",x"F7",x"CF",x"FF", -- 0x0548
+ x"F7",x"D5",x"E3",x"C1",x"E3",x"D5",x"F7",x"FF", -- 0x0550
+ x"FF",x"F7",x"F7",x"C1",x"C1",x"F3",x"F3",x"FF", -- 0x0558
+ x"FF",x"FF",x"FF",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x0560
+ x"FF",x"FF",x"FF",x"81",x"81",x"FF",x"FF",x"FF", -- 0x0568
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570
+ x"FF",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"FF", -- 0x0578
+ x"81",x"BD",x"B9",x"95",x"8D",x"9D",x"81",x"FF", -- 0x0580
+ x"C7",x"F7",x"F7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0588
+ x"81",x"BD",x"FD",x"81",x"9F",x"9F",x"81",x"FF", -- 0x0590
+ x"C1",x"FD",x"FD",x"E1",x"F9",x"F9",x"81",x"FF", -- 0x0598
+ x"BF",x"BF",x"BB",x"BB",x"81",x"F3",x"F3",x"FF", -- 0x05A0
+ x"C1",x"DF",x"DF",x"C1",x"F9",x"B9",x"81",x"FF", -- 0x05A8
+ x"81",x"BF",x"BF",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05B0
+ x"81",x"BD",x"FB",x"F7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8
+ x"C3",x"DB",x"DB",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05C0
+ x"81",x"BD",x"BD",x"81",x"F9",x"F9",x"81",x"FF", -- 0x05C8
+ x"FF",x"FF",x"E7",x"FF",x"E7",x"E7",x"FF",x"FF", -- 0x05D0
+ x"FF",x"FF",x"E3",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x05D8
+ x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0
+ x"FF",x"FF",x"81",x"FF",x"81",x"81",x"FF",x"FF", -- 0x05E8
+ x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0
+ x"81",x"BD",x"FD",x"C1",x"CF",x"FF",x"CF",x"FF", -- 0x05F8
+ x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF", -- 0x0600
+ x"E7",x"C3",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x0608
+ x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF", -- 0x0610
+ x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0618
+ x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0620
+ x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF", -- 0x0630
+ x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF", -- 0x0638
+ x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB", -- 0x0640
+ x"FF",x"FF",x"FF",x"3F",x"CF",x"EF",x"F7",x"F7", -- 0x0648
+ x"EF",x"EF",x"F7",x"F3",x"FC",x"FF",x"FF",x"FF", -- 0x0650
+ x"F7",x"F7",x"EF",x"CF",x"3F",x"FF",x"FF",x"FF", -- 0x0658
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"00", -- 0x0660
+ x"7F",x"BF",x"DF",x"EF",x"F7",x"FB",x"FD",x"FE", -- 0x0668
+ x"FE",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"7F", -- 0x0670
+ x"00",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0678
+ x"00",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0680
+ x"C3",x"81",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x0690
+ x"DB",x"81",x"81",x"81",x"C3",x"E7",x"E7",x"FF", -- 0x0698
+ x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF", -- 0x06A0
+ x"FF",x"FF",x"FF",x"FC",x"F3",x"F7",x"EF",x"EF", -- 0x06A8
+ x"7E",x"BD",x"DB",x"E7",x"E7",x"DB",x"BD",x"7E", -- 0x06B0
+ x"C3",x"81",x"99",x"BD",x"99",x"81",x"C3",x"FF", -- 0x06B8
+ x"E7",x"E7",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x06C0
+ x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD", -- 0x06C8
+ x"FF",x"E7",x"C3",x"81",x"81",x"C3",x"E7",x"FF", -- 0x06D0
+ x"F7",x"F7",x"F7",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x06D8
+ x"3F",x"CF",x"3F",x"CF",x"3F",x"CF",x"3F",x"CF", -- 0x06E0
+ x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7", -- 0x06E8
+ x"FF",x"FF",x"83",x"DB",x"9B",x"9B",x"99",x"FF", -- 0x06F0
+ x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700
+ x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708
+ x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710
+ x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0728
+ x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC", -- 0x0730
+ x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0738
+ x"FF",x"FF",x"FF",x"FF",x"33",x"CC",x"33",x"CC", -- 0x0740
+ x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750
+ x"F7",x"F7",x"F7",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0758
+ x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760
+ x"F7",x"F7",x"F7",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0768
+ x"FF",x"FF",x"FF",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0770
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778
+ x"FF",x"FF",x"FF",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0780
+ x"F7",x"F7",x"F7",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0788
+ x"FF",x"FF",x"FF",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x0790
+ x"F7",x"F7",x"F7",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0798
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0
+ x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8
+ x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0
+ x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8
+ x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8
+ x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"00", -- 0x07D0
+ x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8
+ x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0
+ x"F7",x"F7",x"F7",x"07",x"FF",x"FF",x"FF",x"FF", -- 0x07E8
+ x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0
+ x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"00", -- 0x07F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8
+ );
+
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd b/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd
new file mode 100644
index 0000000..95a9bd1
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd
@@ -0,0 +1,539 @@
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(7 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
+ constant ROM : ROM_ARRAY := (
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000
+ x"08",x"14",x"14",x"22",x"3E",x"41",x"41",x"80", -- 0x0008
+ x"FC",x"42",x"42",x"7C",x"42",x"42",x"42",x"FC", -- 0x0010
+ x"3C",x"46",x"40",x"40",x"40",x"40",x"46",x"3C", -- 0x0018
+ x"FC",x"42",x"42",x"42",x"42",x"42",x"42",x"FC", -- 0x0020
+ x"FC",x"46",x"50",x"70",x"50",x"40",x"46",x"FC", -- 0x0028
+ x"FC",x"46",x"50",x"70",x"50",x"40",x"40",x"E0", -- 0x0030
+ x"3C",x"46",x"40",x"4E",x"44",x"44",x"44",x"3C", -- 0x0038
+ x"EE",x"44",x"44",x"7C",x"44",x"44",x"44",x"EE", -- 0x0040
+ x"1C",x"08",x"08",x"08",x"08",x"08",x"08",x"1C", -- 0x0048
+ x"1C",x"08",x"08",x"08",x"08",x"08",x"C8",x"70", -- 0x0050
+ x"E6",x"48",x"50",x"60",x"50",x"48",x"44",x"EE", -- 0x0058
+ x"E0",x"40",x"40",x"40",x"40",x"40",x"46",x"FC", -- 0x0060
+ x"C6",x"6C",x"6C",x"54",x"54",x"44",x"44",x"EE", -- 0x0068
+ x"CE",x"64",x"64",x"54",x"54",x"4C",x"4C",x"E6", -- 0x0070
+ x"3C",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x0078
+ x"FC",x"42",x"42",x"7C",x"40",x"40",x"40",x"E0", -- 0x0080
+ x"3C",x"42",x"42",x"42",x"42",x"4A",x"46",x"3D", -- 0x0088
+ x"FC",x"42",x"42",x"7C",x"50",x"48",x"44",x"EE", -- 0x0090
+ x"3C",x"42",x"40",x"20",x"1C",x"02",x"C2",x"7C", -- 0x0098
+ x"FE",x"92",x"10",x"10",x"10",x"10",x"10",x"38", -- 0x00A0
+ x"E7",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x00A8
+ x"E7",x"42",x"42",x"42",x"42",x"42",x"24",x"18", -- 0x00B0
+ x"C3",x"41",x"5D",x"49",x"49",x"55",x"63",x"41", -- 0x00B8
+ x"EE",x"44",x"28",x"10",x"10",x"28",x"44",x"EE", -- 0x00C0
+ x"EE",x"44",x"44",x"28",x"10",x"10",x"10",x"38", -- 0x00C8
+ x"FE",x"84",x"08",x"7C",x"24",x"40",x"82",x"FE", -- 0x00D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
+ x"10",x"10",x"10",x"10",x"10",x"00",x"10",x"10", -- 0x0108
+ x"CC",x"44",x"44",x"22",x"00",x"00",x"00",x"00", -- 0x0110
+ x"77",x"22",x"FF",x"22",x"22",x"FF",x"22",x"77", -- 0x0118
+ x"10",x"3E",x"50",x"3C",x"12",x"12",x"7C",x"10", -- 0x0120
+ x"87",x"42",x"04",x"08",x"10",x"20",x"44",x"E2", -- 0x0128
+ x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130
+ x"1E",x"08",x"3C",x"00",x"00",x"00",x"00",x"00", -- 0x0138
+ x"0E",x"12",x"60",x"40",x"40",x"60",x"12",x"0E", -- 0x0140
+ x"70",x"48",x"06",x"02",x"02",x"06",x"48",x"70", -- 0x0148
+ x"42",x"24",x"99",x"7E",x"99",x"24",x"42",x"00", -- 0x0150
+ x"08",x"08",x"08",x"7F",x"08",x"08",x"08",x"00", -- 0x0158
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
+ x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
+ x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178
+ x"7C",x"82",x"82",x"82",x"82",x"82",x"82",x"7C", -- 0x0180
+ x"10",x"30",x"50",x"10",x"10",x"10",x"10",x"7C", -- 0x0188
+ x"7C",x"C2",x"02",x"1C",x"60",x"80",x"86",x"FC", -- 0x0190
+ x"7C",x"C2",x"02",x"1C",x"02",x"02",x"C2",x"7C", -- 0x0198
+ x"08",x"18",x"28",x"48",x"FE",x"08",x"08",x"3E", -- 0x01A0
+ x"FE",x"80",x"80",x"FC",x"02",x"02",x"C2",x"7C", -- 0x01A8
+ x"7C",x"86",x"80",x"FC",x"82",x"82",x"82",x"7C", -- 0x01B0
+ x"7E",x"C2",x"04",x"08",x"10",x"10",x"10",x"7C", -- 0x01B8
+ x"7C",x"82",x"82",x"7C",x"82",x"82",x"82",x"7C", -- 0x01C0
+ x"7C",x"82",x"82",x"7E",x"02",x"02",x"C2",x"7C", -- 0x01C8
+ x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0
+ x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8
+ x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
+ x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
+ x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
+ x"3C",x"62",x"02",x"04",x"08",x"08",x"00",x"08", -- 0x01F8
+ x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0200
+ x"FE",x"FE",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0208
+ x"FE",x"FE",x"C6",x"FC",x"C6",x"C6",x"FE",x"FE", -- 0x0210
+ x"FE",x"FE",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0218
+ x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0220
+ x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"FE",x"FE", -- 0x0228
+ x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0230
+ x"FE",x"FE",x"C0",x"DE",x"C6",x"C6",x"FE",x"FE", -- 0x0238
+ x"C6",x"C6",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0240
+ x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0248
+ x"18",x"18",x"18",x"18",x"18",x"18",x"78",x"78", -- 0x0250
+ x"C6",x"C6",x"DC",x"F0",x"D8",x"CC",x"C6",x"C6", -- 0x0258
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0260
+ x"FE",x"FE",x"D6",x"D6",x"D6",x"D6",x"D6",x"D6", -- 0x0268
+ x"E6",x"E6",x"F6",x"D6",x"D6",x"DE",x"CE",x"CE", -- 0x0270
+ x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0278
+ x"FE",x"FE",x"C6",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0280
+ x"FE",x"FE",x"C6",x"C6",x"C6",x"CE",x"FE",x"FF", -- 0x0288
+ x"FE",x"FE",x"C6",x"FE",x"D8",x"D8",x"C6",x"C6", -- 0x0290
+ x"FE",x"FE",x"C0",x"FE",x"06",x"06",x"FE",x"FE", -- 0x0298
+ x"FE",x"FE",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02A0
+ x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x02A8
+ x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"7C", -- 0x02B0
+ x"D6",x"D6",x"D6",x"D6",x"D6",x"D6",x"FE",x"FE", -- 0x02B8
+ x"C6",x"C6",x"6C",x"38",x"38",x"6C",x"C6",x"C6", -- 0x02C0
+ x"C6",x"C6",x"C6",x"FE",x"06",x"06",x"FE",x"FE", -- 0x02C8
+ x"FE",x"FE",x"0E",x"18",x"30",x"E0",x"FE",x"FE", -- 0x02D0
+ x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x02D8
+ x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x02E0
+ x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x02E8
+ x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x02F0
+ x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x02F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368
+ x"00",x"00",x"00",x"07",x"1F",x"3F",x"3F",x"7F", -- 0x0370
+ x"00",x"00",x"00",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0378
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
+ x"03",x"1F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0408
+ x"FC",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"0F", -- 0x0410
+ x"00",x"80",x"E0",x"F8",x"F8",x"FE",x"FE",x"FE", -- 0x0418
+ x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07", -- 0x0420
+ x"00",x"00",x"00",x"00",x"00",x"00",x"F8",x"FE", -- 0x0428
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0430
+ x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x0438
+ x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"7F", -- 0x0440
+ x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x0448
+ x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x0450
+ x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0458
+ x"00",x"00",x"00",x"00",x"00",x"00",x"1F",x"7F", -- 0x0460
+ x"00",x"00",x"00",x"00",x"00",x"00",x"E0",x"F8", -- 0x0468
+ x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7F",x"7F", -- 0x0470
+ x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"FF",x"FF", -- 0x0478
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC", -- 0x0480
+ x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0488
+ x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F1", -- 0x0490
+ x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"FF", -- 0x0498
+ x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x04A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x04A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x04B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0508
+ x"03",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0510
+ x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0518
+ x"07",x"07",x"07",x"00",x"00",x"07",x"0F",x"3F", -- 0x0520
+ x"FE",x"FF",x"FF",x"7F",x"3F",x"FF",x"FF",x"FF", -- 0x0528
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0530
+ x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"03", -- 0x0538
+ x"7F",x"7F",x"7F",x"07",x"03",x"7F",x"FF",x"FF", -- 0x0540
+ x"E0",x"F0",x"F1",x"F1",x"F3",x"F3",x"F3",x"F1", -- 0x0548
+ x"7F",x"FF",x"FF",x"FC",x"F0",x"F0",x"F0",x"F8", -- 0x0550
+ x"C0",x"C1",x"C1",x"03",x"03",x"03",x"03",x"03", -- 0x0558
+ x"FF",x"FF",x"FF",x"FF",x"F8",x"F0",x"F0",x"F0", -- 0x0560
+ x"FC",x"FE",x"FE",x"FF",x"7F",x"3F",x"3F",x"3F", -- 0x0568
+ x"7F",x"7F",x"7F",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0570
+ x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0578
+ x"FC",x"FC",x"FC",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0580
+ x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0588
+ x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0590
+ x"FF",x"FF",x"FF",x"F3",x"F1",x"F1",x"F1",x"F1", -- 0x0598
+ x"F0",x"F0",x"F8",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x05A0
+ x"7F",x"FF",x"FF",x"FC",x"F8",x"F8",x"F8",x"F8", -- 0x05A8
+ x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
+ x"3C",x"42",x"B9",x"A5",x"B9",x"A9",x"A5",x"42", -- 0x05B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0608
+ x"01",x"01",x"03",x"0F",x"7F",x"7F",x"7F",x"7F", -- 0x0610
+ x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FC",x"FC", -- 0x0618
+ x"3F",x"7F",x"7E",x"7C",x"7E",x"7F",x"3F",x"3F", -- 0x0620
+ x"FF",x"FF",x"3F",x"3F",x"3F",x"BF",x"BF",x"BF", -- 0x0628
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"1F", -- 0x0630
+ x"03",x"07",x"07",x"07",x"07",x"F7",x"F3",x"F3", -- 0x0638
+ x"FF",x"FF",x"E3",x"C3",x"E3",x"FB",x"FB",x"FB", -- 0x0640
+ x"F1",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0648
+ x"FC",x"FE",x"7F",x"3F",x"1F",x"0F",x"07",x"03", -- 0x0650
+ x"03",x"03",x"83",x"C3",x"E3",x"F1",x"F1",x"F0", -- 0x0658
+ x"F0",x"F0",x"F0",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0660
+ x"3F",x"3F",x"3F",x"3F",x"7F",x"FE",x"FE",x"FC", -- 0x0668
+ x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0670
+ x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"07", -- 0x0678
+ x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC",x"FC", -- 0x0680
+ x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0688
+ x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0690
+ x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0698
+ x"F9",x"F9",x"F9",x"F9",x"F9",x"F8",x"F8",x"F8", -- 0x06A0
+ x"F8",x"F8",x"F8",x"F8",x"FC",x"FF",x"FF",x"7F", -- 0x06A8
+ x"00",x"00",x"00",x"00",x"00",x"FC",x"FC",x"FC", -- 0x06B0
+ x"3C",x"00",x"00",x"00",x"78",x"FC",x"FC",x"FC", -- 0x06B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
+ x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0708
+ x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0710
+ x"F0",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
+ x"0F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
+ x"BF",x"BF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
+ x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
+ x"F0",x"F0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
+ x"FB",x"7B",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0740
+ x"F0",x"F8",x"FE",x"FF",x"FF",x"FF",x"3F",x"07", -- 0x0748
+ x"03",x"07",x"1F",x"FF",x"FF",x"FF",x"FE",x"F0", -- 0x0750
+ x"F0",x"F0",x"E0",x"E0",x"C0",x"80",x"00",x"00", -- 0x0758
+ x"7F",x"1F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
+ x"F8",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
+ x"7E",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
+ x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
+ x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
+ x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
+ x"F3",x"F3",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
+ x"F1",x"F1",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
+ x"F8",x"F8",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
+ x"3F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
+ x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
+ x"FC",x"78",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8
+ );
+
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd b/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd
new file mode 100644
index 0000000..ce977b6
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd
@@ -0,0 +1,539 @@
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(7 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
+ constant ROM : ROM_ARRAY := (
+ x"3C",x"66",x"6E",x"6A",x"6E",x"60",x"3C",x"00", -- 0x0000
+ x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0008
+ x"60",x"60",x"7C",x"66",x"66",x"66",x"7C",x"00", -- 0x0010
+ x"00",x"00",x"3C",x"66",x"60",x"66",x"3C",x"00", -- 0x0018
+ x"06",x"06",x"3E",x"66",x"66",x"66",x"3E",x"00", -- 0x0020
+ x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0028
+ x"1C",x"30",x"30",x"7C",x"30",x"30",x"30",x"00", -- 0x0030
+ x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"3C", -- 0x0038
+ x"60",x"60",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0040
+ x"18",x"00",x"38",x"18",x"18",x"18",x"3C",x"00", -- 0x0048
+ x"18",x"00",x"38",x"18",x"18",x"18",x"18",x"70", -- 0x0050
+ x"60",x"60",x"66",x"6C",x"78",x"6C",x"66",x"00", -- 0x0058
+ x"38",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0060
+ x"00",x"00",x"36",x"7F",x"6B",x"6B",x"63",x"00", -- 0x0068
+ x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0070
+ x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0078
+ x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0080
+ x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"07", -- 0x0088
+ x"00",x"00",x"6C",x"76",x"60",x"60",x"60",x"00", -- 0x0090
+ x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0098
+ x"30",x"30",x"7C",x"30",x"30",x"30",x"1C",x"00", -- 0x00A0
+ x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x00A8
+ x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0
+ x"00",x"00",x"63",x"6B",x"6B",x"7F",x"36",x"00", -- 0x00B8
+ x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x00C0
+ x"00",x"00",x"66",x"66",x"66",x"3E",x"06",x"3C", -- 0x00C8
+ x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x00D0
+ x"7C",x"60",x"60",x"60",x"60",x"60",x"7C",x"00", -- 0x00D8
+ x"1C",x"36",x"30",x"7C",x"30",x"30",x"7E",x"00", -- 0x00E0
+ x"3E",x"06",x"06",x"06",x"06",x"06",x"3E",x"00", -- 0x00E8
+ x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0
+ x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
+ x"18",x"18",x"18",x"18",x"18",x"00",x"18",x"00", -- 0x0108
+ x"6C",x"6C",x"6C",x"00",x"00",x"00",x"00",x"00", -- 0x0110
+ x"36",x"36",x"7F",x"36",x"7F",x"36",x"36",x"00", -- 0x0118
+ x"0C",x"3F",x"68",x"3E",x"0B",x"7E",x"18",x"00", -- 0x0120
+ x"60",x"66",x"0C",x"18",x"30",x"66",x"06",x"00", -- 0x0128
+ x"38",x"6C",x"6C",x"38",x"6D",x"66",x"3B",x"00", -- 0x0130
+ x"0C",x"18",x"30",x"00",x"00",x"00",x"00",x"00", -- 0x0138
+ x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140
+ x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148
+ x"00",x"18",x"7E",x"3C",x"7E",x"18",x"00",x"00", -- 0x0150
+ x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
+ x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
+ x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
+ x"00",x"06",x"0C",x"18",x"30",x"60",x"00",x"00", -- 0x0178
+ x"3C",x"66",x"6E",x"7E",x"76",x"66",x"3C",x"00", -- 0x0180
+ x"18",x"38",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0188
+ x"3C",x"66",x"06",x"0C",x"18",x"30",x"7E",x"00", -- 0x0190
+ x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198
+ x"0C",x"1C",x"3C",x"6C",x"7E",x"0C",x"0C",x"00", -- 0x01A0
+ x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8
+ x"1C",x"30",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0
+ x"7E",x"06",x"0C",x"18",x"30",x"30",x"30",x"00", -- 0x01B8
+ x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0
+ x"3C",x"66",x"66",x"3E",x"06",x"0C",x"38",x"00", -- 0x01C8
+ x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"00", -- 0x01D0
+ x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"30", -- 0x01D8
+ x"0C",x"18",x"30",x"60",x"30",x"18",x"0C",x"00", -- 0x01E0
+ x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
+ x"30",x"18",x"0C",x"06",x"0C",x"18",x"30",x"00", -- 0x01F0
+ x"3C",x"66",x"0C",x"18",x"18",x"00",x"18",x"00", -- 0x01F8
+ x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200
+ x"3C",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0208
+ x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0210
+ x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0218
+ x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0220
+ x"7E",x"60",x"60",x"7C",x"60",x"60",x"7E",x"00", -- 0x0228
+ x"7E",x"60",x"60",x"7C",x"60",x"60",x"60",x"00", -- 0x0230
+ x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0238
+ x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0240
+ x"7E",x"18",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0248
+ x"3E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0250
+ x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0258
+ x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0260
+ x"63",x"77",x"7F",x"6B",x"6B",x"63",x"63",x"00", -- 0x0268
+ x"66",x"66",x"76",x"7E",x"6E",x"66",x"66",x"00", -- 0x0270
+ x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0278
+ x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0280
+ x"3C",x"66",x"66",x"66",x"6A",x"6C",x"36",x"00", -- 0x0288
+ x"7C",x"66",x"66",x"7C",x"6C",x"66",x"66",x"00", -- 0x0290
+ x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0298
+ x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x02A0
+ x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x02A8
+ x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x02B0
+ x"63",x"63",x"6B",x"00",x"00",x"00",x"00",x"00", -- 0x02B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8
+ );
+
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd
new file mode 100644
index 0000000..3b60051
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd
@@ -0,0 +1,4383 @@
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port
+ (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(7 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
+ constant ROM : ROM_ARRAY :=
+ (
+ -- ASCII 032 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 033 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "00111100", -- | #### | 05
+ "00111100", -- | #### | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00000000", -- | | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 034 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 035 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110110", -- | ## ## | 03
+ "00110110", -- | ## ## | 04
+ "01111111", -- | #######| 05
+ "00110110", -- | ## ## | 06
+ "00110110", -- | ## ## | 07
+ "00110110", -- | ## ## | 08
+ "01111111", -- | #######| 09
+ "00110110", -- | ## ## | 10
+ "00110110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 036 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00011000", -- | ## | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00000110", -- | ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00011000", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00000000", -- | | 14
+ -- ASCII 037 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01110000", -- | ### | 02
+ "11011000", -- |## ## | 03
+ "11011010", -- |## ## # | 04
+ "01110110", -- | ### ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "01101110", -- | ## ### | 09
+ "01011011", -- | # ## ##| 10
+ "00011011", -- | ## ##| 11
+ "00001110", -- | ### | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 038 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "11111111", -- |########| 13
+ "00000000", -- | | 14
+ -- ASCII 039 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 040 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001100", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00110000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00000000", -- | | 14
+ -- ASCII 041 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00110000", -- | ## | 13
+ "00000000", -- | | 14
+ -- ASCII 042 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00110110", -- | ## ## | 05
+ "00011100", -- | ### | 06
+ "01111111", -- | #######| 07
+ "00011100", -- | ### | 08
+ "00110110", -- | ## ## | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 043 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "01111110", -- | ###### | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 044 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011100", -- | ### | 10
+ "00011100", -- | ### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00000000", -- | | 14
+ -- ASCII 045 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "01111110", -- | ###### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 046 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011100", -- | ### | 10
+ "00011100", -- | ### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 047 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000110", -- | ## | 03
+ "00000110", -- | ## | 04
+ "00001100", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "01100000", -- | ## | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 048 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011110", -- | #### | 03
+ "00110011", -- | ## ##| 04
+ "00110111", -- | ## ###| 05
+ "00110111", -- | ## ###| 06
+ "00110011", -- | ## ##| 07
+ "00111011", -- | ### ##| 08
+ "00111011", -- | ### ##| 09
+ "00110011", -- | ## ##| 10
+ "00011110", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 049 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001100", -- | ## | 03
+ "00011100", -- | ### | 04
+ "01111100", -- | ##### | 05
+ "00001100", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00001100", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 050 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00000110", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 051 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00000110", -- | ## | 06
+ "00011100", -- | ### | 07
+ "00000110", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 052 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110000", -- | ## | 03
+ "00110000", -- | ## | 04
+ "00110110", -- | ## ## | 05
+ "00110110", -- | ## ## | 06
+ "00110110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01111111", -- | #######| 09
+ "00000110", -- | ## | 10
+ "00000110", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 053 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "00000110", -- | ## | 08
+ "00000110", -- | ## | 09
+ "00001100", -- | ## | 10
+ "01111000", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 054 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011100", -- | ### | 03
+ "00011000", -- | ## | 04
+ "00110000", -- | ## | 05
+ "01111100", -- | ##### | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 055 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "00000110", -- | ## | 04
+ "00001100", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00110000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 056 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01110110", -- | ### ## | 06
+ "00111100", -- | #### | 07
+ "01101110", -- | ## ### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 057 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "00111110", -- | ##### | 08
+ "00001100", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111000", -- | ### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 058 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00011100", -- | ### | 05
+ "00011100", -- | ### | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011100", -- | ### | 10
+ "00011100", -- | ### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 059 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00011100", -- | ### | 05
+ "00011100", -- | ### | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011100", -- | ### | 10
+ "00011100", -- | ### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00000000", -- | | 14
+ -- ASCII 060 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000110", -- | ## | 03
+ "00001100", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00000110", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 061 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "01111110", -- | ###### | 06
+ "00000000", -- | | 07
+ "01111110", -- | ###### | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 062 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "00110000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 063 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00000000", -- | | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 064 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "11000011", -- |## ##| 04
+ "11000011", -- |## ##| 05
+ "11001111", -- |## ####| 06
+ "11011011", -- |## ## ##| 07
+ "11011011", -- |## ## ##| 08
+ "11001111", -- |## ####| 09
+ "11000000", -- |## | 10
+ "01111111", -- | #######| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 065 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 066 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111100", -- | ##### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01111100", -- | ##### | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 067 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 068 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111000", -- | #### | 03
+ "01101100", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01101100", -- | ## ## | 10
+ "01111000", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 069 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 070 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 071 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "01101110", -- | ## ### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 072 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01111110", -- | ###### | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 073 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 074 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000110", -- | ## | 03
+ "00000110", -- | ## | 04
+ "00000110", -- | ## | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00000110", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 075 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01101100", -- | ## ## | 05
+ "01101100", -- | ## ## | 06
+ "01111000", -- | #### | 07
+ "01101100", -- | ## ## | 08
+ "01101100", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 076 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 077 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100011", -- | ## ##| 03
+ "01100011", -- | ## ##| 04
+ "01110111", -- | ### ###| 05
+ "01101011", -- | ## # ##| 06
+ "01101011", -- | ## # ##| 07
+ "01101011", -- | ## # ##| 08
+ "01100011", -- | ## ##| 09
+ "01100011", -- | ## ##| 10
+ "01100011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 078 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100011", -- | ## ##| 03
+ "01100011", -- | ## ##| 04
+ "01110011", -- | ### ##| 05
+ "01111011", -- | #### ##| 06
+ "01101111", -- | ## ####| 07
+ "01100111", -- | ## ###| 08
+ "01100011", -- | ## ##| 09
+ "01100011", -- | ## ##| 10
+ "01100011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 079 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 080 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111100", -- | ##### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 081 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00001100", -- | ## | 12
+ "00000110", -- | ## | 13
+ "00000000", -- | | 14
+ -- ASCII 082 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111100", -- | ##### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01111100", -- | ##### | 07
+ "01101100", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 083 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00000110", -- | ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 084 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 085 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 086 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "00111100", -- | #### | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 087 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100011", -- | ## ##| 03
+ "01100011", -- | ## ##| 04
+ "01100011", -- | ## ##| 05
+ "01101011", -- | ## # ##| 06
+ "01101011", -- | ## # ##| 07
+ "01101011", -- | ## # ##| 08
+ "00110110", -- | ## ## | 09
+ "00110110", -- | ## ## | 10
+ "00110110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 088 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "00110100", -- | ## # | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00101100", -- | # ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 089 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "00111100", -- | #### | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 090 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "00000110", -- | ## | 04
+ "00000110", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 091 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00110000", -- | ## | 04
+ "00110000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00110000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00110000", -- | ## | 11
+ "00110000", -- | ## | 12
+ "00110000", -- | ## | 13
+ "00111100", -- | #### | 14
+ -- ASCII 092 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "00110000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00000110", -- | ## | 11
+ "00000110", -- | ## | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 093 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00001100", -- | ## | 04
+ "00001100", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00001100", -- | ## | 11
+ "00001100", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00111100", -- | #### | 14
+ -- ASCII 094 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 095 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "11111111", -- |########| 14
+ -- ASCII 096 ---------------
+ "00000000", -- | | 00
+ "00111000", -- | ### | 01
+ "00011000", -- | ## | 02
+ "00001100", -- | ## | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 097 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 098 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 099 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 100 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000110", -- | ## | 03
+ "00000110", -- | ## | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 101 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 102 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011110", -- | #### | 03
+ "00110000", -- | ## | 04
+ "00110000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "01111110", -- | ###### | 07
+ "00110000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00110000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 103 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000110", -- | ## | 12
+ "00000110", -- | ## | 13
+ "01111100", -- | ##### | 14
+ -- ASCII 104 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 105 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00011000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 106 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00001100", -- | ## | 02
+ "00001100", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00001100", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00001100", -- | ## | 11
+ "00001100", -- | ## | 12
+ "00001100", -- | ## | 13
+ "01111000", -- | #### | 14
+ -- ASCII 107 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01101100", -- | ## ## | 07
+ "01111000", -- | #### | 08
+ "01101100", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 108 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111000", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 109 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01111110", -- | ###### | 05
+ "01101011", -- | ## # ##| 06
+ "01101011", -- | ## # ##| 07
+ "01101011", -- | ## # ##| 08
+ "01101011", -- | ## # ##| 09
+ "01101011", -- | ## # ##| 10
+ "01100011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 110 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 111 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 112 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "01100000", -- | ## | 12
+ "01100000", -- | ## | 13
+ "01100000", -- | ## | 14
+ -- ASCII 113 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000110", -- | ## | 12
+ "00000110", -- | ## | 13
+ "00000110", -- | ## | 14
+ -- ASCII 114 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01101110", -- | ## ### | 06
+ "01110000", -- | ### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 115 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111110", -- | ##### | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "00111100", -- | #### | 08
+ "00000110", -- | ## | 09
+ "00000110", -- | ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 116 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110000", -- | ## | 03
+ "00110000", -- | ## | 04
+ "01111110", -- | ###### | 05
+ "00110000", -- | ## | 06
+ "00110000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00011110", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 117 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 118 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "00111100", -- | #### | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 119 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100011", -- | ## ##| 05
+ "01101011", -- | ## # ##| 06
+ "01101011", -- | ## # ##| 07
+ "01101011", -- | ## # ##| 08
+ "01101011", -- | ## # ##| 09
+ "00110110", -- | ## ## | 10
+ "00110110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 120 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "00111100", -- | #### | 07
+ "00011000", -- | ## | 08
+ "00111100", -- | #### | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 121 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "11110000", -- |#### | 14
+ -- ASCII 122 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01111110", -- | ###### | 05
+ "00000110", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 123 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001100", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00110000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00000000", -- | | 14
+ -- ASCII 124 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00011000", -- | ## | 14
+ -- ASCII 125 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00000110", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00110000", -- | ## | 13
+ "00000000", -- | | 14
+ -- ASCII 126 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01110001", -- | ### #| 03
+ "11011011", -- |## ## ##| 04
+ "10001110", -- |# ### | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 127 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 128 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 129 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 130 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 131 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 132 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 133 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 134 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 135 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 136 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 137 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 138 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 139 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 140 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 141 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 142 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 143 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 144 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 145 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001100", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011100", -- | ### | 05
+ "00011100", -- | ### | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 146 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011100", -- | ### | 03
+ "00011100", -- | ### | 04
+ "00001100", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 147 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 148 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 149 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 150 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 151 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 152 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 153 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 154 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 155 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 156 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 157 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 158 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 159 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 160 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 161 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00000000", -- | | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00111100", -- | #### | 12
+ "00111100", -- | #### | 13
+ "00011000", -- | ## | 14
+ -- ASCII 162 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "00111100", -- | #### | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 163 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "11111100", -- |###### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "11000000", -- |## | 10
+ "11111110", -- |####### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 164 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "01100110", -- | ## ## | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "00111100", -- | #### | 08
+ "01100110", -- | ## ## | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 165 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00111100", -- | #### | 06
+ "01111110", -- | ###### | 07
+ "00011000", -- | ## | 08
+ "01111110", -- | ###### | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 166 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00011000", -- | ## | 14
+ -- ASCII 167 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100000", -- | ## | 05
+ "00111000", -- | ### | 06
+ "00111100", -- | #### | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "00111100", -- | #### | 10
+ "00011100", -- | ### | 11
+ "00000110", -- | ## | 12
+ "01100110", -- | ## ## | 13
+ "00111100", -- | #### | 14
+ -- ASCII 168 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 169 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "11000011", -- |## ##| 04
+ "10011001", -- |# ## #| 05
+ "10100101", -- |# # # #| 06
+ "10100001", -- |# # #| 07
+ "10100101", -- |# # # #| 08
+ "10011001", -- |# ## #| 09
+ "11000011", -- |## ##| 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 170 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00000110", -- | ## | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "00111110", -- | ##### | 07
+ "00000000", -- | | 08
+ "01111110", -- | ###### | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 171 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00110011", -- | ## ##| 07
+ "01100110", -- | ## ## | 08
+ "11001100", -- |## ## | 09
+ "01100110", -- | ## ## | 10
+ "00110011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 172 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "01111110", -- | ###### | 07
+ "00000110", -- | ## | 08
+ "00000110", -- | ## | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 173 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "01111110", -- | ###### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 174 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "11000011", -- |## ##| 04
+ "10111001", -- |# ### #| 05
+ "10100101", -- |# # # #| 06
+ "10100101", -- |# # # #| 07
+ "10111001", -- |# ### #| 08
+ "10100101", -- |# # # #| 09
+ "11000011", -- |## ##| 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 175 ---------------
+ "11111111", -- |########| 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 176 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "00111100", -- | #### | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 177 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "01111110", -- | ###### | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00000000", -- | | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 178 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111000", -- | ### | 03
+ "00001100", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00111100", -- | #### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 179 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111000", -- | ### | 03
+ "00001100", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00111000", -- | ### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 180 ---------------
+ "00000000", -- | | 00
+ "00011100", -- | ### | 01
+ "00011000", -- | ## | 02
+ "00110000", -- | ## | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 181 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111011", -- | #### ##| 11
+ "01100000", -- | ## | 12
+ "01100000", -- | ## | 13
+ "11000000", -- |## | 14
+ -- ASCII 182 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011111", -- | #####| 03
+ "00111110", -- | ##### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "00111110", -- | ##### | 08
+ "00011110", -- | #### | 09
+ "00000110", -- | ## | 10
+ "00000110", -- | ## | 11
+ "00000110", -- | ## | 12
+ "00000110", -- | ## | 13
+ "00000110", -- | ## | 14
+ -- ASCII 183 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00011100", -- | ### | 06
+ "00011100", -- | ### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 184 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00111000", -- | ### | 14
+ -- ASCII 185 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111000", -- | ### | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 186 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "00111100", -- | #### | 07
+ "00000000", -- | | 08
+ "01111110", -- | ###### | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 187 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "11001100", -- |## ## | 07
+ "01100110", -- | ## ## | 08
+ "00110011", -- | ## ##| 09
+ "01100110", -- | ## ## | 10
+ "11001100", -- |## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 188 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100000", -- | ## | 02
+ "11100000", -- |### | 03
+ "01100011", -- | ## ##| 04
+ "01100110", -- | ## ## | 05
+ "01101100", -- | ## ## | 06
+ "00011000", -- | ## | 07
+ "00110111", -- | ## ###| 08
+ "01101111", -- | ## ####| 09
+ "11011011", -- |## ## ##| 10
+ "00011111", -- | #####| 11
+ "00000011", -- | ##| 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 189 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100000", -- | ## | 02
+ "11100000", -- |### | 03
+ "01100011", -- | ## ##| 04
+ "01100110", -- | ## ## | 05
+ "01101100", -- | ## ## | 06
+ "00011000", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100011", -- | ## ##| 09
+ "11000110", -- |## ## | 10
+ "00001100", -- | ## | 11
+ "00001111", -- | ####| 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 190 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "11100000", -- |### | 02
+ "00110000", -- | ## | 03
+ "01100011", -- | ## ##| 04
+ "00110110", -- | ## ## | 05
+ "11101100", -- |### ## | 06
+ "00011000", -- | ## | 07
+ "00110111", -- | ## ###| 08
+ "01101111", -- | ## ####| 09
+ "11011011", -- |## ## ##| 10
+ "00011111", -- | #####| 11
+ "00000011", -- | ##| 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 191 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00000000", -- | | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00110000", -- | ## | 11
+ "01100110", -- | ## ## | 12
+ "01100110", -- | ## ## | 13
+ "00111100", -- | #### | 14
+ -- ASCII 192 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 193 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 194 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 195 ---------------
+ "00111011", -- | ### ##| 00
+ "01101110", -- | ## ### | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 196 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 197 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00111100", -- | #### | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 198 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001111", -- | ####| 03
+ "00011100", -- | ### | 04
+ "00111100", -- | #### | 05
+ "01101100", -- | ## ## | 06
+ "01101111", -- | ## ####| 07
+ "01111100", -- | ##### | 08
+ "01101100", -- | ## ## | 09
+ "01101100", -- | ## ## | 10
+ "01101111", -- | ## ####| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 199 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00111000", -- | ### | 14
+ -- ASCII 200 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 201 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 202 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 203 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 204 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 205 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 206 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 207 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 208 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111000", -- | #### | 03
+ "01101100", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "11110110", -- |#### ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01101100", -- | ## ## | 10
+ "01111000", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 209 ---------------
+ "00111011", -- | ### ##| 00
+ "01101110", -- | ## ### | 01
+ "00000000", -- | | 02
+ "01100011", -- | ## ##| 03
+ "01100011", -- | ## ##| 04
+ "01110011", -- | ### ##| 05
+ "01111011", -- | #### ##| 06
+ "01101111", -- | ## ####| 07
+ "01100111", -- | ## ###| 08
+ "01100011", -- | ## ##| 09
+ "01100011", -- | ## ##| 10
+ "01100011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 210 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 211 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 212 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 213 ---------------
+ "00111011", -- | ### ##| 00
+ "01101110", -- | ## ### | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 214 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 215 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "01000010", -- | # # | 04
+ "01100110", -- | ## ## | 05
+ "00111100", -- | #### | 06
+ "00011000", -- | ## | 07
+ "00111100", -- | #### | 08
+ "01100110", -- | ## ## | 09
+ "01000010", -- | # # | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 216 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111110", -- | ##### | 03
+ "01100110", -- | ## ## | 04
+ "01101110", -- | ## ### | 05
+ "01101110", -- | ## ### | 06
+ "01111110", -- | ###### | 07
+ "01110110", -- | ### ## | 08
+ "01110110", -- | ### ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 217 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 218 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 219 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 220 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 221 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "00111100", -- | #### | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 222 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01111100", -- | ##### | 09
+ "01100000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 223 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111000", -- | ### | 03
+ "01101100", -- | ## ## | 04
+ "01101100", -- | ## ## | 05
+ "01101100", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01101100", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 224 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 225 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 226 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 227 ---------------
+ "00000000", -- | | 00
+ "01110001", -- | ### #| 01
+ "11011011", -- |## ## ##| 02
+ "10001110", -- |# ### | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 228 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 229 ---------------
+ "00000000", -- | | 00
+ "00111100", -- | #### | 01
+ "01100110", -- | ## ## | 02
+ "00111100", -- | #### | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 230 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01101110", -- | ## ### | 05
+ "00011011", -- | ## ##| 06
+ "00011011", -- | ## ##| 07
+ "01111111", -- | #######| 08
+ "11011000", -- |## ## | 09
+ "11011000", -- |## ## | 10
+ "01110111", -- | ### ###| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 231 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00111000", -- | ### | 14
+ -- ASCII 232 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 233 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 234 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 235 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 236 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 237 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 238 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 239 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 240 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110110", -- | ## ## | 03
+ "00011000", -- | ## | 04
+ "01101100", -- | ## ## | 05
+ "00011110", -- | #### | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 241 ---------------
+ "00000000", -- | | 00
+ "01110001", -- | ### #| 01
+ "11011011", -- |## ## ##| 02
+ "10001110", -- |# ### | 03
+ "00000000", -- | | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 242 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 243 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 244 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 245 ---------------
+ "00000000", -- | | 00
+ "01110001", -- | ### #| 01
+ "11011011", -- |## ## ##| 02
+ "10001110", -- |# ### | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 246 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 247 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00000000", -- | | 06
+ "01111110", -- | ###### | 07
+ "00000000", -- | | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 248 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01101110", -- | ## ### | 07
+ "01111110", -- | ###### | 08
+ "01110110", -- | ### ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 249 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 250 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 251 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 252 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 253 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "11110000", -- |#### | 14
+ -- ASCII 254 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01111100", -- | ##### | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "01100000", -- | ## | 12
+ "01100000", -- | ## | 13
+ "01100000", -- | ## | 14
+ -- ASCII 255 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "11110000", -- |#### | 14
+ -- ASCII 256 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 257 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 258 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 259 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 260 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 261 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 262 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 263 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 264 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 265 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 266 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 267 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 268 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 269 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 270 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 271 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 272 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 273 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 274 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 275 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 276 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 277 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 278 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 279 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 280 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 281 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 282 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 283 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 284 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 285 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 286 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- ASCII 287 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ -- Padding ---------------
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000", -- Padded
+ "00000000" -- Padded
+ );
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+
+end RTL;
+
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd
new file mode 100644
index 0000000..e46151c
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd
@@ -0,0 +1,4382 @@
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port
+ (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(7 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
+ constant ROM : ROM_ARRAY :=
+ (
+ -- ASCII 032 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 033 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "00111100", -- | #### | 05
+ "00111100", -- | #### | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00000000", -- | | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 034 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 035 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110110", -- | ## ## | 03
+ "00110110", -- | ## ## | 04
+ "01111111", -- | #######| 05
+ "00110110", -- | ## ## | 06
+ "00110110", -- | ## ## | 07
+ "00110110", -- | ## ## | 08
+ "01111111", -- | #######| 09
+ "00110110", -- | ## ## | 10
+ "00110110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 036 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00011000", -- | ## | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00000110", -- | ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00011000", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 037 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01110000", -- | ### | 02
+ "11011000", -- |## ## | 03
+ "11011010", -- |## ## # | 04
+ "01110110", -- | ### ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "01101110", -- | ## ### | 09
+ "01011011", -- | # ## ##| 10
+ "00011011", -- | ## ##| 11
+ "00001110", -- | ### | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 038 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "11111111", -- |########| 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 039 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 040 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001100", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00110000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 041 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00110000", -- | ## | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 042 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00110110", -- | ## ## | 05
+ "00011100", -- | ### | 06
+ "01111111", -- | #######| 07
+ "00011100", -- | ### | 08
+ "00110110", -- | ## ## | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 043 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "01111110", -- | ###### | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 044 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011100", -- | ### | 10
+ "00011100", -- | ### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 045 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "01111110", -- | ###### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 046 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011100", -- | ### | 10
+ "00011100", -- | ### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 047 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000110", -- | ## | 03
+ "00000110", -- | ## | 04
+ "00001100", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "01100000", -- | ## | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 048 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011110", -- | #### | 03
+ "00110011", -- | ## ##| 04
+ "00110111", -- | ## ###| 05
+ "00110111", -- | ## ###| 06
+ "00110011", -- | ## ##| 07
+ "00111011", -- | ### ##| 08
+ "00111011", -- | ### ##| 09
+ "00110011", -- | ## ##| 10
+ "00011110", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 049 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001100", -- | ## | 03
+ "00011100", -- | ### | 04
+ "01111100", -- | ##### | 05
+ "00001100", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00001100", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 050 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00000110", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 051 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00000110", -- | ## | 06
+ "00011100", -- | ### | 07
+ "00000110", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 052 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110000", -- | ## | 03
+ "00110000", -- | ## | 04
+ "00110110", -- | ## ## | 05
+ "00110110", -- | ## ## | 06
+ "00110110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01111111", -- | #######| 09
+ "00000110", -- | ## | 10
+ "00000110", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 053 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "00000110", -- | ## | 08
+ "00000110", -- | ## | 09
+ "00001100", -- | ## | 10
+ "01111000", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 054 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011100", -- | ### | 03
+ "00011000", -- | ## | 04
+ "00110000", -- | ## | 05
+ "01111100", -- | ##### | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 055 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "00000110", -- | ## | 04
+ "00001100", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00110000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 056 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01110110", -- | ### ## | 06
+ "00111100", -- | #### | 07
+ "01101110", -- | ## ### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 057 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "00111110", -- | ##### | 08
+ "00001100", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111000", -- | ### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 058 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00011100", -- | ### | 05
+ "00011100", -- | ### | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011100", -- | ### | 10
+ "00011100", -- | ### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 059 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00011100", -- | ### | 05
+ "00011100", -- | ### | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011100", -- | ### | 10
+ "00011100", -- | ### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 060 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000110", -- | ## | 03
+ "00001100", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00000110", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 061 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "01111110", -- | ###### | 06
+ "00000000", -- | | 07
+ "01111110", -- | ###### | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 062 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "00110000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 063 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00000000", -- | | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 064 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "11000011", -- |## ##| 04
+ "11000011", -- |## ##| 05
+ "11001111", -- |## ####| 06
+ "11011011", -- |## ## ##| 07
+ "11011011", -- |## ## ##| 08
+ "11001111", -- |## ####| 09
+ "11000000", -- |## | 10
+ "01111111", -- | #######| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 065 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 066 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111100", -- | ##### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01111100", -- | ##### | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 067 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 068 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111000", -- | #### | 03
+ "01101100", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01101100", -- | ## ## | 10
+ "01111000", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 069 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 070 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 071 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "01101110", -- | ## ### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 072 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01111110", -- | ###### | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 073 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 074 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000110", -- | ## | 03
+ "00000110", -- | ## | 04
+ "00000110", -- | ## | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00000110", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 075 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01101100", -- | ## ## | 05
+ "01101100", -- | ## ## | 06
+ "01111000", -- | #### | 07
+ "01101100", -- | ## ## | 08
+ "01101100", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 076 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 077 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100011", -- | ## ##| 03
+ "01100011", -- | ## ##| 04
+ "01110111", -- | ### ###| 05
+ "01101011", -- | ## # ##| 06
+ "01101011", -- | ## # ##| 07
+ "01101011", -- | ## # ##| 08
+ "01100011", -- | ## ##| 09
+ "01100011", -- | ## ##| 10
+ "01100011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 078 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100011", -- | ## ##| 03
+ "01100011", -- | ## ##| 04
+ "01110011", -- | ### ##| 05
+ "01111011", -- | #### ##| 06
+ "01101111", -- | ## ####| 07
+ "01100111", -- | ## ###| 08
+ "01100011", -- | ## ##| 09
+ "01100011", -- | ## ##| 10
+ "01100011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 079 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 080 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111100", -- | ##### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 081 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00001100", -- | ## | 12
+ "00000110", -- | ## | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 082 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111100", -- | ##### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01111100", -- | ##### | 07
+ "01101100", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 083 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00000110", -- | ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 084 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 085 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 086 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "00111100", -- | #### | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 087 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100011", -- | ## ##| 03
+ "01100011", -- | ## ##| 04
+ "01100011", -- | ## ##| 05
+ "01101011", -- | ## # ##| 06
+ "01101011", -- | ## # ##| 07
+ "01101011", -- | ## # ##| 08
+ "00110110", -- | ## ## | 09
+ "00110110", -- | ## ## | 10
+ "00110110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 088 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "00110100", -- | ## # | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00101100", -- | # ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 089 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "00111100", -- | #### | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 090 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "00000110", -- | ## | 04
+ "00000110", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 091 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00110000", -- | ## | 04
+ "00110000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00110000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00110000", -- | ## | 11
+ "00110000", -- | ## | 12
+ "00110000", -- | ## | 13
+ "00111100", -- | #### | 14
+ "00000000", -- | | 15
+ -- ASCII 092 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "00110000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00000110", -- | ## | 11
+ "00000110", -- | ## | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 093 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00001100", -- | ## | 04
+ "00001100", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00001100", -- | ## | 11
+ "00001100", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00111100", -- | #### | 14
+ "00000000", -- | | 15
+ -- ASCII 094 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 095 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "11111111", -- |########| 14
+ "00000000", -- | | 15
+ -- ASCII 096 ---------------
+ "00000000", -- | | 00
+ "00111000", -- | ### | 01
+ "00011000", -- | ## | 02
+ "00001100", -- | ## | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 097 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 098 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 099 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 100 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000110", -- | ## | 03
+ "00000110", -- | ## | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 101 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 102 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011110", -- | #### | 03
+ "00110000", -- | ## | 04
+ "00110000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "01111110", -- | ###### | 07
+ "00110000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00110000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 103 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000110", -- | ## | 12
+ "00000110", -- | ## | 13
+ "01111100", -- | ##### | 14
+ "00000000", -- | | 15
+ -- ASCII 104 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 105 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00011000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 106 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00001100", -- | ## | 02
+ "00001100", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00001100", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00001100", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00001100", -- | ## | 10
+ "00001100", -- | ## | 11
+ "00001100", -- | ## | 12
+ "00001100", -- | ## | 13
+ "01111000", -- | #### | 14
+ "00000000", -- | | 15
+ -- ASCII 107 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01101100", -- | ## ## | 07
+ "01111000", -- | #### | 08
+ "01101100", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 108 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111000", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 109 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01111110", -- | ###### | 05
+ "01101011", -- | ## # ##| 06
+ "01101011", -- | ## # ##| 07
+ "01101011", -- | ## # ##| 08
+ "01101011", -- | ## # ##| 09
+ "01101011", -- | ## # ##| 10
+ "01100011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 110 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 111 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 112 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "01100000", -- | ## | 12
+ "01100000", -- | ## | 13
+ "01100000", -- | ## | 14
+ "00000000", -- | | 15
+ -- ASCII 113 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000110", -- | ## | 12
+ "00000110", -- | ## | 13
+ "00000110", -- | ## | 14
+ "00000000", -- | | 15
+ -- ASCII 114 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01101110", -- | ## ### | 06
+ "01110000", -- | ### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 115 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111110", -- | ##### | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "00111100", -- | #### | 08
+ "00000110", -- | ## | 09
+ "00000110", -- | ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 116 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110000", -- | ## | 03
+ "00110000", -- | ## | 04
+ "01111110", -- | ###### | 05
+ "00110000", -- | ## | 06
+ "00110000", -- | ## | 07
+ "00110000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00110000", -- | ## | 10
+ "00011110", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 117 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 118 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "00111100", -- | #### | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 119 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100011", -- | ## ##| 05
+ "01101011", -- | ## # ##| 06
+ "01101011", -- | ## # ##| 07
+ "01101011", -- | ## # ##| 08
+ "01101011", -- | ## # ##| 09
+ "00110110", -- | ## ## | 10
+ "00110110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 120 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "00111100", -- | #### | 07
+ "00011000", -- | ## | 08
+ "00111100", -- | #### | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 121 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "11110000", -- |#### | 14
+ "00000000", -- | | 15
+ -- ASCII 122 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01111110", -- | ###### | 05
+ "00000110", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 123 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001100", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00110000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "00110000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 124 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00011000", -- | ## | 14
+ "00000000", -- | | 15
+ -- ASCII 125 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00001100", -- | ## | 07
+ "00000110", -- | ## | 08
+ "00001100", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00110000", -- | ## | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 126 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01110001", -- | ### #| 03
+ "11011011", -- |## ## ##| 04
+ "10001110", -- |# ### | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 127 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 128 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 129 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 130 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 131 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 132 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 133 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 134 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 135 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 136 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 137 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 138 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 139 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 140 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 141 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 142 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 143 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 144 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 145 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001100", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011100", -- | ### | 05
+ "00011100", -- | ### | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 146 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011100", -- | ### | 03
+ "00011100", -- | ### | 04
+ "00001100", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 147 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 148 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 149 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 150 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 151 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 152 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 153 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 154 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 155 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 156 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 157 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 158 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 159 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01111110", -- | ###### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "01111110", -- | ###### | 08
+ "01111110", -- | ###### | 09
+ "01111110", -- | ###### | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 160 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 161 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00000000", -- | | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00111100", -- | #### | 12
+ "00111100", -- | #### | 13
+ "00011000", -- | ## | 14
+ "00000000", -- | | 15
+ -- ASCII 162 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "00111100", -- | #### | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 163 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "11111100", -- |###### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "11000000", -- |## | 10
+ "11111110", -- |####### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 164 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "01100110", -- | ## ## | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "00111100", -- | #### | 08
+ "01100110", -- | ## ## | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 165 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "00111100", -- | #### | 06
+ "01111110", -- | ###### | 07
+ "00011000", -- | ## | 08
+ "01111110", -- | ###### | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 166 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00011000", -- | ## | 12
+ "00011000", -- | ## | 13
+ "00011000", -- | ## | 14
+ "00000000", -- | | 15
+ -- ASCII 167 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100000", -- | ## | 05
+ "00111000", -- | ### | 06
+ "00111100", -- | #### | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "00111100", -- | #### | 10
+ "00011100", -- | ### | 11
+ "00000110", -- | ## | 12
+ "01100110", -- | ## ## | 13
+ "00111100", -- | #### | 14
+ "00000000", -- | | 15
+ -- ASCII 168 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 169 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "11000011", -- |## ##| 04
+ "10011001", -- |# ## #| 05
+ "10100101", -- |# # # #| 06
+ "10100001", -- |# # #| 07
+ "10100101", -- |# # # #| 08
+ "10011001", -- |# ## #| 09
+ "11000011", -- |## ##| 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 170 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00000110", -- | ## | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "00111110", -- | ##### | 07
+ "00000000", -- | | 08
+ "01111110", -- | ###### | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 171 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00110011", -- | ## ##| 07
+ "01100110", -- | ## ## | 08
+ "11001100", -- |## ## | 09
+ "01100110", -- | ## ## | 10
+ "00110011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 172 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "01111110", -- | ###### | 07
+ "00000110", -- | ## | 08
+ "00000110", -- | ## | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 173 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "01111110", -- | ###### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 174 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "11000011", -- |## ##| 04
+ "10111001", -- |# ### #| 05
+ "10100101", -- |# # # #| 06
+ "10100101", -- |# # # #| 07
+ "10111001", -- |# ### #| 08
+ "10100101", -- |# # # #| 09
+ "11000011", -- |## ##| 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 175 ---------------
+ "11111111", -- |########| 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 176 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "00111100", -- | #### | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 177 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "01111110", -- | ###### | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00000000", -- | | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 178 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111000", -- | ### | 03
+ "00001100", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00110000", -- | ## | 06
+ "00111100", -- | #### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 179 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111000", -- | ### | 03
+ "00001100", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00001100", -- | ## | 06
+ "00111000", -- | ### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 180 ---------------
+ "00000000", -- | | 00
+ "00011100", -- | ### | 01
+ "00011000", -- | ## | 02
+ "00110000", -- | ## | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 181 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111011", -- | #### ##| 11
+ "01100000", -- | ## | 12
+ "01100000", -- | ## | 13
+ "11000000", -- |## | 14
+ "00000000", -- | | 15
+ -- ASCII 182 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011111", -- | #####| 03
+ "00111110", -- | ##### | 04
+ "01111110", -- | ###### | 05
+ "01111110", -- | ###### | 06
+ "01111110", -- | ###### | 07
+ "00111110", -- | ##### | 08
+ "00011110", -- | #### | 09
+ "00000110", -- | ## | 10
+ "00000110", -- | ## | 11
+ "00000110", -- | ## | 12
+ "00000110", -- | ## | 13
+ "00000110", -- | ## | 14
+ "00000000", -- | | 15
+ -- ASCII 183 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00011100", -- | ### | 06
+ "00011100", -- | ### | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 184 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00111000", -- | ### | 14
+ "00000000", -- | | 15
+ -- ASCII 185 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111000", -- | ### | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 186 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "00111100", -- | #### | 07
+ "00000000", -- | | 08
+ "01111110", -- | ###### | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 187 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "11001100", -- |## ## | 07
+ "01100110", -- | ## ## | 08
+ "00110011", -- | ## ##| 09
+ "01100110", -- | ## ## | 10
+ "11001100", -- |## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 188 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100000", -- | ## | 02
+ "11100000", -- |### | 03
+ "01100011", -- | ## ##| 04
+ "01100110", -- | ## ## | 05
+ "01101100", -- | ## ## | 06
+ "00011000", -- | ## | 07
+ "00110111", -- | ## ###| 08
+ "01101111", -- | ## ####| 09
+ "11011011", -- |## ## ##| 10
+ "00011111", -- | #####| 11
+ "00000011", -- | ##| 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 189 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100000", -- | ## | 02
+ "11100000", -- |### | 03
+ "01100011", -- | ## ##| 04
+ "01100110", -- | ## ## | 05
+ "01101100", -- | ## ## | 06
+ "00011000", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100011", -- | ## ##| 09
+ "11000110", -- |## ## | 10
+ "00001100", -- | ## | 11
+ "00001111", -- | ####| 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 190 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "11100000", -- |### | 02
+ "00110000", -- | ## | 03
+ "01100011", -- | ## ##| 04
+ "00110110", -- | ## ## | 05
+ "11101100", -- |### ## | 06
+ "00011000", -- | ## | 07
+ "00110111", -- | ## ###| 08
+ "01101111", -- | ## ####| 09
+ "11011011", -- |## ## ##| 10
+ "00011111", -- | #####| 11
+ "00000011", -- | ##| 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 191 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00000000", -- | | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00110000", -- | ## | 11
+ "01100110", -- | ## ## | 12
+ "01100110", -- | ## ## | 13
+ "00111100", -- | #### | 14
+ "00000000", -- | | 15
+ -- ASCII 192 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 193 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 194 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 195 ---------------
+ "00111011", -- | ### ##| 00
+ "01101110", -- | ## ### | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 196 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 197 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00111100", -- | #### | 02
+ "00011000", -- | ## | 03
+ "00111100", -- | #### | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 198 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00001111", -- | ####| 03
+ "00011100", -- | ### | 04
+ "00111100", -- | #### | 05
+ "01101100", -- | ## ## | 06
+ "01101111", -- | ## ####| 07
+ "01111100", -- | ##### | 08
+ "01101100", -- | ## ## | 09
+ "01101100", -- | ## ## | 10
+ "01101111", -- | ## ####| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 199 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100000", -- | ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00111000", -- | ### | 14
+ "00000000", -- | | 15
+ -- ASCII 200 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 201 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 202 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 203 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "01111110", -- | ###### | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01100000", -- | ## | 06
+ "01111100", -- | ##### | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 204 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 205 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 206 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 207 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 208 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01111000", -- | #### | 03
+ "01101100", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "11110110", -- |#### ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01101100", -- | ## ## | 10
+ "01111000", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 209 ---------------
+ "00111011", -- | ### ##| 00
+ "01101110", -- | ## ### | 01
+ "00000000", -- | | 02
+ "01100011", -- | ## ##| 03
+ "01100011", -- | ## ##| 04
+ "01110011", -- | ### ##| 05
+ "01111011", -- | #### ##| 06
+ "01101111", -- | ## ####| 07
+ "01100111", -- | ## ###| 08
+ "01100011", -- | ## ##| 09
+ "01100011", -- | ## ##| 10
+ "01100011", -- | ## ##| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 210 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 211 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 212 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 213 ---------------
+ "00111011", -- | ### ##| 00
+ "01101110", -- | ## ### | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 214 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "00111100", -- | #### | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 215 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "01000010", -- | # # | 04
+ "01100110", -- | ## ## | 05
+ "00111100", -- | #### | 06
+ "00011000", -- | ## | 07
+ "00111100", -- | #### | 08
+ "01100110", -- | ## ## | 09
+ "01000010", -- | # # | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 216 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111110", -- | ##### | 03
+ "01100110", -- | ## ## | 04
+ "01101110", -- | ## ### | 05
+ "01101110", -- | ## ### | 06
+ "01111110", -- | ###### | 07
+ "01110110", -- | ### ## | 08
+ "01110110", -- | ### ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 217 ---------------
+ "00110000", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 218 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 219 ---------------
+ "00111100", -- | #### | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 220 ---------------
+ "01100110", -- | ## ## | 00
+ "01100110", -- | ## ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 221 ---------------
+ "00001100", -- | ## | 00
+ "00011000", -- | ## | 01
+ "00000000", -- | | 02
+ "01100110", -- | ## ## | 03
+ "01100110", -- | ## ## | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "00111100", -- | #### | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00011000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 222 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01111100", -- | ##### | 09
+ "01100000", -- | ## | 10
+ "01100000", -- | ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 223 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00111000", -- | ### | 03
+ "01101100", -- | ## ## | 04
+ "01101100", -- | ## ## | 05
+ "01101100", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01101100", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 224 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 225 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 226 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 227 ---------------
+ "00000000", -- | | 00
+ "01110001", -- | ### #| 01
+ "11011011", -- |## ## ##| 02
+ "10001110", -- |# ### | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 228 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 229 ---------------
+ "00000000", -- | | 00
+ "00111100", -- | #### | 01
+ "01100110", -- | ## ## | 02
+ "00111100", -- | #### | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "00000110", -- | ## | 06
+ "00000110", -- | ## | 07
+ "00111110", -- | ##### | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 230 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "01101110", -- | ## ### | 05
+ "00011011", -- | ## ##| 06
+ "00011011", -- | ## ##| 07
+ "01111111", -- | #######| 08
+ "11011000", -- |## ## | 09
+ "11011000", -- |## ## | 10
+ "01110111", -- | ### ###| 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 231 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100000", -- | ## | 07
+ "01100000", -- | ## | 08
+ "01100000", -- | ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00011000", -- | ## | 12
+ "00001100", -- | ## | 13
+ "00111000", -- | ### | 14
+ "00000000", -- | | 15
+ -- ASCII 232 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 233 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 234 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 235 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01111110", -- | ###### | 08
+ "01100000", -- | ## | 09
+ "01100000", -- | ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 236 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 237 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 238 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 239 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01111000", -- | #### | 05
+ "00011000", -- | ## | 06
+ "00011000", -- | ## | 07
+ "00011000", -- | ## | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "01111110", -- | ###### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 240 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00110110", -- | ## ## | 03
+ "00011000", -- | ## | 04
+ "01101100", -- | ## ## | 05
+ "00011110", -- | #### | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 241 ---------------
+ "00000000", -- | | 00
+ "01110001", -- | ### #| 01
+ "11011011", -- |## ## ##| 02
+ "10001110", -- |# ### | 03
+ "00000000", -- | | 04
+ "01111100", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01100110", -- | ## ## | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 242 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 243 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 244 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 245 ---------------
+ "00000000", -- | | 00
+ "01110001", -- | ### #| 01
+ "11011011", -- |## ## ##| 02
+ "10001110", -- |# ### | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 246 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "00111100", -- | #### | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 247 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00011000", -- | ## | 04
+ "00011000", -- | ## | 05
+ "00000000", -- | | 06
+ "01111110", -- | ###### | 07
+ "00000000", -- | | 08
+ "00011000", -- | ## | 09
+ "00011000", -- | ## | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 248 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00111110", -- | ##### | 05
+ "01100110", -- | ## ## | 06
+ "01101110", -- | ## ### | 07
+ "01111110", -- | ###### | 08
+ "01110110", -- | ### ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 249 ---------------
+ "00000000", -- | | 00
+ "01110000", -- | ### | 01
+ "00110000", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 250 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 251 ---------------
+ "00000000", -- | | 00
+ "00011000", -- | ## | 01
+ "00111100", -- | #### | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 252 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111110", -- | ##### | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 253 ---------------
+ "00000000", -- | | 00
+ "00001110", -- | ### | 01
+ "00001100", -- | ## | 02
+ "00011000", -- | ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "11110000", -- |#### | 14
+ "00000000", -- | | 15
+ -- ASCII 254 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "01100000", -- | ## | 03
+ "01100000", -- | ## | 04
+ "01100000", -- | ## | 05
+ "01111100", -- | ##### | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "01111100", -- | ##### | 11
+ "01100000", -- | ## | 12
+ "01100000", -- | ## | 13
+ "01100000", -- | ## | 14
+ "00000000", -- | | 15
+ -- ASCII 255 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "01100110", -- | ## ## | 02
+ "01100110", -- | ## ## | 03
+ "00000000", -- | | 04
+ "01100110", -- | ## ## | 05
+ "01100110", -- | ## ## | 06
+ "01100110", -- | ## ## | 07
+ "01100110", -- | ## ## | 08
+ "01100110", -- | ## ## | 09
+ "01100110", -- | ## ## | 10
+ "00111100", -- | #### | 11
+ "00001100", -- | ## | 12
+ "00011000", -- | ## | 13
+ "11110000", -- |#### | 14
+ "00000000", -- | | 15
+ -- ASCII 256 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 257 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 258 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 259 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 260 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 261 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 262 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 263 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 264 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 265 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 266 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 267 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 268 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 269 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 270 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 271 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 272 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 273 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 274 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 275 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 276 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 277 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 278 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 279 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 280 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 281 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 282 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 283 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 284 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 285 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 286 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "00000000", -- | | 12
+ "00000000", -- | | 13
+ "00000000", -- | | 14
+ "00000000", -- | | 15
+ -- ASCII 287 ---------------
+ "00000000", -- | | 00
+ "00000000", -- | | 01
+ "00000000", -- | | 02
+ "00000000", -- | | 03
+ "00000000", -- | | 04
+ "00000000", -- | | 05
+ "00000000", -- | | 06
+ "00000000", -- | | 07
+ "00000000", -- | | 08
+ "00000000", -- | | 09
+ "00000000", -- | | 10
+ "00000000", -- | | 11
+ "11111111", -- |########| 12
+ "11111111", -- |########| 13
+ "11111111", -- |########| 14
+ "00000000" -- | | 15
+ );
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+
+end RTL;
+
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd
new file mode 100644
index 0000000..9b32d16
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd
@@ -0,0 +1,4351 @@
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port
+ (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(8 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(8 downto 0);
+ constant ROM : ROM_ARRAY :=
+ (
+ -- ASCII 032 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 033 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "001111000", -- | #### | 04
+ "001111000", -- | #### | 05
+ "001111000", -- | #### | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000000000", -- | | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 034 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 035 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001101100", -- | ## ## | 03
+ "001101100", -- | ## ## | 04
+ "011111110", -- | ####### | 05
+ "001101100", -- | ## ## | 06
+ "001101100", -- | ## ## | 07
+ "001101100", -- | ## ## | 08
+ "011111110", -- | ####### | 09
+ "001101100", -- | ## ## | 10
+ "001101100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 036 ---------------
+ "000000000", -- | | 00
+ "000110000", -- | ## | 01
+ "000110000", -- | ## | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011000000", -- | ## | 05
+ "001100000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000011000", -- | ## | 08
+ "000001100", -- | ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000110000", -- | ## | 12
+ "000110000", -- | ## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 037 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011100000", -- | ### | 02
+ "110110000", -- |## ## | 03
+ "110110100", -- |## ## # | 04
+ "011101100", -- | ### ## | 05
+ "000011000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "001100000", -- | ## | 08
+ "011011100", -- | ## ### | 09
+ "010110110", -- | # ## ## | 10
+ "000110110", -- | ## ## | 11
+ "000011100", -- | ### | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 038 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "111111110", -- |######## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 039 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 040 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000011000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "001100000", -- | ## | 06
+ "001100000", -- | ## | 07
+ "001100000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "001100000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000110000", -- | ## | 12
+ "000011000", -- | ## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 041 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001100000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000011000", -- | ## | 06
+ "000011000", -- | ## | 07
+ "000011000", -- | ## | 08
+ "000011000", -- | ## | 09
+ "000011000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000110000", -- | ## | 12
+ "001100000", -- | ## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 042 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001101100", -- | ## ## | 05
+ "000111000", -- | ### | 06
+ "011111110", -- | ####### | 07
+ "000111000", -- | ### | 08
+ "001101100", -- | ## ## | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 043 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "011111100", -- | ###### | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 044 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000111000", -- | ### | 10
+ "000111000", -- | ### | 11
+ "000011000", -- | ## | 12
+ "000110000", -- | ## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 045 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "011111100", -- | ###### | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 046 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000111000", -- | ### | 10
+ "000111000", -- | ### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 047 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000001100", -- | ## | 03
+ "000001100", -- | ## | 04
+ "000011000", -- | ## | 05
+ "000011000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "001100000", -- | ## | 10
+ "011000000", -- | ## | 11
+ "011000000", -- | ## | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 048 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000111100", -- | #### | 03
+ "001100110", -- | ## ## | 04
+ "001101110", -- | ## ### | 05
+ "001101110", -- | ## ### | 06
+ "001100110", -- | ## ## | 07
+ "001110110", -- | ### ## | 08
+ "001110110", -- | ### ## | 09
+ "001100110", -- | ## ## | 10
+ "000111100", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 049 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000011000", -- | ## | 03
+ "000111000", -- | ### | 04
+ "011111000", -- | ##### | 05
+ "000011000", -- | ## | 06
+ "000011000", -- | ## | 07
+ "000011000", -- | ## | 08
+ "000011000", -- | ## | 09
+ "000011000", -- | ## | 10
+ "000011000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 050 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "000001100", -- | ## | 06
+ "000011000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 051 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "000001100", -- | ## | 06
+ "000111000", -- | ### | 07
+ "000001100", -- | ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 052 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001100000", -- | ## | 03
+ "001100000", -- | ## | 04
+ "001101100", -- | ## ## | 05
+ "001101100", -- | ## ## | 06
+ "001101100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011111110", -- | ####### | 09
+ "000001100", -- | ## | 10
+ "000001100", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 053 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "011111000", -- | ##### | 07
+ "000001100", -- | ## | 08
+ "000001100", -- | ## | 09
+ "000011000", -- | ## | 10
+ "011110000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 054 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000111000", -- | ### | 03
+ "000110000", -- | ## | 04
+ "001100000", -- | ## | 05
+ "011111000", -- | ##### | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 055 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "000001100", -- | ## | 04
+ "000011000", -- | ## | 05
+ "000011000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "001100000", -- | ## | 10
+ "001100000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 056 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011101100", -- | ### ## | 06
+ "001111000", -- | #### | 07
+ "011011100", -- | ## ### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 057 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "001111100", -- | ##### | 08
+ "000011000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "001110000", -- | ### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 058 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000111000", -- | ### | 05
+ "000111000", -- | ### | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000111000", -- | ### | 10
+ "000111000", -- | ### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 059 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000111000", -- | ### | 05
+ "000111000", -- | ### | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000111000", -- | ### | 10
+ "000111000", -- | ### | 11
+ "000011000", -- | ## | 12
+ "000110000", -- | ## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 060 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000001100", -- | ## | 03
+ "000011000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "001100000", -- | ## | 06
+ "011000000", -- | ## | 07
+ "001100000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000011000", -- | ## | 10
+ "000001100", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 061 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "011111100", -- | ###### | 06
+ "000000000", -- | | 07
+ "011111100", -- | ###### | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 062 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000000", -- | ## | 03
+ "001100000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000011000", -- | ## | 06
+ "000001100", -- | ## | 07
+ "000011000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "001100000", -- | ## | 10
+ "011000000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 063 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "000011000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000000000", -- | | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 064 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "110000110", -- |## ## | 04
+ "110000110", -- |## ## | 05
+ "110011110", -- |## #### | 06
+ "110110110", -- |## ## ## | 07
+ "110110110", -- |## ## ## | 08
+ "110011110", -- |## #### | 09
+ "110000000", -- |## | 10
+ "011111110", -- | ####### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 065 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "001111000", -- | #### | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 066 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111000", -- | ##### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011111000", -- | ##### | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011111000", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 067 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011000000", -- | ## | 06
+ "011000000", -- | ## | 07
+ "011000000", -- | ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 068 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011110000", -- | #### | 03
+ "011011000", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011011000", -- | ## ## | 10
+ "011110000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 069 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "011111000", -- | ##### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 070 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "011111000", -- | ##### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011000000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 071 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011000000", -- | ## | 06
+ "011000000", -- | ## | 07
+ "011011100", -- | ## ### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 072 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011111100", -- | ###### | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 073 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 074 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000001100", -- | ## | 03
+ "000001100", -- | ## | 04
+ "000001100", -- | ## | 05
+ "000001100", -- | ## | 06
+ "000001100", -- | ## | 07
+ "000001100", -- | ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 075 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011011000", -- | ## ## | 05
+ "011011000", -- | ## ## | 06
+ "011110000", -- | #### | 07
+ "011011000", -- | ## ## | 08
+ "011011000", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 076 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000000", -- | ## | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "011000000", -- | ## | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 077 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000110", -- | ## ## | 03
+ "011000110", -- | ## ## | 04
+ "011101110", -- | ### ### | 05
+ "011010110", -- | ## # ## | 06
+ "011010110", -- | ## # ## | 07
+ "011010110", -- | ## # ## | 08
+ "011000110", -- | ## ## | 09
+ "011000110", -- | ## ## | 10
+ "011000110", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 078 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000110", -- | ## ## | 03
+ "011000110", -- | ## ## | 04
+ "011100110", -- | ### ## | 05
+ "011110110", -- | #### ## | 06
+ "011011110", -- | ## #### | 07
+ "011001110", -- | ## ### | 08
+ "011000110", -- | ## ## | 09
+ "011000110", -- | ## ## | 10
+ "011000110", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 079 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 080 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111000", -- | ##### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011111000", -- | ##### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011000000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 081 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000011000", -- | ## | 12
+ "000001100", -- | ## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 082 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111000", -- | ##### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011111000", -- | ##### | 07
+ "011011000", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 083 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011000000", -- | ## | 05
+ "001100000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000011000", -- | ## | 08
+ "000001100", -- | ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 084 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 085 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 086 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "001111000", -- | #### | 10
+ "000110000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 087 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000110", -- | ## ## | 03
+ "011000110", -- | ## ## | 04
+ "011000110", -- | ## ## | 05
+ "011010110", -- | ## # ## | 06
+ "011010110", -- | ## # ## | 07
+ "011010110", -- | ## # ## | 08
+ "001101100", -- | ## ## | 09
+ "001101100", -- | ## ## | 10
+ "001101100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 088 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "001101000", -- | ## # | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "001011000", -- | # ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 089 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "001111000", -- | #### | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 090 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "000001100", -- | ## | 04
+ "000001100", -- | ## | 05
+ "000011000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "001100000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 091 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "001100000", -- | ## | 04
+ "001100000", -- | ## | 05
+ "001100000", -- | ## | 06
+ "001100000", -- | ## | 07
+ "001100000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "001100000", -- | ## | 10
+ "001100000", -- | ## | 11
+ "001100000", -- | ## | 12
+ "001100000", -- | ## | 13
+ "001111000", -- | #### | 14
+ "000000000", -- | | 15
+ -- ASCII 092 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000000", -- | ## | 03
+ "011000000", -- | ## | 04
+ "001100000", -- | ## | 05
+ "001100000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000011000", -- | ## | 09
+ "000011000", -- | ## | 10
+ "000001100", -- | ## | 11
+ "000001100", -- | ## | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 093 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "000011000", -- | ## | 04
+ "000011000", -- | ## | 05
+ "000011000", -- | ## | 06
+ "000011000", -- | ## | 07
+ "000011000", -- | ## | 08
+ "000011000", -- | ## | 09
+ "000011000", -- | ## | 10
+ "000011000", -- | ## | 11
+ "000011000", -- | ## | 12
+ "000011000", -- | ## | 13
+ "001111000", -- | #### | 14
+ "000000000", -- | | 15
+ -- ASCII 094 ---------------
+ "000000000", -- | | 00
+ "000110000", -- | ## | 01
+ "001111000", -- | #### | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 095 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "111111110", -- |######## | 14
+ "000000000", -- | | 15
+ -- ASCII 096 ---------------
+ "000000000", -- | | 00
+ "001110000", -- | ### | 01
+ "000110000", -- | ## | 02
+ "000011000", -- | ## | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 097 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "000001100", -- | ## | 06
+ "000001100", -- | ## | 07
+ "001111100", -- | ##### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 098 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000000", -- | ## | 03
+ "011000000", -- | ## | 04
+ "011111000", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011111000", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 099 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011000000", -- | ## | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 100 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000001100", -- | ## | 03
+ "000001100", -- | ## | 04
+ "001111100", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 101 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 102 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000111100", -- | #### | 03
+ "001100000", -- | ## | 04
+ "001100000", -- | ## | 05
+ "001100000", -- | ## | 06
+ "011111100", -- | ###### | 07
+ "001100000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "001100000", -- | ## | 10
+ "001100000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 103 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111100", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000001100", -- | ## | 12
+ "000001100", -- | ## | 13
+ "011111000", -- | ##### | 14
+ "000000000", -- | | 15
+ -- ASCII 104 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000000", -- | ## | 03
+ "011000000", -- | ## | 04
+ "011111000", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 105 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000110000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "011110000", -- | #### | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 106 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000011000", -- | ## | 02
+ "000011000", -- | ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "000011000", -- | ## | 06
+ "000011000", -- | ## | 07
+ "000011000", -- | ## | 08
+ "000011000", -- | ## | 09
+ "000011000", -- | ## | 10
+ "000011000", -- | ## | 11
+ "000011000", -- | ## | 12
+ "000011000", -- | ## | 13
+ "011110000", -- | #### | 14
+ "000000000", -- | | 15
+ -- ASCII 107 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000000", -- | ## | 03
+ "011000000", -- | ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011011000", -- | ## ## | 07
+ "011110000", -- | #### | 08
+ "011011000", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 108 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011110000", -- | #### | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 109 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011111100", -- | ###### | 05
+ "011010110", -- | ## # ## | 06
+ "011010110", -- | ## # ## | 07
+ "011010110", -- | ## # ## | 08
+ "011010110", -- | ## # ## | 09
+ "011010110", -- | ## # ## | 10
+ "011000110", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 110 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011111000", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 111 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 112 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011111000", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011111000", -- | ##### | 11
+ "011000000", -- | ## | 12
+ "011000000", -- | ## | 13
+ "011000000", -- | ## | 14
+ "000000000", -- | | 15
+ -- ASCII 113 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111100", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000001100", -- | ## | 12
+ "000001100", -- | ## | 13
+ "000001100", -- | ## | 14
+ "000000000", -- | | 15
+ -- ASCII 114 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011011100", -- | ## ### | 06
+ "011100000", -- | ### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011000000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 115 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111100", -- | ##### | 05
+ "011000000", -- | ## | 06
+ "011000000", -- | ## | 07
+ "001111000", -- | #### | 08
+ "000001100", -- | ## | 09
+ "000001100", -- | ## | 10
+ "011111000", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 116 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001100000", -- | ## | 03
+ "001100000", -- | ## | 04
+ "011111100", -- | ###### | 05
+ "001100000", -- | ## | 06
+ "001100000", -- | ## | 07
+ "001100000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "001100000", -- | ## | 10
+ "000111100", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 117 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 118 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "001111000", -- | #### | 10
+ "000110000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 119 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011000110", -- | ## ## | 05
+ "011010110", -- | ## # ## | 06
+ "011010110", -- | ## # ## | 07
+ "011010110", -- | ## # ## | 08
+ "011010110", -- | ## # ## | 09
+ "001101100", -- | ## ## | 10
+ "001101100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 120 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "001111000", -- | #### | 07
+ "000110000", -- | ## | 08
+ "001111000", -- | #### | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 121 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000011000", -- | ## | 12
+ "000110000", -- | ## | 13
+ "111100000", -- |#### | 14
+ "000000000", -- | | 15
+ -- ASCII 122 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011111100", -- | ###### | 05
+ "000001100", -- | ## | 06
+ "000011000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 123 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000011000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "001100000", -- | ## | 07
+ "011000000", -- | ## | 08
+ "001100000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000110000", -- | ## | 12
+ "000011000", -- | ## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 124 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000110000", -- | ## | 12
+ "000110000", -- | ## | 13
+ "000110000", -- | ## | 14
+ "000000000", -- | | 15
+ -- ASCII 125 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001100000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000011000", -- | ## | 07
+ "000001100", -- | ## | 08
+ "000011000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000110000", -- | ## | 12
+ "001100000", -- | ## | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 126 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011100010", -- | ### # | 03
+ "110110110", -- |## ## ## | 04
+ "100011100", -- |# ### | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 127 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 128 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 129 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 130 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 131 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 132 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 133 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 134 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 135 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 136 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 137 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 138 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 139 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 140 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 141 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 142 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 143 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 144 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 145 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000011000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "000111000", -- | ### | 05
+ "000111000", -- | ### | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 146 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000111000", -- | ### | 03
+ "000111000", -- | ### | 04
+ "000011000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 147 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 148 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 149 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 150 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 151 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 152 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 153 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 154 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 155 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 156 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 157 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 158 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 159 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011111100", -- | ###### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "011111100", -- | ###### | 08
+ "011111100", -- | ###### | 09
+ "011111100", -- | ###### | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 160 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 161 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000000000", -- | | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "001111000", -- | #### | 12
+ "001111000", -- | #### | 13
+ "000110000", -- | ## | 14
+ "000000000", -- | | 15
+ -- ASCII 162 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011000000", -- | ## | 07
+ "011000000", -- | ## | 08
+ "011001100", -- | ## ## | 09
+ "001111000", -- | #### | 10
+ "000110000", -- | ## | 11
+ "000110000", -- | ## | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 163 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "111111000", -- |###### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "110000000", -- |## | 10
+ "111111100", -- |####### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 164 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "011001100", -- | ## ## | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "001111000", -- | #### | 08
+ "011001100", -- | ## ## | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 165 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "001111000", -- | #### | 06
+ "011111100", -- | ###### | 07
+ "000110000", -- | ## | 08
+ "011111100", -- | ###### | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 166 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000110000", -- | ## | 12
+ "000110000", -- | ## | 13
+ "000110000", -- | ## | 14
+ "000000000", -- | | 15
+ -- ASCII 167 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011000000", -- | ## | 05
+ "001110000", -- | ### | 06
+ "001111000", -- | #### | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "001111000", -- | #### | 10
+ "000111000", -- | ### | 11
+ "000001100", -- | ## | 12
+ "011001100", -- | ## ## | 13
+ "001111000", -- | #### | 14
+ "000000000", -- | | 15
+ -- ASCII 168 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011001100", -- | ## ## | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 169 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "110000110", -- |## ## | 04
+ "100110010", -- |# ## # | 05
+ "101001010", -- |# # # # | 06
+ "101000010", -- |# # # | 07
+ "101001010", -- |# # # # | 08
+ "100110010", -- |# ## # | 09
+ "110000110", -- |## ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 170 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "000001100", -- | ## | 04
+ "001111100", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "001111100", -- | ##### | 07
+ "000000000", -- | | 08
+ "011111100", -- | ###### | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 171 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "001100110", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "110011000", -- |## ## | 09
+ "011001100", -- | ## ## | 10
+ "001100110", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 172 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "011111100", -- | ###### | 07
+ "000001100", -- | ## | 08
+ "000001100", -- | ## | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 173 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "011111100", -- | ###### | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 174 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "110000110", -- |## ## | 04
+ "101110010", -- |# ### # | 05
+ "101001010", -- |# # # # | 06
+ "101001010", -- |# # # # | 07
+ "101110010", -- |# ### # | 08
+ "101001010", -- |# # # # | 09
+ "110000110", -- |## ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 175 ---------------
+ "111111110", -- |######## | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 176 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "001111000", -- | #### | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "001111000", -- | #### | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 177 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "011111100", -- | ###### | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000000000", -- | | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 178 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001110000", -- | ### | 03
+ "000011000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "001100000", -- | ## | 06
+ "001111000", -- | #### | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 179 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001110000", -- | ### | 03
+ "000011000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000011000", -- | ## | 06
+ "001110000", -- | ### | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 180 ---------------
+ "000000000", -- | | 00
+ "000111000", -- | ### | 01
+ "000110000", -- | ## | 02
+ "001100000", -- | ## | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 181 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011110110", -- | #### ## | 11
+ "011000000", -- | ## | 12
+ "011000000", -- | ## | 13
+ "110000000", -- |## | 14
+ "000000000", -- | | 15
+ -- ASCII 182 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000111110", -- | ##### | 03
+ "001111100", -- | ##### | 04
+ "011111100", -- | ###### | 05
+ "011111100", -- | ###### | 06
+ "011111100", -- | ###### | 07
+ "001111100", -- | ##### | 08
+ "000111100", -- | #### | 09
+ "000001100", -- | ## | 10
+ "000001100", -- | ## | 11
+ "000001100", -- | ## | 12
+ "000001100", -- | ## | 13
+ "000001100", -- | ## | 14
+ "000000000", -- | | 15
+ -- ASCII 183 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000111000", -- | ### | 06
+ "000111000", -- | ### | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 184 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "000000000", -- | | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000110000", -- | ## | 12
+ "000011000", -- | ## | 13
+ "001110000", -- | ### | 14
+ "000000000", -- | | 15
+ -- ASCII 185 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "001110000", -- | ### | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000000000", -- | | 08
+ "000000000", -- | | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 186 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "001111000", -- | #### | 07
+ "000000000", -- | | 08
+ "011111100", -- | ###### | 09
+ "000000000", -- | | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 187 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000000000", -- | | 06
+ "110011000", -- |## ## | 07
+ "011001100", -- | ## ## | 08
+ "001100110", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "110011000", -- |## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 188 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011000000", -- | ## | 02
+ "111000000", -- |### | 03
+ "011000110", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011011000", -- | ## ## | 06
+ "000110000", -- | ## | 07
+ "001101110", -- | ## ### | 08
+ "011011110", -- | ## #### | 09
+ "110110110", -- |## ## ## | 10
+ "000111110", -- | ##### | 11
+ "000000110", -- | ## | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 189 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011000000", -- | ## | 02
+ "111000000", -- |### | 03
+ "011000110", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011011000", -- | ## ## | 06
+ "000110000", -- | ## | 07
+ "001111100", -- | ##### | 08
+ "011000110", -- | ## ## | 09
+ "110001100", -- |## ## | 10
+ "000011000", -- | ## | 11
+ "000011110", -- | #### | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 190 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "111000000", -- |### | 02
+ "001100000", -- | ## | 03
+ "011000110", -- | ## ## | 04
+ "001101100", -- | ## ## | 05
+ "111011000", -- |### ## | 06
+ "000110000", -- | ## | 07
+ "001101110", -- | ## ### | 08
+ "011011110", -- | ## #### | 09
+ "110110110", -- |## ## ## | 10
+ "000111110", -- | ##### | 11
+ "000000110", -- | ## | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 191 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "000000000", -- | | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000000000", -- | | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "001100000", -- | ## | 11
+ "011001100", -- | ## ## | 12
+ "011001100", -- | ## ## | 13
+ "001111000", -- | #### | 14
+ "000000000", -- | | 15
+ -- ASCII 192 ---------------
+ "001100000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "001111000", -- | #### | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 193 ---------------
+ "000011000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "001111000", -- | #### | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 194 ---------------
+ "001111000", -- | #### | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "001111000", -- | #### | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 195 ---------------
+ "001110110", -- | ### ## | 00
+ "011011100", -- | ## ### | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "001111000", -- | #### | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 196 ---------------
+ "011001100", -- | ## ## | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "000110000", -- | ## | 03
+ "001111000", -- | #### | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 197 ---------------
+ "001111000", -- | #### | 00
+ "011001100", -- | ## ## | 01
+ "001111000", -- | #### | 02
+ "000110000", -- | ## | 03
+ "001111000", -- | #### | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 198 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000011110", -- | #### | 03
+ "000111000", -- | ### | 04
+ "001111000", -- | #### | 05
+ "011011000", -- | ## ## | 06
+ "011011110", -- | ## #### | 07
+ "011111000", -- | ##### | 08
+ "011011000", -- | ## ## | 09
+ "011011000", -- | ## ## | 10
+ "011011110", -- | ## #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 199 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011000000", -- | ## | 06
+ "011000000", -- | ## | 07
+ "011000000", -- | ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000110000", -- | ## | 12
+ "000011000", -- | ## | 13
+ "001110000", -- | ### | 14
+ "000000000", -- | | 15
+ -- ASCII 200 ---------------
+ "001100000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "011111000", -- | ##### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 201 ---------------
+ "000011000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "011111000", -- | ##### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 202 ---------------
+ "001111000", -- | #### | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "011111000", -- | ##### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 203 ---------------
+ "011001100", -- | ## ## | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "011111100", -- | ###### | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011000000", -- | ## | 06
+ "011111000", -- | ##### | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 204 ---------------
+ "001100000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 205 ---------------
+ "000011000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 206 ---------------
+ "001111000", -- | #### | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 207 ---------------
+ "011001100", -- | ## ## | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 208 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011110000", -- | #### | 03
+ "011011000", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "111101100", -- |#### ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011011000", -- | ## ## | 10
+ "011110000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 209 ---------------
+ "001110110", -- | ### ## | 00
+ "011011100", -- | ## ### | 01
+ "000000000", -- | | 02
+ "011000110", -- | ## ## | 03
+ "011000110", -- | ## ## | 04
+ "011100110", -- | ### ## | 05
+ "011110110", -- | #### ## | 06
+ "011011110", -- | ## #### | 07
+ "011001110", -- | ## ### | 08
+ "011000110", -- | ## ## | 09
+ "011000110", -- | ## ## | 10
+ "011000110", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 210 ---------------
+ "001100000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 211 ---------------
+ "000011000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 212 ---------------
+ "001111000", -- | #### | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 213 ---------------
+ "001110110", -- | ### ## | 00
+ "011011100", -- | ## ### | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 214 ---------------
+ "011001100", -- | ## ## | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "001111000", -- | #### | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 215 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "010000100", -- | # # | 04
+ "011001100", -- | ## ## | 05
+ "001111000", -- | #### | 06
+ "000110000", -- | ## | 07
+ "001111000", -- | #### | 08
+ "011001100", -- | ## ## | 09
+ "010000100", -- | # # | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 216 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001111100", -- | ##### | 03
+ "011001100", -- | ## ## | 04
+ "011011100", -- | ## ### | 05
+ "011011100", -- | ## ### | 06
+ "011111100", -- | ###### | 07
+ "011101100", -- | ### ## | 08
+ "011101100", -- | ### ## | 09
+ "011001100", -- | ## ## | 10
+ "011111000", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 217 ---------------
+ "001100000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 218 ---------------
+ "000011000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 219 ---------------
+ "001111000", -- | #### | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 220 ---------------
+ "011001100", -- | ## ## | 00
+ "011001100", -- | ## ## | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 221 ---------------
+ "000011000", -- | ## | 00
+ "000110000", -- | ## | 01
+ "000000000", -- | | 02
+ "011001100", -- | ## ## | 03
+ "011001100", -- | ## ## | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "001111000", -- | #### | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "000110000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 222 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000000", -- | ## | 03
+ "011000000", -- | ## | 04
+ "011111000", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011111000", -- | ##### | 09
+ "011000000", -- | ## | 10
+ "011000000", -- | ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 223 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001110000", -- | ### | 03
+ "011011000", -- | ## ## | 04
+ "011011000", -- | ## ## | 05
+ "011011000", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011011000", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 224 ---------------
+ "000000000", -- | | 00
+ "011100000", -- | ### | 01
+ "001100000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "000001100", -- | ## | 06
+ "000001100", -- | ## | 07
+ "001111100", -- | ##### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 225 ---------------
+ "000000000", -- | | 00
+ "000011100", -- | ### | 01
+ "000011000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "000001100", -- | ## | 06
+ "000001100", -- | ## | 07
+ "001111100", -- | ##### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 226 ---------------
+ "000000000", -- | | 00
+ "000110000", -- | ## | 01
+ "001111000", -- | #### | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "000001100", -- | ## | 06
+ "000001100", -- | ## | 07
+ "001111100", -- | ##### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 227 ---------------
+ "000000000", -- | | 00
+ "011100010", -- | ### # | 01
+ "110110110", -- |## ## ## | 02
+ "100011100", -- |# ### | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "000001100", -- | ## | 06
+ "000001100", -- | ## | 07
+ "001111100", -- | ##### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 228 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011001100", -- | ## ## | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "000001100", -- | ## | 06
+ "000001100", -- | ## | 07
+ "001111100", -- | ##### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 229 ---------------
+ "000000000", -- | | 00
+ "001111000", -- | #### | 01
+ "011001100", -- | ## ## | 02
+ "001111000", -- | #### | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "000001100", -- | ## | 06
+ "000001100", -- | ## | 07
+ "001111100", -- | ##### | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 230 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "011011100", -- | ## ### | 05
+ "000110110", -- | ## ## | 06
+ "000110110", -- | ## ## | 07
+ "011111110", -- | ####### | 08
+ "110110000", -- |## ## | 09
+ "110110000", -- |## ## | 10
+ "011101110", -- | ### ### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 231 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011000000", -- | ## | 07
+ "011000000", -- | ## | 08
+ "011000000", -- | ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000110000", -- | ## | 12
+ "000011000", -- | ## | 13
+ "001110000", -- | ### | 14
+ "000000000", -- | | 15
+ -- ASCII 232 ---------------
+ "000000000", -- | | 00
+ "011100000", -- | ### | 01
+ "001100000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 233 ---------------
+ "000000000", -- | | 00
+ "000011100", -- | ### | 01
+ "000011000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 234 ---------------
+ "000000000", -- | | 00
+ "000110000", -- | ## | 01
+ "001111000", -- | #### | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 235 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011001100", -- | ## ## | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011111100", -- | ###### | 08
+ "011000000", -- | ## | 09
+ "011000000", -- | ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 236 ---------------
+ "000000000", -- | | 00
+ "011100000", -- | ### | 01
+ "001100000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "011110000", -- | #### | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 237 ---------------
+ "000000000", -- | | 00
+ "000011100", -- | ### | 01
+ "000011000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "011110000", -- | #### | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 238 ---------------
+ "000000000", -- | | 00
+ "000110000", -- | ## | 01
+ "001111000", -- | #### | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "011110000", -- | #### | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 239 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011001100", -- | ## ## | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "011110000", -- | #### | 05
+ "000110000", -- | ## | 06
+ "000110000", -- | ## | 07
+ "000110000", -- | ## | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "011111100", -- | ###### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 240 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "001101100", -- | ## ## | 03
+ "000110000", -- | ## | 04
+ "011011000", -- | ## ## | 05
+ "000111100", -- | #### | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 241 ---------------
+ "000000000", -- | | 00
+ "011100010", -- | ### # | 01
+ "110110110", -- |## ## ## | 02
+ "100011100", -- |# ### | 03
+ "000000000", -- | | 04
+ "011111000", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011001100", -- | ## ## | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 242 ---------------
+ "000000000", -- | | 00
+ "011100000", -- | ### | 01
+ "001100000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 243 ---------------
+ "000000000", -- | | 00
+ "000011100", -- | ### | 01
+ "000011000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 244 ---------------
+ "000000000", -- | | 00
+ "000110000", -- | ## | 01
+ "001111000", -- | #### | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 245 ---------------
+ "000000000", -- | | 00
+ "011100010", -- | ### # | 01
+ "110110110", -- |## ## ## | 02
+ "100011100", -- |# ### | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 246 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011001100", -- | ## ## | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "001111000", -- | #### | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 247 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000110000", -- | ## | 04
+ "000110000", -- | ## | 05
+ "000000000", -- | | 06
+ "011111100", -- | ###### | 07
+ "000000000", -- | | 08
+ "000110000", -- | ## | 09
+ "000110000", -- | ## | 10
+ "000000000", -- | | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 248 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "000000000", -- | | 03
+ "000000000", -- | | 04
+ "001111100", -- | ##### | 05
+ "011001100", -- | ## ## | 06
+ "011011100", -- | ## ### | 07
+ "011111100", -- | ###### | 08
+ "011101100", -- | ### ## | 09
+ "011001100", -- | ## ## | 10
+ "011111000", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 249 ---------------
+ "000000000", -- | | 00
+ "011100000", -- | ### | 01
+ "001100000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 250 ---------------
+ "000000000", -- | | 00
+ "000011100", -- | ### | 01
+ "000011000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 251 ---------------
+ "000000000", -- | | 00
+ "000110000", -- | ## | 01
+ "001111000", -- | #### | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 252 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011001100", -- | ## ## | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111100", -- | ##### | 11
+ "000000000", -- | | 12
+ "000000000", -- | | 13
+ "000000000", -- | | 14
+ "000000000", -- | | 15
+ -- ASCII 253 ---------------
+ "000000000", -- | | 00
+ "000011100", -- | ### | 01
+ "000011000", -- | ## | 02
+ "000110000", -- | ## | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000011000", -- | ## | 12
+ "000110000", -- | ## | 13
+ "111100000", -- |#### | 14
+ "000000000", -- | | 15
+ -- ASCII 254 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "000000000", -- | | 02
+ "011000000", -- | ## | 03
+ "011000000", -- | ## | 04
+ "011000000", -- | ## | 05
+ "011111000", -- | ##### | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "011111000", -- | ##### | 11
+ "011000000", -- | ## | 12
+ "011000000", -- | ## | 13
+ "011000000", -- | ## | 14
+ "000000000", -- | | 15
+ -- ASCII 255 ---------------
+ "000000000", -- | | 00
+ "000000000", -- | | 01
+ "011001100", -- | ## ## | 02
+ "011001100", -- | ## ## | 03
+ "000000000", -- | | 04
+ "011001100", -- | ## ## | 05
+ "011001100", -- | ## ## | 06
+ "011001100", -- | ## ## | 07
+ "011001100", -- | ## ## | 08
+ "011001100", -- | ## ## | 09
+ "011001100", -- | ## ## | 10
+ "001111000", -- | #### | 11
+ "000011000", -- | ## | 12
+ "000110000", -- | ## | 13
+ "111100000", -- |#### | 14
+ "000000000", -- | | 15
+ -- Padding ---------------
+ "000000000", -- Padded
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+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000", -- Padded
+ "000000000" -- Padded
+ );
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+
+end RTL;
+
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd
new file mode 100644
index 0000000..d50d36f
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd
@@ -0,0 +1,4382 @@
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port
+ (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(15 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(15 downto 0);
+ constant ROM : ROM_ARRAY :=
+ (
+ -- ASCII 032 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 033 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0000000000000000", -- | | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 034 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100110000000000", -- |## ## | 03
+ "1100110000000000", -- |## ## | 04
+ "1100110000000000", -- |## ## | 05
+ "1100110000000000", -- |## ## | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 035 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011011000000000", -- | ## ## | 03
+ "0011011000000000", -- | ## ## | 04
+ "0111111100000000", -- | ####### | 05
+ "0011011000000000", -- | ## ## | 06
+ "0011011000000000", -- | ## ## | 07
+ "0110110000000000", -- | ## ## | 08
+ "0110110000000000", -- | ## ## | 09
+ "1111111000000000", -- |####### | 10
+ "0110110000000000", -- | ## ## | 11
+ "0110110000000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 036 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001100000000000", -- | ## | 03
+ "0011110000000000", -- | #### | 04
+ "0110011000000000", -- | ## ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110000000000000", -- | ## | 07
+ "0011110000000000", -- | #### | 08
+ "0000011000000000", -- | ## | 09
+ "0000011000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0001100000000000", -- | ## | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 037 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111000001100000", -- | ### ## | 03
+ "1101100011000000", -- |## ## ## | 04
+ "1101100110000000", -- |## ## ## | 05
+ "1101101100000000", -- |## ## ## | 06
+ "0111011000000000", -- | ### ## | 07
+ "0000110111000000", -- | ## ### | 08
+ "0001101101100000", -- | ## ## ## | 09
+ "0011001101100000", -- | ## ## ## | 10
+ "0110001101100000", -- | ## ## ## | 11
+ "1100000111000000", -- |## ### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 038 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "1111000000000000", -- |#### | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 039 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 040 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "0011000000000000", -- | ## | 15
+ -- ASCII 041 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100000000000000", -- |## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "1100000000000000", -- |## | 15
+ -- ASCII 042 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011000000000000", -- | ## | 03
+ "1111110000000000", -- |###### | 04
+ "0011000000000000", -- | ## | 05
+ "0111100000000000", -- | #### | 06
+ "0100100000000000", -- | # # | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 043 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0001100000000000", -- | ## | 05
+ "0001100000000000", -- | ## | 06
+ "0001100000000000", -- | ## | 07
+ "0111111000000000", -- | ###### | 08
+ "0001100000000000", -- | ## | 09
+ "0001100000000000", -- | ## | 10
+ "0001100000000000", -- | ## | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 044 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "1100000000000000", -- |## | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 045 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "1111000000000000", -- |#### | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 046 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 047 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011000000000000", -- | ## | 03
+ "0011000000000000", -- | ## | 04
+ "0011000000000000", -- | ## | 05
+ "0011000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "1100000000000000", -- |## | 11
+ "1100000000000000", -- |## | 12
+ "1100000000000000", -- |## | 13
+ "1100000000000000", -- |## | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 048 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0110011000000000", -- | ## ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 049 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001100000000000", -- | ## | 03
+ "0111100000000000", -- | #### | 04
+ "0001100000000000", -- | ## | 05
+ "0001100000000000", -- | ## | 06
+ "0001100000000000", -- | ## | 07
+ "0001100000000000", -- | ## | 08
+ "0001100000000000", -- | ## | 09
+ "0001100000000000", -- | ## | 10
+ "0001100000000000", -- | ## | 11
+ "0001100000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 050 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0110011000000000", -- | ## ## | 05
+ "0000011000000000", -- | ## | 06
+ "0000110000000000", -- | ## | 07
+ "0001100000000000", -- | ## | 08
+ "0011000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0111111000000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 051 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000011000000000", -- | ## | 05
+ "0000011000000000", -- | ## | 06
+ "0001110000000000", -- | ### | 07
+ "0000011000000000", -- | ## | 08
+ "0000011000000000", -- | ## | 09
+ "0000011000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 052 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000011000000000", -- | ## | 03
+ "0000111000000000", -- | ### | 04
+ "0001111000000000", -- | #### | 05
+ "0001111000000000", -- | #### | 06
+ "0011011000000000", -- | ## ## | 07
+ "0011011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "0000011000000000", -- | ## | 11
+ "0000011000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 053 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111000000000", -- | ###### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0111110000000000", -- | ##### | 07
+ "0110011000000000", -- | ## ## | 08
+ "0000011000000000", -- | ## | 09
+ "0000011000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 054 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0111110000000000", -- | ##### | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 055 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111000000000", -- | ###### | 03
+ "0000011000000000", -- | ## | 04
+ "0000110000000000", -- | ## | 05
+ "0000110000000000", -- | ## | 06
+ "0001100000000000", -- | ## | 07
+ "0001100000000000", -- | ## | 08
+ "0001100000000000", -- | ## | 09
+ "0011000000000000", -- | ## | 10
+ "0011000000000000", -- | ## | 11
+ "0011000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 056 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0110011000000000", -- | ## ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "0011110000000000", -- | #### | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 057 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0110011000000000", -- | ## ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0011111000000000", -- | ##### | 08
+ "0000011000000000", -- | ## | 09
+ "0000011000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 058 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 059 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "1100000000000000", -- |## | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 060 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000011000000000", -- | ## | 04
+ "0000110000000000", -- | ## | 05
+ "0001100000000000", -- | ## | 06
+ "0011000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0011000000000000", -- | ## | 09
+ "0001100000000000", -- | ## | 10
+ "0000110000000000", -- | ## | 11
+ "0000011000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 061 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0111111000000000", -- | ###### | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0111111000000000", -- | ###### | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 062 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0011000000000000", -- | ## | 05
+ "0001100000000000", -- | ## | 06
+ "0000110000000000", -- | ## | 07
+ "0000011000000000", -- | ## | 08
+ "0000110000000000", -- | ## | 09
+ "0001100000000000", -- | ## | 10
+ "0011000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 063 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0110011000000000", -- | ## ## | 05
+ "0000011000000000", -- | ## | 06
+ "0000110000000000", -- | ## | 07
+ "0001100000000000", -- | ## | 08
+ "0001100000000000", -- | ## | 09
+ "0000000000000000", -- | | 10
+ "0001100000000000", -- | ## | 11
+ "0001100000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 064 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000011110000000", -- | #### | 02
+ "0001110011100000", -- | ### ### | 03
+ "0011000000110000", -- | ## ## | 04
+ "0011001110110000", -- | ## ### ## | 05
+ "0110011011011000", -- | ## ## ## ## | 06
+ "0110011011011000", -- | ## ## ## ## | 07
+ "0110110011011000", -- | ## ## ## ## | 08
+ "0110110110011000", -- | ## ## ## ## | 09
+ "0110110110011000", -- | ## ## ## ## | 10
+ "0011011011110000", -- | ## ## #### | 11
+ "0011000000000000", -- | ## | 12
+ "0001110001110000", -- | ### ### | 13
+ "0000011111000000", -- | ##### | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 065 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001100000000000", -- | ## | 03
+ "0001100000000000", -- | ## | 04
+ "0011110000000000", -- | #### | 05
+ "0011110000000000", -- | #### | 06
+ "0010010000000000", -- | # # | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "1100001100000000", -- |## ## | 11
+ "1100001100000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 066 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0111111100000000", -- | ####### | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0110000110000000", -- | ## ## | 11
+ "0111111100000000", -- | ####### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 067 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000100000000", -- | ## # | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000100000000", -- | ## # | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 068 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111000000000", -- | ###### | 03
+ "0110001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0110001100000000", -- | ## ## | 11
+ "0111111000000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 069 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0111111000000000", -- | ###### | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0111111100000000", -- | ####### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 070 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0111111000000000", -- | ###### | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 071 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001111100000000", -- | ##### | 03
+ "0011000110000000", -- | ## ## | 04
+ "0110000010000000", -- | ## # | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110011110000000", -- | ## #### | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011000110000000", -- | ## ## | 11
+ "0001111010000000", -- | #### # | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 072 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000110000000", -- | ## ## | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0111111110000000", -- | ######## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0110000110000000", -- | ## ## | 11
+ "0110000110000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 073 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 074 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000110000000000", -- | ## | 03
+ "0000110000000000", -- | ## | 04
+ "0000110000000000", -- | ## | 05
+ "0000110000000000", -- | ## | 06
+ "0000110000000000", -- | ## | 07
+ "0000110000000000", -- | ## | 08
+ "0000110000000000", -- | ## | 09
+ "1100110000000000", -- |## ## | 10
+ "1100110000000000", -- |## ## | 11
+ "0111100000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 075 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110001100000000", -- | ## ## | 03
+ "0110011000000000", -- | ## ## | 04
+ "0110110000000000", -- | ## ## | 05
+ "0111100000000000", -- | #### | 06
+ "0111000000000000", -- | ### | 07
+ "0111100000000000", -- | #### | 08
+ "0110110000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110001100000000", -- | ## ## | 11
+ "0110000110000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 076 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0111111100000000", -- | ####### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 077 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000001100000", -- | ## ## | 03
+ "0110000001100000", -- | ## ## | 04
+ "0111000011100000", -- | ### ### | 05
+ "0111000011100000", -- | ### ### | 06
+ "0111100111100000", -- | #### #### | 07
+ "0111100111100000", -- | #### #### | 08
+ "0110111101100000", -- | ## #### ## | 09
+ "0110111101100000", -- | ## #### ## | 10
+ "0110011001100000", -- | ## ## ## | 11
+ "0110011001100000", -- | ## ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 078 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000110000000", -- | ## ## | 03
+ "0111000110000000", -- | ### ## | 04
+ "0111100110000000", -- | #### ## | 05
+ "0111100110000000", -- | #### ## | 06
+ "0110110110000000", -- | ## ## ## | 07
+ "0110110110000000", -- | ## ## ## | 08
+ "0110011110000000", -- | ## #### | 09
+ "0110011110000000", -- | ## #### | 10
+ "0110001110000000", -- | ## ### | 11
+ "0110000110000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 079 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 080 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0111111100000000", -- | ####### | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 081 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110011110000000", -- | ## #### | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111110000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 082 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0111111100000000", -- | ####### | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0110000110000000", -- | ## ## | 11
+ "0110000011000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 083 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011111000000000", -- | ##### | 03
+ "0110001100000000", -- | ## ## | 04
+ "0110001100000000", -- | ## ## | 05
+ "0110000000000000", -- | ## | 06
+ "0011100000000000", -- | ### | 07
+ "0000111000000000", -- | ### | 08
+ "0000001100000000", -- | ## | 09
+ "0110001100000000", -- | ## ## | 10
+ "0110001100000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 084 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1111111100000000", -- |######## | 03
+ "0001100000000000", -- | ## | 04
+ "0001100000000000", -- | ## | 05
+ "0001100000000000", -- | ## | 06
+ "0001100000000000", -- | ## | 07
+ "0001100000000000", -- | ## | 08
+ "0001100000000000", -- | ## | 09
+ "0001100000000000", -- | ## | 10
+ "0001100000000000", -- | ## | 11
+ "0001100000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 085 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000110000000", -- | ## ## | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 086 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100001100000000", -- |## ## | 03
+ "1100001100000000", -- |## ## | 04
+ "0110011000000000", -- | ## ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0010010000000000", -- | # # | 08
+ "0011110000000000", -- | #### | 09
+ "0011110000000000", -- | #### | 10
+ "0001100000000000", -- | ## | 11
+ "0001100000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 087 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100001100001100", -- |## ## ## | 03
+ "1100001100001100", -- |## ## ## | 04
+ "1100001100001100", -- |## ## ## | 05
+ "0110011110011000", -- | ## #### ## | 06
+ "0110011110011000", -- | ## #### ## | 07
+ "0011010010110000", -- | ## # # ## | 08
+ "0011110011110000", -- | #### #### | 09
+ "0001100001100000", -- | ## ## | 10
+ "0001100001100000", -- | ## ## | 11
+ "0001100001100000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 088 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100000110000000", -- |## ## | 03
+ "1100000110000000", -- |## ## | 04
+ "0110001100000000", -- | ## ## | 05
+ "0011011000000000", -- | ## ## | 06
+ "0001110000000000", -- | ### | 07
+ "0001110000000000", -- | ### | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110001100000000", -- | ## ## | 10
+ "1100000110000000", -- |## ## | 11
+ "1100000110000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 089 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100000011000000", -- |## ## | 03
+ "1100000011000000", -- |## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0011001100000000", -- | ## ## | 06
+ "0001111000000000", -- | #### | 07
+ "0000110000000000", -- | ## | 08
+ "0000110000000000", -- | ## | 09
+ "0000110000000000", -- | ## | 10
+ "0000110000000000", -- | ## | 11
+ "0000110000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 090 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1111111110000000", -- |######### | 03
+ "0000000110000000", -- | ## | 04
+ "0000001100000000", -- | ## | 05
+ "0000011000000000", -- | ## | 06
+ "0000110000000000", -- | ## | 07
+ "0001100000000000", -- | ## | 08
+ "0011000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "1100000000000000", -- |## | 11
+ "1111111110000000", -- |######### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 091 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111000000000000", -- | ### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "0111000000000000", -- | ### | 15
+ -- ASCII 092 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100000000000000", -- |## | 03
+ "1100000000000000", -- |## | 04
+ "1100000000000000", -- |## | 05
+ "1100000000000000", -- |## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0011000000000000", -- | ## | 11
+ "0011000000000000", -- | ## | 12
+ "0011000000000000", -- | ## | 13
+ "0011000000000000", -- | ## | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 093 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1110000000000000", -- |### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "1110000000000000", -- |### | 15
+ -- ASCII 094 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0010000000000000", -- | # | 03
+ "0111000000000000", -- | ### | 04
+ "1101100000000000", -- |## ## | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 095 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "1111111100000000", -- |######## | 15
+ -- ASCII 096 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0111000000000000", -- | ### | 02
+ "0011000000000000", -- | ## | 03
+ "0001100000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 097 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0001111000000000", -- | #### | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 098 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0111110000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0111110000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 099 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 100 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000011000000000", -- | ## | 03
+ "0000011000000000", -- | ## | 04
+ "0000011000000000", -- | ## | 05
+ "0011111000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 101 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0111111000000000", -- | ###### | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 102 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "1111000000000000", -- |#### | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 103 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011111000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000011000000000", -- | ## | 13
+ "0110011000000000", -- | ## ## | 14
+ "0011110000000000", -- | #### | 15
+ -- ASCII 104 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0111110000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0110011000000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 105 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 106 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "1100000000000000", -- |## | 15
+ -- ASCII 107 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110110000000000", -- | ## ## | 07
+ "0111100000000000", -- | #### | 08
+ "0111000000000000", -- | ### | 09
+ "0111100000000000", -- | #### | 10
+ "0110110000000000", -- | ## ## | 11
+ "0110011000000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 108 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 109 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0111111111000000", -- | ######### | 06
+ "0110011001100000", -- | ## ## ## | 07
+ "0110011001100000", -- | ## ## ## | 08
+ "0110011001100000", -- | ## ## ## | 09
+ "0110011001100000", -- | ## ## ## | 10
+ "0110011001100000", -- | ## ## ## | 11
+ "0110011001100000", -- | ## ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 110 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0111110000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0110011000000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 111 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 112 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0111110000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0111110000000000", -- | ##### | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "0110000000000000", -- | ## | 15
+ -- ASCII 113 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011111000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000011000000000", -- | ## | 13
+ "0000011000000000", -- | ## | 14
+ "0000011000000000", -- | ## | 15
+ -- ASCII 114 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0111100000000000", -- | #### | 06
+ "0111000000000000", -- | ### | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 115 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110000000000000", -- | ## | 08
+ "0011110000000000", -- | #### | 09
+ "0000011000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 116 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "1111000000000000", -- |#### | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0011000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 117 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 118 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "1100001100000000", -- |## ## | 06
+ "1100001100000000", -- |## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0011110000000000", -- | #### | 10
+ "0001100000000000", -- | ## | 11
+ "0001100000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 119 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "1100000011000000", -- |## ## | 06
+ "1100110011000000", -- |## ## ## | 07
+ "0110110110000000", -- | ## ## ## | 08
+ "0110110110000000", -- | ## ## ## | 09
+ "0111111110000000", -- | ######## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0011001100000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 120 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "1100001100000000", -- |## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0011110000000000", -- | #### | 08
+ "0001100000000000", -- | ## | 09
+ "0011110000000000", -- | #### | 10
+ "0110011000000000", -- | ## ## | 11
+ "1100001100000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 121 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "1100001100000000", -- |## ## | 06
+ "1100001100000000", -- |## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0011110000000000", -- | #### | 10
+ "0011110000000000", -- | #### | 11
+ "0001100000000000", -- | ## | 12
+ "0001100000000000", -- | ## | 13
+ "0011000000000000", -- | ## | 14
+ "0110000000000000", -- | ## | 15
+ -- ASCII 122 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0111111000000000", -- | ###### | 06
+ "0000011000000000", -- | ## | 07
+ "0000110000000000", -- | ## | 08
+ "0001100000000000", -- | ## | 09
+ "0011000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0111111000000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 123 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001100000000000", -- | ## | 03
+ "0011000000000000", -- | ## | 04
+ "0011000000000000", -- | ## | 05
+ "0011000000000000", -- | ## | 06
+ "0011000000000000", -- | ## | 07
+ "0011000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0011000000000000", -- | ## | 10
+ "0011000000000000", -- | ## | 11
+ "0011000000000000", -- | ## | 12
+ "0011000000000000", -- | ## | 13
+ "0011000000000000", -- | ## | 14
+ "0001100000000000", -- | ## | 15
+ -- ASCII 124 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "0110000000000000", -- | ## | 15
+ -- ASCII 125 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100000000000000", -- |## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0011000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "1100000000000000", -- |## | 15
+ -- ASCII 126 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1110100000000000", -- |### # | 03
+ "1011100000000000", -- |# ### | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 127 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 128 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 129 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 130 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 131 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 132 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 133 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 134 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 135 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 136 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 137 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 138 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 139 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 140 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 141 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 142 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 143 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 144 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 145 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0011000000000000", -- | ## | 02
+ "0110000000000000", -- | ## | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 146 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0110000000000000", -- | ## | 02
+ "1100000000000000", -- |## | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 147 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 148 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 149 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 150 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 151 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 152 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 153 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 154 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 155 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 156 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 157 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 158 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 159 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 160 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 161 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 162 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000110000000000", -- | ## | 05
+ "0011110000000000", -- | #### | 06
+ "0110111000000000", -- | ## ### | 07
+ "0110100000000000", -- | ## # | 08
+ "0110100000000000", -- | ## # | 09
+ "0111000000000000", -- | ### | 10
+ "0111011000000000", -- | ### ## | 11
+ "0011110000000000", -- | #### | 12
+ "0011000000000000", -- | ## | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 163 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011100000000000", -- | ### | 03
+ "0110110000000000", -- | ## ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0011000000000000", -- | ## | 07
+ "0111100000000000", -- | #### | 08
+ "0011000000000000", -- | ## | 09
+ "0011000000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0111110000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 164 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110011000000000", -- | ## ## | 03
+ "0011110000000000", -- | #### | 04
+ "0010010000000000", -- | # # | 05
+ "0010010000000000", -- | # # | 06
+ "0011110000000000", -- | #### | 07
+ "0110011000000000", -- | ## ## | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 165 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1100001100000000", -- |## ## | 03
+ "1100001100000000", -- |## ## | 04
+ "0110011000000000", -- | ## ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "1111111100000000", -- |######## | 07
+ "0001100000000000", -- | ## | 08
+ "1111111100000000", -- |######## | 09
+ "0001100000000000", -- | ## | 10
+ "0001100000000000", -- | ## | 11
+ "0001100000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 166 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0000000000000000", -- | | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "0110000000000000", -- | ## | 15
+ -- ASCII 167 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0011100000000000", -- | ### | 05
+ "0011100000000000", -- | ### | 06
+ "0110110000000000", -- | ## ## | 07
+ "0011011000000000", -- | ## ## | 08
+ "0001110000000000", -- | ### | 09
+ "0001110000000000", -- | ### | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 168 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1101100000000000", -- |## ## | 03
+ "1101100000000000", -- |## ## | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 169 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011111100000000", -- | ###### | 03
+ "0110000110000000", -- | ## ## | 04
+ "1100110011000000", -- |## ## ## | 05
+ "1101001011000000", -- |## # # ## | 06
+ "1101000011000000", -- |## # ## | 07
+ "1101000011000000", -- |## # ## | 08
+ "1101001011000000", -- |## # # ## | 09
+ "1100110011000000", -- |## ## ## | 10
+ "0110000110000000", -- | ## ## | 11
+ "0011111100000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 170 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0010000000000000", -- | # | 03
+ "0001000000000000", -- | # | 04
+ "0011000000000000", -- | ## | 05
+ "0101000000000000", -- | # # | 06
+ "0011000000000000", -- | ## | 07
+ "0000000000000000", -- | | 08
+ "0111000000000000", -- | ### | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 171 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0011011000000000", -- | ## ## | 07
+ "0110110000000000", -- | ## ## | 08
+ "1101100000000000", -- |## ## | 09
+ "0110110000000000", -- | ## ## | 10
+ "0011011000000000", -- | ## ## | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 172 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0111111000000000", -- | ###### | 07
+ "0000011000000000", -- | ## | 08
+ "0000011000000000", -- | ## | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 173 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "1111000000000000", -- |#### | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 174 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011111100000000", -- | ###### | 03
+ "0110000110000000", -- | ## ## | 04
+ "1101110011000000", -- |## ### ## | 05
+ "1101001011000000", -- |## # # ## | 06
+ "1101001011000000", -- |## # # ## | 07
+ "1101110011000000", -- |## ### ## | 08
+ "1101010011000000", -- |## # # ## | 09
+ "1101001011000000", -- |## # # ## | 10
+ "0110000110000000", -- | ## ## | 11
+ "0011111100000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 175 ---------------
+ "0000000000000000", -- | | 00
+ "1111111100000000", -- |######## | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 176 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111000000000000", -- | ### | 03
+ "0101000000000000", -- | # # | 04
+ "0101000000000000", -- | # # | 05
+ "0111000000000000", -- | ### | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 177 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0001100000000000", -- | ## | 06
+ "0001100000000000", -- | ## | 07
+ "0111111000000000", -- | ###### | 08
+ "0001100000000000", -- | ## | 09
+ "0001100000000000", -- | ## | 10
+ "0000000000000000", -- | | 11
+ "0111111000000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 178 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "1011000000000000", -- |# ## | 04
+ "0011000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "1111000000000000", -- |#### | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 179 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "1011000000000000", -- |# ## | 04
+ "0110000000000000", -- | ## | 05
+ "1011000000000000", -- |# ## | 06
+ "0110000000000000", -- | ## | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 180 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0011100000000000", -- | ### | 02
+ "0011000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 181 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0110011000000000", -- | ## ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0111111100000000", -- | ####### | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "0110000000000000", -- | ## | 15
+ -- ASCII 182 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0111110000000000", -- | ##### | 04
+ "0111110000000000", -- | ##### | 05
+ "0111110000000000", -- | ##### | 06
+ "0111110000000000", -- | ##### | 07
+ "0011110000000000", -- | #### | 08
+ "0000110000000000", -- | ## | 09
+ "0000110000000000", -- | ## | 10
+ "0000110000000000", -- | ## | 11
+ "0000110000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 183 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 184 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0011000000000000", -- | ## | 13
+ "0001100000000000", -- | ## | 14
+ "0111000000000000", -- | ### | 15
+ -- ASCII 185 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "1110000000000000", -- |### | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 186 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111000000000000", -- | ### | 03
+ "0101000000000000", -- | # # | 04
+ "0101000000000000", -- | # # | 05
+ "0101000000000000", -- | # # | 06
+ "0111000000000000", -- | ### | 07
+ "0000000000000000", -- | | 08
+ "0111000000000000", -- | ### | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 187 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "1101100000000000", -- |## ## | 07
+ "0110110000000000", -- | ## ## | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110110000000000", -- | ## ## | 10
+ "1101100000000000", -- |## ## | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 188 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011000001100000", -- | ## ## | 03
+ "0111000011000000", -- | ### ## | 04
+ "0011000110000000", -- | ## ## | 05
+ "0011001100000000", -- | ## ## | 06
+ "0011011000000000", -- | ## ## | 07
+ "0000110011000000", -- | ## ## | 08
+ "0001100111000000", -- | ## ### | 09
+ "0011001101000000", -- | ## ## # | 10
+ "0110001111000000", -- | ## #### | 11
+ "1100000011000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 189 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011000001100000", -- | ## ## | 03
+ "0111000011000000", -- | ### ## | 04
+ "0011000110000000", -- | ## ## | 05
+ "0011001100000000", -- | ## ## | 06
+ "0011011000000000", -- | ## ## | 07
+ "0000110110000000", -- | ## ## | 08
+ "0001101011000000", -- | ## # ## | 09
+ "0011000011000000", -- | ## ## | 10
+ "0110000110000000", -- | ## ## | 11
+ "1100001111000000", -- |## #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 190 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011000001100000", -- | ## ## | 03
+ "0101100011000000", -- | # ## ## | 04
+ "0011000110000000", -- | ## ## | 05
+ "0101101100000000", -- | # ## ## | 06
+ "0011011000000000", -- | ## ## | 07
+ "0000110011000000", -- | ## ## | 08
+ "0001100111000000", -- | ## ### | 09
+ "0011001101000000", -- | ## ## # | 10
+ "0110001111000000", -- | ## #### | 11
+ "1100000011000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 191 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001100000000000", -- | ## | 03
+ "0001100000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0001100000000000", -- | ## | 06
+ "0001100000000000", -- | ## | 07
+ "0011000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 192 ---------------
+ "0011100000000000", -- | ### | 00
+ "0001100000000000", -- | ## | 01
+ "0000110000000000", -- | ## | 02
+ "0001100000000000", -- | ## | 03
+ "0001100000000000", -- | ## | 04
+ "0011110000000000", -- | #### | 05
+ "0011110000000000", -- | #### | 06
+ "0010010000000000", -- | # # | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "1100001100000000", -- |## ## | 11
+ "1100001100000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 193 ---------------
+ "0001110000000000", -- | ### | 00
+ "0001100000000000", -- | ## | 01
+ "0011000000000000", -- | ## | 02
+ "0001100000000000", -- | ## | 03
+ "0001100000000000", -- | ## | 04
+ "0011110000000000", -- | #### | 05
+ "0011110000000000", -- | #### | 06
+ "0010010000000000", -- | # # | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "1100001100000000", -- |## ## | 11
+ "1100001100000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 194 ---------------
+ "0001100000000000", -- | ## | 00
+ "0011110000000000", -- | #### | 01
+ "0110011000000000", -- | ## ## | 02
+ "0001100000000000", -- | ## | 03
+ "0001100000000000", -- | ## | 04
+ "0011110000000000", -- | #### | 05
+ "0011110000000000", -- | #### | 06
+ "0010010000000000", -- | # # | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "1100001100000000", -- |## ## | 11
+ "1100001100000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 195 ---------------
+ "0111101000000000", -- | #### # | 00
+ "0101111000000000", -- | # #### | 01
+ "0000000000000000", -- | | 02
+ "0001100000000000", -- | ## | 03
+ "0001100000000000", -- | ## | 04
+ "0011110000000000", -- | #### | 05
+ "0011110000000000", -- | #### | 06
+ "0010010000000000", -- | # # | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "1100001100000000", -- |## ## | 11
+ "1100001100000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 196 ---------------
+ "0110011000000000", -- | ## ## | 00
+ "0110011000000000", -- | ## ## | 01
+ "0000000000000000", -- | | 02
+ "0001100000000000", -- | ## | 03
+ "0001100000000000", -- | ## | 04
+ "0011110000000000", -- | #### | 05
+ "0011110000000000", -- | #### | 06
+ "0010010000000000", -- | # # | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "1100001100000000", -- |## ## | 11
+ "1100001100000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 197 ---------------
+ "0001100000000000", -- | ## | 00
+ "0011110000000000", -- | #### | 01
+ "0001100000000000", -- | ## | 02
+ "0000000000000000", -- | | 03
+ "0001100000000000", -- | ## | 04
+ "0001100000000000", -- | ## | 05
+ "0011110000000000", -- | #### | 06
+ "0010010000000000", -- | # # | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "1100001100000000", -- |## ## | 11
+ "1100001100000000", -- |## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 198 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001111111110000", -- | ######### | 03
+ "0001111000000000", -- | #### | 04
+ "0011011000000000", -- | ## ## | 05
+ "0011011000000000", -- | ## ## | 06
+ "0011011111100000", -- | ## ###### | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "1100011000000000", -- |## ## | 11
+ "1100011111110000", -- |## ####### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 199 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000100000000", -- | ## # | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000100000000", -- | ## # | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000110000000000", -- | ## | 13
+ "0000011000000000", -- | ## | 14
+ "0001110000000000", -- | ### | 15
+ -- ASCII 200 ---------------
+ "0001110000000000", -- | ### | 00
+ "0000110000000000", -- | ## | 01
+ "0000011000000000", -- | ## | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0111111000000000", -- | ###### | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0111111100000000", -- | ####### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 201 ---------------
+ "0000111000000000", -- | ### | 00
+ "0000110000000000", -- | ## | 01
+ "0001100000000000", -- | ## | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0111111000000000", -- | ###### | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0111111100000000", -- | ####### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 202 ---------------
+ "0000110000000000", -- | ## | 00
+ "0001111000000000", -- | #### | 01
+ "0011001100000000", -- | ## ## | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0111111000000000", -- | ###### | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0111111100000000", -- | ####### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 203 ---------------
+ "0011001100000000", -- | ## ## | 00
+ "0011001100000000", -- | ## ## | 01
+ "0000000000000000", -- | | 02
+ "0111111100000000", -- | ####### | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0111111000000000", -- | ###### | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0111111100000000", -- | ####### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 204 ---------------
+ "1100000000000000", -- |## | 00
+ "0110000000000000", -- | ## | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 205 ---------------
+ "0011000000000000", -- | ## | 00
+ "0110000000000000", -- | ## | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 206 ---------------
+ "0110000000000000", -- | ## | 00
+ "1001000000000000", -- |# # | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 207 ---------------
+ "1001000000000000", -- |# # | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 208 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111111000000000", -- | ###### | 03
+ "0110001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "1111100110000000", -- |##### ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0110001100000000", -- | ## ## | 11
+ "0111111000000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 209 ---------------
+ "0011110100000000", -- | #### # | 00
+ "0010111100000000", -- | # #### | 01
+ "0000000000000000", -- | | 02
+ "0110000110000000", -- | ## ## | 03
+ "0111000110000000", -- | ### ## | 04
+ "0111100110000000", -- | #### ## | 05
+ "0111100110000000", -- | #### ## | 06
+ "0110110110000000", -- | ## ## ## | 07
+ "0110110110000000", -- | ## ## ## | 08
+ "0110011110000000", -- | ## #### | 09
+ "0110011110000000", -- | ## #### | 10
+ "0110001110000000", -- | ## ### | 11
+ "0110000110000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 210 ---------------
+ "0001110000000000", -- | ### | 00
+ "0000110000000000", -- | ## | 01
+ "0000011000000000", -- | ## | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 211 ---------------
+ "0000111000000000", -- | ### | 00
+ "0000110000000000", -- | ## | 01
+ "0001100000000000", -- | ## | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 212 ---------------
+ "0000110000000000", -- | ## | 00
+ "0001111000000000", -- | #### | 01
+ "0011001100000000", -- | ## ## | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 213 ---------------
+ "0011110100000000", -- | #### # | 00
+ "0010111100000000", -- | # #### | 01
+ "0000000000000000", -- | | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 214 ---------------
+ "0011001100000000", -- | ## ## | 00
+ "0011001100000000", -- | ## ## | 01
+ "0000000000000000", -- | | 02
+ "0001111000000000", -- | #### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 215 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0110011000000000", -- | ## ## | 07
+ "0011110000000000", -- | #### | 08
+ "0001100000000000", -- | ## | 09
+ "0011110000000000", -- | #### | 10
+ "0110011000000000", -- | ## ## | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 216 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0001111110000000", -- | ###### | 03
+ "0011001100000000", -- | ## ## | 04
+ "0110001110000000", -- | ## ### | 05
+ "0110011110000000", -- | ## #### | 06
+ "0110110110000000", -- | ## ## ## | 07
+ "0110110110000000", -- | ## ## ## | 08
+ "0111100110000000", -- | #### ## | 09
+ "0111000110000000", -- | ### ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0111111000000000", -- | ###### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 217 ---------------
+ "0001110000000000", -- | ### | 00
+ "0000110000000000", -- | ## | 01
+ "0000011000000000", -- | ## | 02
+ "0110000110000000", -- | ## ## | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 218 ---------------
+ "0000111000000000", -- | ### | 00
+ "0000110000000000", -- | ## | 01
+ "0001100000000000", -- | ## | 02
+ "0110000110000000", -- | ## ## | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 219 ---------------
+ "0000110000000000", -- | ## | 00
+ "0001111000000000", -- | #### | 01
+ "0011001100000000", -- | ## ## | 02
+ "0000000000000000", -- | | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 220 ---------------
+ "0011001100000000", -- | ## ## | 00
+ "0011001100000000", -- | ## ## | 01
+ "0000000000000000", -- | | 02
+ "0110000110000000", -- | ## ## | 03
+ "0110000110000000", -- | ## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0110000110000000", -- | ## ## | 06
+ "0110000110000000", -- | ## ## | 07
+ "0110000110000000", -- | ## ## | 08
+ "0110000110000000", -- | ## ## | 09
+ "0110000110000000", -- | ## ## | 10
+ "0011001100000000", -- | ## ## | 11
+ "0001111000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 221 ---------------
+ "0000111000000000", -- | ### | 00
+ "0000110000000000", -- | ## | 01
+ "0001100000000000", -- | ## | 02
+ "1100000011000000", -- |## ## | 03
+ "1100000011000000", -- |## ## | 04
+ "0110000110000000", -- | ## ## | 05
+ "0011001100000000", -- | ## ## | 06
+ "0001111000000000", -- | #### | 07
+ "0000110000000000", -- | ## | 08
+ "0000110000000000", -- | ## | 09
+ "0000110000000000", -- | ## | 10
+ "0000110000000000", -- | ## | 11
+ "0000110000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 222 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0111111000000000", -- | ###### | 05
+ "0110001100000000", -- | ## ## | 06
+ "0110001100000000", -- | ## ## | 07
+ "0110001100000000", -- | ## ## | 08
+ "0110001100000000", -- | ## ## | 09
+ "0111111000000000", -- | ###### | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 223 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0110011000000000", -- | ## ## | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110110000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0110110000000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 224 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0011100000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0000110000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0001111000000000", -- | #### | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 225 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001110000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0011000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0001111000000000", -- | #### | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 226 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001100000000000", -- | ## | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0001111000000000", -- | #### | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 227 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111101000000000", -- | #### # | 03
+ "0101111000000000", -- | # #### | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0001111000000000", -- | #### | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 228 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110011000000000", -- | ## ## | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0001111000000000", -- | #### | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 229 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001100000000000", -- | ## | 02
+ "0011110000000000", -- | #### | 03
+ "0001100000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0001111000000000", -- | #### | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 230 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011111111000000", -- | ######## | 06
+ "0110011001100000", -- | ## ## ## | 07
+ "0001111111100000", -- | ######## | 08
+ "0011011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011001100000", -- | ## ## ## | 11
+ "0011111111000000", -- | ######## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 231 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0001100000000000", -- | ## | 13
+ "0000110000000000", -- | ## | 14
+ "0011100000000000", -- | ### | 15
+ -- ASCII 232 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0011100000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0000110000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0111111000000000", -- | ###### | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 233 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001110000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0011000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0111111000000000", -- | ###### | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 234 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001100000000000", -- | ## | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0111111000000000", -- | ###### | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 235 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110011000000000", -- | ## ## | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0111111000000000", -- | ###### | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 236 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "1110000000000000", -- |### | 02
+ "0110000000000000", -- | ## | 03
+ "0011000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 237 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0111000000000000", -- | ### | 02
+ "0110000000000000", -- | ## | 03
+ "1100000000000000", -- |## | 04
+ "0000000000000000", -- | | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 238 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0110000000000000", -- | ## | 02
+ "1111000000000000", -- |#### | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 239 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "1001000000000000", -- |# # | 03
+ "1001000000000000", -- |# # | 04
+ "0000000000000000", -- | | 05
+ "0110000000000000", -- | ## | 06
+ "0110000000000000", -- | ## | 07
+ "0110000000000000", -- | ## | 08
+ "0110000000000000", -- | ## | 09
+ "0110000000000000", -- | ## | 10
+ "0110000000000000", -- | ## | 11
+ "0110000000000000", -- | ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 240 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111011000000000", -- | ### ## | 03
+ "0001100000000000", -- | ## | 04
+ "0110110000000000", -- | ## ## | 05
+ "0000110000000000", -- | ## | 06
+ "0011111000000000", -- | ##### | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 241 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111101000000000", -- | #### # | 03
+ "0101111000000000", -- | # #### | 04
+ "0000000000000000", -- | | 05
+ "0111110000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0110011000000000", -- | ## ## | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 242 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0011100000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0000110000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 243 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001110000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0011000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 244 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001100000000000", -- | ## | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 245 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0111101000000000", -- | #### # | 03
+ "0101111000000000", -- | # #### | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 246 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110011000000000", -- | ## ## | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "0011110000000000", -- | #### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011110000000000", -- | #### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 247 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0011000000000000", -- | ## | 05
+ "0011000000000000", -- | ## | 06
+ "0000000000000000", -- | | 07
+ "0111100000000000", -- | #### | 08
+ "0000000000000000", -- | | 09
+ "0011000000000000", -- | ## | 10
+ "0011000000000000", -- | ## | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 248 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0011111000000000", -- | ##### | 06
+ "0110111000000000", -- | ## ### | 07
+ "0110111000000000", -- | ## ### | 08
+ "0110011000000000", -- | ## ## | 09
+ "0111011000000000", -- | ### ## | 10
+ "0111011000000000", -- | ### ## | 11
+ "0111110000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 249 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0011100000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0000110000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 250 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001110000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0011000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 251 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001100000000000", -- | ## | 02
+ "0011110000000000", -- | #### | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 252 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110011000000000", -- | ## ## | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "0110011000000000", -- | ## ## | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0011111000000000", -- | ##### | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 253 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0001110000000000", -- | ### | 02
+ "0001100000000000", -- | ## | 03
+ "0011000000000000", -- | ## | 04
+ "0000000000000000", -- | | 05
+ "1100001100000000", -- |## ## | 06
+ "1100001100000000", -- |## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0011110000000000", -- | #### | 10
+ "0011110000000000", -- | #### | 11
+ "0001100000000000", -- | ## | 12
+ "0001100000000000", -- | ## | 13
+ "0011000000000000", -- | ## | 14
+ "0110000000000000", -- | ## | 15
+ -- ASCII 254 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110000000000000", -- | ## | 03
+ "0110000000000000", -- | ## | 04
+ "0110000000000000", -- | ## | 05
+ "0111110000000000", -- | ##### | 06
+ "0110011000000000", -- | ## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0110011000000000", -- | ## ## | 10
+ "0110011000000000", -- | ## ## | 11
+ "0111110000000000", -- | ##### | 12
+ "0110000000000000", -- | ## | 13
+ "0110000000000000", -- | ## | 14
+ "0110000000000000", -- | ## | 15
+ -- ASCII 255 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0110011000000000", -- | ## ## | 03
+ "0110011000000000", -- | ## ## | 04
+ "0000000000000000", -- | | 05
+ "1100001100000000", -- |## ## | 06
+ "1100001100000000", -- |## ## | 07
+ "0110011000000000", -- | ## ## | 08
+ "0110011000000000", -- | ## ## | 09
+ "0011110000000000", -- | #### | 10
+ "0011110000000000", -- | #### | 11
+ "0001100000000000", -- | ## | 12
+ "0001100000000000", -- | ## | 13
+ "0011000000000000", -- | ## | 14
+ "0110000000000000", -- | ## | 15
+ -- ASCII 256 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 257 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 258 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 259 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 260 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 261 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 262 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 263 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 264 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 265 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 266 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 267 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 268 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 269 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 270 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 271 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 272 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 273 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 274 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 275 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 276 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 277 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 278 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 279 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 280 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 281 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 282 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 283 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 284 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 285 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 286 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000", -- | | 15
+ -- ASCII 287 ---------------
+ "0000000000000000", -- | | 00
+ "0000000000000000", -- | | 01
+ "0000000000000000", -- | | 02
+ "0000000000000000", -- | | 03
+ "0000000000000000", -- | | 04
+ "0000000000000000", -- | | 05
+ "0000000000000000", -- | | 06
+ "0000000000000000", -- | | 07
+ "0000000000000000", -- | | 08
+ "0000000000000000", -- | | 09
+ "0000000000000000", -- | | 10
+ "0000000000000000", -- | | 11
+ "0000000000000000", -- | | 12
+ "0000000000000000", -- | | 13
+ "0000000000000000", -- | | 14
+ "0000000000000000" -- | | 15
+ );
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+
+end RTL;
+
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd b/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd
new file mode 100644
index 0000000..f5bbcc5
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd
@@ -0,0 +1,539 @@
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity char_rom is
+ port (
+ CLK : in std_logic;
+ ADDR : in unsigned(11 downto 0);
+ DATA : out unsigned(7 downto 0)
+ );
+end;
+
+architecture RTL of char_rom is
+
+
+ type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
+ constant ROM : ROM_ARRAY := (
+ x"00",x"00",x"01",x"03",x"07",x"0F",x"0F",x"0F", -- 0x0000
+ x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0008
+ x"00",x"00",x"E0",x"F0",x"F8",x"FC",x"FC",x"FC", -- 0x0010
+ x"00",x"00",x"01",x"07",x"1F",x"3F",x"7F",x"7F", -- 0x0018
+ x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020
+ x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0028
+ x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0030
+ x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"8F", -- 0x0038
+ x"00",x"00",x"C3",x"E3",x"F1",x"F1",x"F1",x"F1", -- 0x0040
+ x"00",x"00",x"F8",x"FC",x"FE",x"FE",x"FE",x"FE", -- 0x0048
+ x"00",x"00",x"1F",x"1F",x"0F",x"0F",x"0F",x"0F", -- 0x0050
+ x"00",x"00",x"81",x"C3",x"E2",x"E2",x"E2",x"E2", -- 0x0058
+ x"00",x"00",x"FC",x"06",x"FA",x"72",x"DA",x"FA", -- 0x0060
+ x"00",x"00",x"03",x"0F",x"3F",x"7F",x"7F",x"7F", -- 0x0068
+ x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"C7", -- 0x0070
+ x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0078
+ x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0080
+ x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0088
+ x"00",x"00",x"80",x"C0",x"C0",x"E0",x"E0",x"F0", -- 0x0090
+ x"00",x"00",x"3F",x"3F",x"06",x"06",x"06",x"06", -- 0x0098
+ x"00",x"00",x"D8",x"D8",x"18",x"1F",x"1F",x"18", -- 0x00A0
+ x"00",x"00",x"DF",x"DF",x"D8",x"DE",x"DE",x"D8", -- 0x00A8
+ x"00",x"00",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x00B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8
+ x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"3F", -- 0x0100
+ x"C1",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"80", -- 0x0108
+ x"FC",x"F8",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x0110
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0118
+ x"FF",x"C3",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0120
+ x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0128
+ x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0130
+ x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0138
+ x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0140
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148
+ x"0F",x"0F",x"0F",x"8F",x"8F",x"8F",x"DF",x"FF", -- 0x0150
+ x"E3",x"E3",x"E1",x"E0",x"E1",x"E1",x"E1",x"E3", -- 0x0158
+ x"56",x"8E",x"FC",x"00",x"FF",x"FE",x"FE",x"FC", -- 0x0160
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0168
+ x"83",x"03",x"03",x"0F",x"3F",x"FF",x"FF",x"FC", -- 0x0170
+ x"F8",x"F8",x"F8",x"F8",x"F0",x"C0",x"00",x"00", -- 0x0178
+ x"FF",x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0180
+ x"E7",x"87",x"07",x"07",x"07",x"00",x"00",x"FF", -- 0x0188
+ x"F0",x"F0",x"F0",x"E0",x"80",x"00",x"00",x"80", -- 0x0190
+ x"06",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198
+ x"18",x"18",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0
+ x"DF",x"DF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8
+ x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8
+ x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"7F",x"7F", -- 0x0200
+ x"80",x"80",x"80",x"83",x"87",x"87",x"07",x"06", -- 0x0208
+ x"00",x"1C",x"7C",x"FC",x"FC",x"FC",x"F0",x"F0", -- 0x0210
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0218
+ x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0220
+ x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0228
+ x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0230
+ x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"0F", -- 0x0238
+ x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0240
+ x"FF",x"FF",x"FF",x"FF",x"FE",x"FC",x"FC",x"FC", -- 0x0248
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"7F",x"7F", -- 0x0250
+ x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3", -- 0x0258
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0260
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0268
+ x"F0",x"C0",x"03",x"07",x"07",x"07",x"03",x"01", -- 0x0270
+ x"18",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0278
+ x"FF",x"FF",x"FF",x"FC",x"E0",x"06",x"1E",x"FE", -- 0x0280
+ x"FF",x"FF",x"FF",x"0F",x"07",x"07",x"07",x"07", -- 0x0288
+ x"C0",x"C0",x"E0",x"E0",x"F0",x"F0",x"F0",x"F0", -- 0x0290
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F", -- 0x0300
+ x"00",x"00",x"00",x"80",x"FF",x"FF",x"FF",x"FF", -- 0x0308
+ x"F0",x"78",x"7C",x"FC",x"FC",x"F8",x"F0",x"E0", -- 0x0310
+ x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0318
+ x"8F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0320
+ x"F8",x"F8",x"F8",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0328
+ x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"3F", -- 0x0330
+ x"1F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0338
+ x"F1",x"F1",x"F1",x"F1",x"E1",x"C1",x"81",x"03", -- 0x0340
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FE",x"FF", -- 0x0348
+ x"7F",x"3F",x"3F",x"3F",x"3F",x"1F",x"1F",x"1F", -- 0x0350
+ x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"C7", -- 0x0358
+ x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"F8",x"F0", -- 0x0360
+ x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0368
+ x"01",x"03",x"07",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0370
+ x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0378
+ x"FE",x"FE",x"FE",x"FF",x"FF",x"7F",x"1F",x"07", -- 0x0380
+ x"07",x"07",x"0F",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0388
+ x"F0",x"F0",x"F0",x"F0",x"FF",x"EF",x"C3",x"83", -- 0x0390
+ x"00",x"00",x"00",x"00",x"DB",x"DF",x"1F",x"1B", -- 0x0398
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8
+ );
+
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)));
+ end process;
+end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/make_rom.bat b/lib/VGA_ctrl/src/fonts/make_rom.bat
new file mode 100644
index 0000000..9cfa61b
--- /dev/null
+++ b/lib/VGA_ctrl/src/fonts/make_rom.bat
@@ -0,0 +1,6 @@
+@echo off
+
+bff2rom fixedsys_8x15.bff y >char_rom_fixedsys_8x15.vhd
+bff2rom fixedsys_8x16.bff y >char_rom_fixedsys_8x16.vhd
+bff2rom fixedsys_9x16.bff y >char_rom_fixedsys_9x16.vhd
+bff2rom System_16x16.bff y >char_rom_system_16x16.vhd
diff --git a/lib/VGA_ctrl/src/linefifo.vhd b/lib/VGA_ctrl/src/linefifo.vhd
new file mode 100644
index 0000000..4336ede
--- /dev/null
+++ b/lib/VGA_ctrl/src/linefifo.vhd
@@ -0,0 +1,121 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity linefifo is
+ Generic
+ (
+ depth : natural := 64;
+ almost_full_thresh : natural := 60;
+ almost_empty_thresh : natural := 4
+ );
+ Port
+ (
+ rst : in STD_LOGIC;
+ clk_w : in STD_LOGIC;
+ clk_r : in STD_LOGIC;
+ we_w : in STD_LOGIC;
+ re_r : in STD_LOGIC;
+ fifo_full : out STD_LOGIC;
+ fifo_empty : out STD_LOGIC;
+ fifo_afull : out STD_LOGIC;
+ fifo_aempty : out STD_LOGIC;
+ color_w : in color_t;
+ color_r : out color_t
+ );
+end linefifo;
+
+architecture Behavioral of linefifo is
+
+ constant data_width : integer := 8;
+ constant addr_width : integer := NextExpBaseTwo(depth);
+
+ signal buf_we_w : STD_LOGIC;
+ signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0);
+ signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0);
+ signal full : STD_LOGIC;
+ signal empty : STD_LOGIC;
+ signal almost_full : STD_LOGIC;
+ signal almost_empty : STD_LOGIC;
+
+begin
+
+ buf_we_w <= we_w;
+ fifo_full <= full;
+ fifo_empty <= empty;
+ fifo_afull <= almost_full;
+ fifo_aempty <= almost_empty;
+
+gen_line:
+ for c in color_range_t generate
+ begin
+ inst_dpram: entity work.dpram
+ GENERIC MAP
+ (
+ addr_width => addr_width,
+ data_width => data_width
+ )
+ PORT MAP(
+ clka => clk_w,
+ clkb => clk_r,
+ en_a => '1',
+ en_b => '1',
+ we_a => buf_we_w,
+ addr_a => ptr_w,
+ addr_b => ptr_r,
+ din_a => color_w(c),
+ dout_b => color_r(c)
+ );
+ end generate;
+
+ inst_fifo_ctrl: entity work.async_fifo_ctrl
+ GENERIC MAP
+ (
+ addr_width => ADDR_WIDTH,
+ almost_full_thresh => almost_full_thresh,
+ almost_empty_thresh => almost_empty_thresh
+ )
+ PORT MAP
+ (
+ rst => rst,
+ clk_w => clk_w,
+ clk_r => clk_r,
+ we => we_w,
+ re => re_r,
+ ptr_w => ptr_w,
+ ptr_r => ptr_r,
+ fifo_full => full,
+ fifo_empty => empty,
+ fifo_afull => almost_full,
+ fifo_aempty => almost_empty
+
+ );
+
+end Behavioral;
+
diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd
new file mode 100644
index 0000000..2994eec
--- /dev/null
+++ b/lib/VGA_ctrl/src/vga_backend.vhd
@@ -0,0 +1,223 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:25:45 10/15/05
+-- Design Name:
+-- Module Name: vga_backend - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity vga_backend is
+ Generic
+ (
+ sys_freq : integer := 100E6;
+ fifo_depth : integer := 2048;
+ fifo_almost_full_thresh : natural := 2000;
+ fifo_almost_empty_thresh : natural := 48;
+ tsvga : vga_timespec_t := ts_vga_800_600_72
+ );
+ Port
+ (
+ -- System signals
+ sys_rst : in std_logic;
+ sys_clk : in std_logic;
+ vga_ready : out std_logic;
+
+ -- Buffered channel (Graphics plane)
+ color_in : in color_t;
+ color_fifo_we : in std_logic;
+ color_fifo_full : out std_logic;
+ color_fifo_afull : out std_logic;
+
+ -- Direct channel (Character plane)
+ direct_color_in : in color_t;
+ direct_draw_en : in std_logic;
+
+ -- Status signals
+ stat_hsync : out std_logic;
+ stat_vsync : out std_logic;
+ stat_hready : out std_logic;
+ stat_vready : out std_logic;
+ stat_hscan : out std_logic;
+ stat_vscan : out std_logic;
+ stat_hpos : out natural range 0 to tsvga.ts_h.ncyc_scan-1;
+ stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1;
+
+ -- VGA domain signals
+ vga_clk_out : out std_logic;
+ vga_color_out : out color_t;
+ vga_blank_n : out std_logic;
+ vga_sync_n : out std_logic;
+ vga_hsync : out std_logic;
+ vga_vsync : out std_logic
+ );
+end vga_backend;
+
+architecture Behavioral of vga_backend is
+
+ signal scan_enable : std_logic;
+ signal fifo_full : std_logic;
+ signal fifo_empty : std_logic;
+ signal fifo_almost_empty : std_logic;
+ signal fifo_almost_full : std_logic;
+ signal is_scan : std_logic;
+ signal is_hscan : std_logic;
+ signal is_vscan : std_logic;
+ signal hsync : std_logic;
+ signal vsync : std_logic;
+ signal hready : std_logic;
+ signal vready : std_logic;
+ signal color : color_t;
+ signal vga_clk : std_logic;
+ signal dcm_locked : std_logic;
+ signal rst : std_logic;
+
+begin
+
+ vga_clk_out <= vga_clk;
+ vga_ready <= dcm_locked;
+
+ inst_clkgen: entity work.clkgen
+ GENERIC MAP
+ (
+ sys_freq => sys_freq,
+ tsvga => tsvga
+ )
+ PORT MAP
+ (
+ rst => sys_rst,
+ clk => sys_clk,
+ vga_clk => vga_clk,
+ dcm_locked => dcm_locked
+ );
+
+ inst_vga_timing: entity work.vga_timing
+ GENERIC MAP
+ (
+ tsvga => tsvga
+ )
+ PORT MAP
+ (
+ sys_rst => sys_rst,
+ vga_clk => vga_clk,
+ vga_ce => dcm_locked,
+ sync_h => hsync,
+ sync_v => vsync,
+ scan_pos_h => stat_hpos,
+ scan_pos_v => stat_vpos,
+ is_scan_h => is_hscan,
+ is_scan_v => is_vscan,
+ scan_rdy_h => hready,
+ scan_rdy_v => vready
+ );
+
+ inst_linefifo: entity work.linefifo
+ GENERIC MAP
+ (
+ depth => fifo_depth,
+ almost_full_thresh => fifo_almost_full_thresh,
+ almost_empty_thresh => fifo_almost_empty_thresh
+ )
+ PORT MAP(
+ rst => sys_rst,
+ clk_w => sys_clk,
+ clk_r => vga_clk,
+ we_w => color_fifo_we,
+ re_r => is_scan,
+ color_w => color_in,
+ color_r => color,
+ fifo_full => fifo_full,
+ fifo_empty => fifo_empty,
+ fifo_afull => fifo_almost_full,
+ fifo_aempty => fifo_almost_empty
+
+ );
+
+ ---------------------------------------------------------------------------------------------
+ rst <= not dcm_locked;
+ stat_hsync <= hsync;
+ stat_vsync <= vsync;
+ stat_hscan <= is_hscan;
+ stat_vscan <= is_vscan;
+ stat_hready <= hready;
+ stat_vready <= vready;
+
+ vga_blank_n <= '1';
+ vga_sync_n <= '0';
+ is_scan <= is_hscan and is_vscan and scan_enable;
+
+ color_fifo_full <= fifo_full;
+ color_fifo_afull <= fifo_almost_full;
+
+ ---------------------------------------------------------------------------------------------
+ proc_vga_start:
+ process (rst, vga_clk)
+ begin
+ if rst = '1' then
+ scan_enable <= '0';
+ elsif rising_edge(vga_clk) then
+ if vsync = '1' then
+ if fifo_empty = '0' then
+ scan_enable <= '1';
+ else
+ scan_enable <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ proc_vga_color_out:
+ process (rst, vga_clk)
+ variable do_scan : std_logic;
+ begin
+ if rst = '1' then
+ do_scan := '0';
+ elsif rising_edge(vga_clk) then
+ vga_color_out <= (X"00", X"00", X"00");
+ if do_scan = '1' then
+ if direct_draw_en = '1' then
+ vga_color_out <= direct_color_in;
+ else
+ vga_color_out <= color;
+ end if;
+ end if;
+ do_scan := is_scan;
+ end if;
+ end process;
+
+ ---------------------------------------------------------------------------------------------
+ proc_vga_sync_out:
+ process (rst, vga_clk)
+ variable hsync_r : std_logic;
+ variable vsync_r : std_logic;
+ begin
+ if rst = '1' then
+ vga_hsync <= tsvga.ts_h.sync_polarity;
+ vga_vsync <= tsvga.ts_v.sync_polarity;
+ hsync_r := tsvga.ts_h.sync_polarity;
+ vsync_r := tsvga.ts_v.sync_polarity;
+ elsif rising_edge(vga_clk) then
+ vga_hsync <= hsync_r;
+ vga_vsync <= vsync_r;
+ hsync_r := hsync xor (not tsvga.ts_h.sync_polarity);
+ vsync_r := vsync xor (not tsvga.ts_v.sync_polarity);
+ end if;
+ end process;
+
+end Behavioral;
diff --git a/lib/VGA_ctrl/src/vga_sync.vhd b/lib/VGA_ctrl/src/vga_sync.vhd
new file mode 100644
index 0000000..56e4384
--- /dev/null
+++ b/lib/VGA_ctrl/src/vga_sync.vhd
@@ -0,0 +1,127 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:15:39 10/21/05
+-- Design Name:
+-- Module Name: fsm_scan - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity vga_sync is
+ Generic
+ (
+ ts : scan_timespec_t := (4,2,1,3,'0')
+ );
+ Port
+ (
+ rst : in std_logic;
+ clk : in std_logic;
+ ce : in std_logic;
+ pos : out natural range 0 to ts.ncyc_scan-1;
+ sync : out std_logic;
+ is_scan : out std_logic;
+ rdy_scan : out std_logic
+ );
+ end vga_sync;
+
+architecture Behavioral of vga_sync is
+
+ type timing_state_t is (st_init, st_scan, st_front, st_sync, st_back);
+
+ -- Counter
+ signal state, next_state : timing_state_t;
+ signal count_srst : std_logic;
+ signal count : natural range 0 to ts.ncyc_scan-1;
+
+begin
+
+ pos <= count;
+
+---------------------------------------------------------------------------------------------
+counter:
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ if ce = '1' then
+ if count_srst = '1' then
+ count <= 0;
+ else
+ count <= count + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------------------------
+SYNC_TIMING:
+process (state, count)
+ begin
+ count_srst <= '0';
+ rdy_scan <= '0';
+ is_scan <= '0';
+ sync <= '0';
+
+ next_state <= state; --default is to stay in current state
+
+ case (state) is
+
+ when st_init =>
+ count_srst <= '1';
+ next_state <= st_front;
+ when st_front =>
+ if count = ts.ncyc_porch_front - 1 then
+ count_srst <= '1';
+ next_state <= st_sync;
+ end if;
+ when st_sync =>
+ sync <= '1';
+ if count = ts.ncyc_sync_pulse - 1 then
+ count_srst <= '1';
+ next_state <= st_back;
+ end if;
+ when st_back =>
+ if count = ts.ncyc_porch_back - 1 then
+ count_srst <= '1';
+ next_state <= st_scan;
+ end if;
+ when st_scan =>
+ is_scan <= '1';
+ if count = ts.ncyc_scan - 1 then
+ count_srst <= '1';
+ rdy_scan <= '1';
+ next_state <= st_front;
+ end if;
+ when others =>
+ next_state <= st_init;
+
+ end case;
+ end process;
+
+SYNC_TIMING_NEXT:
+ process (rst, clk)
+ begin
+ if rst = '1' then
+ state <= st_init;
+ elsif rising_edge(clk) and ce = '1' then
+ state <= next_state;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------------------------
+end Behavioral;
diff --git a/lib/VGA_ctrl/src/vga_timing.vhd b/lib/VGA_ctrl/src/vga_timing.vhd
new file mode 100644
index 0000000..c110652
--- /dev/null
+++ b/lib/VGA_ctrl/src/vga_timing.vhd
@@ -0,0 +1,102 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:25:45 10/15/05
+-- Design Name:
+-- Module Name: vga_ctrl_core - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity vga_timing is
+ Generic
+ (
+ tsvga : vga_timespec_t := ts_vga_800_600_72
+ );
+ Port
+ (
+ sys_rst : in std_logic;
+ vga_clk : in std_logic;
+ vga_ce : in std_logic;
+ sync_h : out std_logic;
+ sync_v : out std_logic;
+ scan_pos_h : out natural range 0 to tsvga.ts_h.ncyc_scan-1;
+ scan_pos_v : out natural range 0 to tsvga.ts_v.ncyc_scan-1;
+ is_scan_h : out std_logic;
+ is_scan_v : out std_logic;
+ scan_rdy_h : out std_logic;
+ scan_rdy_v : out std_logic
+ );
+end vga_timing;
+
+architecture Behavioral of vga_timing is
+
+ ---------------------------------------------------------------------------------------------
+ signal is_scan_h_i : std_logic;
+ signal is_scan_v_i : std_logic;
+ signal scan_rdy_h_i : std_logic;
+ signal scan_rdy_v_i : std_logic;
+ signal sync_h_i : std_logic;
+ signal sync_v_i : std_logic;
+
+ ---------------------------------------------------------------------------------------------
+begin
+
+ is_scan_h <= is_scan_h_i;
+ is_scan_v <= is_scan_v_i;
+ scan_rdy_h <= scan_rdy_h_i;
+ scan_rdy_v <= scan_rdy_v_i;
+ sync_h <= sync_h_i;
+ sync_v <= sync_v_i;
+
+ ---------------------------------------------------------------------------------------------
+ inst_vga_sync_h: entity work.vga_sync
+ GENERIC MAP
+ (
+ ts => tsvga.ts_h
+ )
+ PORT MAP
+ (
+ rst => sys_rst,
+ clk => vga_clk,
+ ce => vga_ce,
+ pos => scan_pos_h,
+ sync => sync_h_i,
+ is_scan => is_scan_h_i,
+ rdy_scan => scan_rdy_h_i
+ );
+
+ inst_vga_sync_v: entity work.vga_sync
+ GENERIC MAP
+ (
+ ts => tsvga.ts_v
+ )
+ PORT MAP
+ (
+ rst => sys_rst,
+ clk => vga_clk,
+ ce => scan_rdy_h_i,
+ pos => scan_pos_v,
+ sync => sync_v_i,
+ is_scan => is_scan_v_i,
+ rdy_scan => scan_rdy_v_i
+ );
+
+---------------------------------------------------------------------------------------------
+
+end Behavioral;
diff --git a/lib/VGA_ctrl/src/vga_types.vhd b/lib/VGA_ctrl/src/vga_types.vhd
new file mode 100644
index 0000000..44cecbd
--- /dev/null
+++ b/lib/VGA_ctrl/src/vga_types.vhd
@@ -0,0 +1,213 @@
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+
+package vga_types is
+
+ -- Constants
+
+ -- Types
+ type color_range_t is (r, g, b);
+ type color_t is array (color_range_t) of unsigned(7 downto 0);
+
+ type scan_timespec_t is
+ record
+ ncyc_scan : integer;
+ ncyc_porch_front : integer;
+ ncyc_sync_pulse : integer;
+ ncyc_porch_back : integer;
+ sync_polarity : std_logic;
+ end record;
+
+ type vga_timespec_t is
+ record
+ f_pxl_clk : integer;
+ nfps : integer;
+ ts_h : scan_timespec_t;
+ ts_v : scan_timespec_t;
+ end record;
+
+ -----------------------------------------------------------------------
+ -- Common timimg specifications
+ -----------------------------------------------------------------------
+ -- For test bench (not for H/W use)
+ constant ts_vga_testbench : vga_timespec_t :=
+ (
+ f_pxl_clk => 100E6,
+ nfps => 6,
+ ts_h => (8,5,2,3,'0'),
+ ts_v => (6,4,2,3,'0')
+ );
+
+ -- 640 x 480 @ 60 Hz (not recommended)
+ constant ts_vga_640_480_60 : vga_timespec_t :=
+ (
+ f_pxl_clk => 25175000,
+ nfps => 60,
+ ts_h => (640,16,96,48,'0'),
+ ts_v => (480,11,2,31,'0')
+ );
+
+ -- 640 x 480 @ 72 Hz (not recommended)
+ constant ts_vga_640_480_72 : vga_timespec_t :=
+ (
+ f_pxl_clk => 31500000,
+ nfps => 72,
+ ts_h => (640,24,40,128,'0'),
+ ts_v => (480,9,3,28,'0')
+ );
+
+ -- 800 x 600 @ 60 Hz (OK)
+ constant ts_vga_800_600_60 : vga_timespec_t :=
+ (
+ f_pxl_clk => 40000000,
+ nfps => 60,
+ ts_h => (800,40,128,88,'0'),
+ ts_v => (600,1,4,23,'0')
+ );
+
+ -- 800 x 600 @ 72 Hz (OK)
+ constant ts_vga_800_600_72 : vga_timespec_t :=
+ (
+ f_pxl_clk => 50000000,
+ nfps => 72,
+ ts_h => (800,56,120,64,'0'),
+ ts_v => (600,37,6,23,'0')
+ );
+
+ -- 1024 x 768 @ 60 Hz (Noisy)
+ constant ts_vga_1024_768_60 : vga_timespec_t :=
+ (
+ f_pxl_clk => 65000000,
+ nfps => 60,
+ ts_h => (1024,24,136,160,'0'),
+ ts_v => (768,3,6,29,'0')
+ );
+
+ -- 1024 x 768 @ 70 Hz (OK)
+ constant ts_vga_1024_768_70 : vga_timespec_t :=
+ (
+ f_pxl_clk => 75000000,
+ nfps => 70,
+ ts_h => (1024,24,136,144,'0'),
+ ts_v => (768,3,6,29,'0')
+ );
+
+ -- 1280 x 1024 @ 70 Hz (Noisy)
+ constant ts_vga_1280_1024_70 : vga_timespec_t :=
+ (
+ f_pxl_clk => 125000000,
+ nfps => 70,
+ ts_h => (1280,16,176,192,'0'),
+ ts_v => (1024,3,3,42,'0')
+ );
+
+ -- 1280 x 1024 @ 72 Hz (OK)
+ constant ts_vga_1280_1024_72 : vga_timespec_t :=
+ (
+ f_pxl_clk => 130000000,
+ nfps => 72,
+ ts_h => (1280,32,160,224,'0'),
+ ts_v => (1024,2,2,33,'0')
+ );
+
+ -- Functions
+ function NextPowerOfTwo(x : natural) return natural;
+ function NextExpBaseTwo(x : natural) return natural;
+ function GCD(a, b : natural) return natural;
+ function LCM(a, b : natural) return natural;
+ function DCM_PERIOD(f_sys_hz : natural) return real;
+ function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural;
+ function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural;
+
+end vga_types;
+
+
+package body vga_types is
+
+ function NextExpBaseTwo(x : natural) return natural is
+ begin
+ return natural(ceil(log2(real(x))));
+ end NextExpBaseTwo;
+
+ function NextPowerOfTwo(x : natural) return natural is
+ begin
+
+ return 2**NextExpBaseTwo(x);
+ end NextPowerOfTwo;
+
+ function GCD(a, b : natural) return natural is
+ variable aa : natural;
+ variable bb : natural;
+ begin
+ aa := a;
+ bb := b;
+ while bb /= 0 loop
+ if aa > bb then
+ aa := aa - bb;
+ else
+ bb := bb - aa;
+ end if;
+ end loop;
+
+ return aa;
+
+ end GCD;
+
+ function LCM(a, b : natural) return natural is
+ begin
+
+ return (a * b)/GCD(a, b);
+
+ end LCM;
+
+ function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural is
+ variable f_sys_mhz : natural;
+ variable f_vga_mhz : natural;
+ variable m : natural;
+ begin
+ f_sys_mhz := f_sys_hz/1E6;
+ f_vga_mhz := f_vga_hz/1E6;
+ m := f_vga_mhz/GCD(f_sys_mhz, f_vga_mhz);
+
+ if m = 1 then
+ m := 2;
+ end if;
+
+ return m;
+
+ end DCM_FREQ_M;
+
+ function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural is
+ variable f_sys_mhz : natural;
+ variable f_vga_mhz : natural;
+ variable m : natural;
+ variable d : natural;
+ begin
+ m := DCM_FREQ_M(f_sys_hz, f_vga_hz);
+ f_sys_mhz := f_sys_hz/1E6;
+ f_vga_mhz := f_vga_hz/1E6;
+ d := m*f_sys_mhz/f_vga_mhz;
+
+ return d;
+
+ end DCM_FREQ_D;
+
+ function DCM_PERIOD(f_sys_hz : natural) return real is
+ begin
+
+ return 1.0E9/real(f_sys_hz);
+
+ end DCM_PERIOD;
+
+
+end vga_types;
+
+
diff --git a/lib/filter/sim/eval_lowpass.m b/lib/filter/sim/eval_lowpass.m
new file mode 100644
index 0000000..ccac021
--- /dev/null
+++ b/lib/filter/sim/eval_lowpass.m
@@ -0,0 +1,37 @@
+function eval_filter(N)
+omega_lp = 0.15
+omega_hp = 0.05
+
+omega_bp_m = 0.02;
+bw2_bp = 0.02;
+
+lp = lowpass(N, omega_lp, 1.0);
+coef_lp = hann(N)'.*lp./sum(lp.^2);
+
+hp = lowpass(N, 0.5-omega_hp, 1.0).*cos(pi*(0:N-1));
+coef_hp = hp./sum(hp.^2).*hann(N)';
+
+bp = lowpass(N, bw2_bp/2, 1.0).*cos(2*pi*omega_bp_m*(0:N-1));
+coef_bp = bp./sum(bp.^2).*hann(N)';
+
+abs_lp = 20*log10(abs(fft(coef_lp)));
+abs_hp = 20*log10(abs(fft(coef_hp)));
+abs_bp = 20*log10(abs(fft(coef_bp)));
+
+close all;
+plot((0:N/2)/N, abs_lp(1:N/2+1));grid;
+figure
+plot((0:N/2)/N, abs_hp(1:N/2+1));grid;
+figure
+plot((0:N/2)/N, abs_bp(1:N/2+1));grid;
+
+figure
+plot((0:N-1), coef_lp);grid;
+figure
+plot((0:N-1), coef_hp);grid;
+figure
+plot((0:N-1), coef_bp);grid;
+
+mean_lp = mean(coef_lp-mean(coef_lp))
+mean_hp = mean(coef_hp)
+mean_bp = mean(coef_bp)
diff --git a/lib/filter/sim/lowpass.m b/lib/filter/sim/lowpass.m
new file mode 100644
index 0000000..292964d
--- /dev/null
+++ b/lib/filter/sim/lowpass.m
@@ -0,0 +1,20 @@
+function coef = lowpass(N, omega, scale)
+
+phi = 0;
+dphi = 2*omega;
+if (mod(N, 2) == 0)
+ M = N/2;
+ for i=0:M-1,
+ phi = phi + dphi;
+ coef(M+i+1) = scale*sinc(phi);
+ coef(M-i-1+1) = coef(M+i+1);
+ end;
+else
+ M = (N-1)/2;
+ for i=1:M,
+ phi = phi + dphi;
+ coef(M+i+1) = scale*sinc(phi);
+ coef(M-i+1) = coef(M+i+1);
+ end;
+ coef(M+1) = scale*Sinc(0.0);
+end;
diff --git a/lib/filter/sim/tb_fir_iterative.fdo b/lib/filter/sim/tb_fir_iterative.fdo
new file mode 100644
index 0000000..d4f35ff
--- /dev/null
+++ b/lib/filter/sim/tb_fir_iterative.fdo
@@ -0,0 +1,16 @@
+vlib work
+vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
+vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit -93 "../src/filter_pkg.vhd"
+vcom -explicit -93 "../src/fir_stage_pkg.vhd"
+vcom -explicit -93 "../src/fir_stage.vhd"
+vcom -explicit -93 "../src/fir_iterative_pkg.vhd"
+vcom -explicit -93 "../src/fir_iterative.vhd"
+vcom -explicit -93 "../src/tb_fir_iterative.vhd"
+vsim -t 1ps -lib work tb_fir_iterative
+do {tb_fir_iterative.wdo}
+view wave
+view structure
+view signals
+run 20us
diff --git a/lib/filter/sim/tb_fir_iterative.wdo b/lib/filter/sim/tb_fir_iterative.wdo
new file mode 100644
index 0000000..1832c4e
--- /dev/null
+++ b/lib/filter/sim/tb_fir_iterative.wdo
@@ -0,0 +1,86 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
+add wave -noupdate -format Literal /tb_fir_iterative/coeffs
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
+add wave -noupdate -format Literal /tb_fir_iterative/xi
+add wave -noupdate -format Literal /tb_fir_iterative/yo
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem
+add wave -noupdate -divider {Xmem Dual}
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
+add wave -noupdate -format Literal /tb_fir_iterative/coeffs
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
+add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi
+add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
+add wave -noupdate -format Logic /tb_fir_iterative/y_valid
+add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
+add wave -noupdate -divider {FIR Stage}
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/in_valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out_clr
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/valid
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/p_valid
+add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
+add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/out_valid
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1892287 ps} 0}
+configure wave -namecolwidth 140
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {1750644 ps} {2771198 ps}
diff --git a/lib/filter/sim/tb_fir_parallel b/lib/filter/sim/tb_fir_parallel
new file mode 100644
index 0000000..f784c1a
Binary files /dev/null and b/lib/filter/sim/tb_fir_parallel differ
diff --git a/lib/filter/sim/tb_fir_parallel.fdo b/lib/filter/sim/tb_fir_parallel.fdo
new file mode 100644
index 0000000..9e15809
--- /dev/null
+++ b/lib/filter/sim/tb_fir_parallel.fdo
@@ -0,0 +1,16 @@
+vlib work
+vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
+vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit -93 "../src/filter_pkg.vhd"
+vcom -explicit -93 "../src/fir_stage_pkg.vhd"
+vcom -explicit -93 "../src/fir_stage.vhd"
+vcom -explicit -93 "../src/fir_parallel_pkg.vhd"
+vcom -explicit -93 "../src/fir_parallel.vhd"
+vcom -explicit -93 "../src/tb_fir_parallel.vhd"
+vsim -t 1ps -lib work tb_fir_parallel
+do {tb_fir_parallel.wdo}
+view wave
+view structure
+view signals
+run 1000us
diff --git a/lib/filter/sim/tb_fir_parallel.wdo b/lib/filter/sim/tb_fir_parallel.wdo
new file mode 100644
index 0000000..f0e20ce
--- /dev/null
+++ b/lib/filter/sim/tb_fir_parallel.wdo
@@ -0,0 +1,29 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_fir_parallel/clk
+add wave -noupdate -format Logic /tb_fir_parallel/srst
+add wave -noupdate -format Logic /tb_fir_parallel/in_valid
+add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/x_in
+add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/y_out
+add wave -noupdate -format Logic /tb_fir_parallel/out_valid
+add wave -noupdate -format Logic /tb_fir_parallel/fileout_enable
+add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/xi
+add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/yo
+add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/coeff_in
+add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/uut_fir_parallel/h
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {19450000 ps} 0}
+configure wave -namecolwidth 140
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {25152750 ps}
diff --git a/lib/filter/sim/tb_fir_results.m b/lib/filter/sim/tb_fir_results.m
new file mode 100644
index 0000000..75a542c
--- /dev/null
+++ b/lib/filter/sim/tb_fir_results.m
@@ -0,0 +1,10 @@
+% Read data
+function tb_fir_results()
+fir = TEXTREAD('fir.txt')';
+
+N= length(fir);
+
+% Output
+close all;
+plot(0:N-1, fir); grid;
+
diff --git a/lib/filter/sim/tb_fir_stage.fdo b/lib/filter/sim/tb_fir_stage.fdo
new file mode 100644
index 0000000..9b4379d
--- /dev/null
+++ b/lib/filter/sim/tb_fir_stage.fdo
@@ -0,0 +1,14 @@
+vlib work
+vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd"
+vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit -93 "../src/filter_pkg.vhd"
+vcom -explicit -93 "../src/fir_stage_pkg.vhd"
+vcom -explicit -93 "../src/fir_stage.vhd"
+vcom -explicit -93 "../src/tb_fir_stage.vhd"
+vsim -t 1ps -lib work tb_fir_stage
+do {tb_fir_stage.wdo}
+view wave
+view structure
+view signals
+run 2us
diff --git a/lib/filter/sim/tb_fir_stage.wdo b/lib/filter/sim/tb_fir_stage.wdo
new file mode 100644
index 0000000..916de83
--- /dev/null
+++ b/lib/filter/sim/tb_fir_stage.wdo
@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_fir_stage/clk
+add wave -noupdate -format Logic /tb_fir_stage/srst
+add wave -noupdate -divider Input
+add wave -noupdate -format Logic /tb_fir_stage/in_valid
+add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x_in
+add wave -noupdate -format Literal /tb_fir_stage/xi
+add wave -noupdate -divider Output
+add wave -noupdate -format Logic /tb_fir_stage/out_valid
+add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y_out
+add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_stage/yo
+add wave -noupdate -divider {Stage signals}
+add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x
+add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1655000 ps} 0}
+configure wave -namecolwidth 140
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {2100 ns}
diff --git a/lib/filter/src/filter_pkg.vhd b/lib/filter/src/filter_pkg.vhd
new file mode 100644
index 0000000..22be814
--- /dev/null
+++ b/lib/filter/src/filter_pkg.vhd
@@ -0,0 +1,227 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use IEEE.MATH_REAL.ALL;
+
+-------------------------------------------------------------------------------
+package filter_pkg is
+
+ constant pi : real := 3.141592653589793e+000;
+ type real_array_t is array (natural range <>) of real;
+
+ function FilterCoef_Lowpass (N : positive; omega, amp : real) return real_array_t;
+ function FilterCoef_Highpass (N : positive; omega, amp : real) return real_array_t;
+ function FilterCoef_Bandpass (N : positive; bw2, omega_m, amp : real) return real_array_t;
+ function FilterCoef_Delta (N:positive; delay:natural; amp:real) return real_array_t;
+ function Window_Hamming (x : real_array_t) return real_array_t;
+ function Window_VonHann (x : real_array_t) return real_array_t;
+ function Window_Blackman (x : real_array_t) return real_array_t;
+ function Sinc (x : real) return real;
+ function FilterEnergy (x : real_array_t) return real;
+ function FilterMean (x : real_array_t) return real;
+ function FilterScale (x : real_array_t; scale : real) return real_array_t;
+ function FilterTestCoef (N : positive) return real_array_t;
+ function NextPowerOfTwo(x : real) return natural;
+
+end; -- package filter_pkg;
+
+-------------------------------------------------------------------------------
+package body filter_pkg is
+
+ function Prototype_Lowpass (N : positive; omega : real) return real_array_t is
+ variable res : real_array_t(0 to N-1);
+ variable M : positive;
+ variable phi : real := 0.0;
+ variable dphi : real := 2.0*pi*omega;
+ begin
+ if (N mod 2) = 0 then
+ M := N/2;
+ for i in 0 to M-1 loop
+ phi := phi + dphi;
+ res(M+i) := Sinc(phi);
+ res(M-i-1) := res(M+i);
+ end loop;
+ else
+ M := (N-1)/2;
+ for i in 1 to M loop
+ phi := phi + dphi;
+ res(M+i) := Sinc(phi);
+ res(M-i) := res(M+i);
+ end loop;
+ res(M) := Sinc(0.0);
+ end if;
+ return res;
+
+ end Prototype_Lowpass;
+
+ -------------------------------------------------------------------------------
+ function FilterCoef_Lowpass (N : positive; omega, amp : real) return real_array_t is
+ variable lp : real_array_t(0 to N-1);
+ begin
+ lp := Prototype_Lowpass(N, omega);
+
+ return Window_VonHann(FilterScale(lp, amp/FilterEnergy(lp)));
+
+ end FilterCoef_Lowpass;
+
+ -------------------------------------------------------------------------------
+ function FilterCoef_Highpass (N : positive; omega, amp : real) return real_array_t is
+ variable lp, res : real_array_t(0 to N-1);
+ variable phi : real := 0.0;
+ variable dphi : real := pi;
+ begin
+ lp := Prototype_Lowpass(N, 0.5-omega);
+
+ for i in 0 to N-1 loop
+ res(i) := lp(i) * cos(phi);
+ phi := phi + dphi;
+ end loop;
+
+ return Window_VonHann(FilterScale(res, amp/FilterEnergy(lp)));
+
+ end FilterCoef_Highpass;
+
+ -------------------------------------------------------------------------------
+ function FilterCoef_Bandpass (N : positive; bw2, omega_m, amp : real) return real_array_t is
+ variable lp, res, mean, sum : real_array_t(0 to N-1);
+ variable phi : real := 0.0;
+ variable dphi : real := 2.0*pi*omega_m;
+ begin
+ lp := Prototype_Lowpass(N, bw2/2.0);
+
+ for i in 0 to N-1 loop
+ res(i) := lp(i) * cos(phi);
+ phi := phi + dphi;
+ end loop;
+
+ return Window_VonHann(FilterScale(res, amp/FilterEnergy(lp)));
+
+ end FilterCoef_Bandpass;
+
+ -------------------------------------------------------------------------------
+ function FilterCoef_Delta (N:positive; delay:natural; amp:real) return real_array_t is
+ variable res : real_array_t(0 to N-1);
+ begin
+ for i in 0 to N-1 loop
+ res(i) := 0.0;
+ end loop;
+ res(delay) := amp;
+
+ return res;
+
+ end FilterCoef_Delta;
+
+ -------------------------------------------------------------------------------
+ function FilterTestCoef (N : positive) return real_array_t is
+ variable phi : real := 0.0;
+ variable dphi : real := 1.0/real(N);
+ variable res : real_array_t(0 to N-1);
+ begin
+ for i in 0 to N-1 loop
+ res(i) := phi;
+ phi := phi + dphi;
+ end loop;
+ return res;
+
+ end FilterTestCoef;
+
+ -------------------------------------------------------------------------------
+ function Window_Hamming (x : real_array_t) return real_array_t is
+ variable res : real_array_t(x'range);
+ variable phi : real := 0.0;
+ variable dphi : real := 2.0*pi/real(x'length-1);
+ begin
+ for i in x'range loop
+ res(i) := x(i) * (0.54 - 0.46*(cos(phi)));
+ phi := phi + dphi;
+ end loop;
+ return res;
+
+ end Window_Hamming;
+
+ -------------------------------------------------------------------------------
+ function Window_VonHann (x : real_array_t) return real_array_t is
+ variable res : real_array_t(x'range);
+ variable phi : real := 0.0;
+ variable dphi : real := 2.0*pi/real(x'length-1);
+ begin
+ for i in x'range loop
+ res(i) := 0.5 * x(i) * (1.0 - (cos(phi)));
+ phi := phi + dphi;
+ end loop;
+ return res;
+
+ end Window_VonHann;
+
+ -------------------------------------------------------------------------------
+ function Window_Blackman (x : real_array_t) return real_array_t is
+ variable res : real_array_t(0 to x'length-1);
+ variable phi : real := 0.0;
+ variable dphi : real := 2.0*pi/real(x'length-1);
+ begin
+ for i in x'range loop
+ res(i) := x(i) * (0.42 - 0.5*cos(phi) + 0.08*cos(2.0*phi));
+ phi := phi + dphi;
+ end loop;
+ return res;
+
+ end Window_Blackman;
+
+ -------------------------------------------------------------------------------
+ function Sinc (x : real) return real is
+ variable res : real := 1.0;
+ begin
+ if x /= 0.0 then
+ res := sin(x)/x;
+ end if;
+
+ return res;
+
+ end Sinc;
+
+ -------------------------------------------------------------------------------
+ function FilterScale (x : real_array_t; scale : real) return real_array_t is
+ variable res : real_array_t(x'range);
+ begin
+ for i in x'range loop
+ res(i) := scale * x(i);
+ end loop;
+
+ return res;
+
+ end FilterScale;
+
+ -------------------------------------------------------------------------------
+ function FilterEnergy (x : real_array_t) return real is
+ variable res : real := 0.0;
+ begin
+ for i in x'range loop
+ res := res + x(i)*x(i);
+ end loop;
+
+ return res;
+
+ end FilterEnergy;
+
+ -------------------------------------------------------------------------------
+ function FilterMean (x : real_array_t) return real is
+ variable res : real := 0.0;
+ begin
+ for i in x'range loop
+ res := res + x(i);
+ end loop;
+
+ return res/real(x'length);
+
+ end FilterMean;
+
+ -------------------------------------------------------------------------------
+ function NextPowerOfTwo(x : real) return natural is
+ begin
+ return integer(ceil(log2(x)));
+
+ end NextPowerOfTwo;
+
+-------------------------------------------------------------------------------
+end; -- package filter_pkg;
diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd
new file mode 100644
index 0000000..24805fd
--- /dev/null
+++ b/lib/filter/src/fir_iterative.vhd
@@ -0,0 +1,352 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: fir_parallel - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.fir_stage_pkg.all;
+use work.fir_iterative_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity fir_iterative is
+Generic
+(
+ ntaps : integer := 33;
+ nbits_in : integer := 12;
+ nbits_in_frac : integer := 11;
+ nbits_stages : integer := 13;
+ nbits_stages_frac : integer := 11;
+ nbits_out : integer := 12;
+ nbits_out_frac : integer := 11;
+ fir_mode : fir_iterative_mode_t := normal;
+ rounding : boolean := true;
+ saturating : boolean := true
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ h_din : in sfixed;
+ h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
+ ready : out std_logic;
+ x_valid : in std_logic;
+ x_din : in sfixed;
+ y_dout_valid : out std_logic;
+ y_dout : out sfixed
+);
+end fir_iterative;
+
+architecture Behavioral of fir_iterative is
+
+-------------------------------------------------------------------------------
+ -- Component Declaration for FIR stage
+ COMPONENT fir_stage
+ GENERIC
+ (
+ nbits_in : integer;
+ nbits_in_frac : integer;
+ nbits_out : integer;
+ nbits_out_frac : integer;
+ has_in_reg : boolean;
+ has_pipe_reg : boolean;
+ fir_mode : fir_stage_mode_t;
+ rounding : boolean;
+ saturating : boolean
+ );
+ PORT
+ (
+ srst : in std_logic;
+ clk : in std_logic;
+ in_valid : in std_logic;
+ x_in : in sfixed;
+ y_in : in sfixed;
+ h_in : in sfixed;
+ out_valid : out std_logic;
+ x_out : out sfixed;
+ y_out : out sfixed;
+ y_out_clr : in std_logic
+ );
+ END COMPONENT;
+
+ -------------------------------------------------------------------------------
+ constant fir_stage_mode : fir_stage_mode_t := transposed;
+ constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
+ constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode);
+
+ subtype in_t is sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+ subtype stage_t is sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
+
+ type state_t is (init, idle, start, proc, p1, p2, output);
+ signal s, sn : state_t;
+ signal x_stage, xo, y_stage : stage_t;
+ signal stage_en, cnt_en, new_round : std_logic;
+
+ subtype tap_cnt_t is natural range 0 to ntaps-1;
+ signal htap_cnt : tap_cnt_t;
+ signal xtap_cnt_w : tap_cnt_t;
+ signal xtap_cnt_r : tap_cnt_t;
+ signal stage_valid, clr_xmem, valid, fir_stage_clr, fir_stage_en, cnt_reset : std_logic;
+ subtype tap_range_t is natural range 0 to ntaps_addr(ntaps, fir_mode)-1;
+ signal h_addr : tap_range_t;
+ signal xmem_din, xmem_dout : in_t;
+ signal xmem_we, y_valid : std_logic;
+
+ type xmem_t is array (0 to ntaps-1) of in_t;
+ signal xmem : xmem_t;
+ signal y_out_reg : stage_t;
+ signal y_reg_valid : std_logic;
+
+ -------------------------------------------------------------------------------
+begin
+
+ h_addr_out <= to_unsigned(h_addr, h_addr_bits);
+ x_stage <= resize(xmem_dout, x_stage, false, false);
+
+ ----------------------------------------
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ y_reg_valid <= '0';
+ if srst = '1' then
+ y_out_reg <= to_sfixed(0, sproto(nbits_out, nbits_out_frac));
+ elsif y_valid = '1' then
+ y_out_reg <= y_stage;
+ y_reg_valid <= '1';
+ end if;
+ end if;
+ end process;
+
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ y_dout_valid <= '0';
+ if srst = '1' then
+ y_dout <= to_sfixed(0, sproto(nbits_out, nbits_out_frac));
+ elsif y_reg_valid = '1' then
+ y_dout <= resize(y_out_reg, sproto(nbits_out, nbits_out_frac), rounding, saturating);
+ y_dout_valid <= '1';
+ end if;
+ end if;
+ end process;
+
+ ----------------------------------------
+ proc_xmem_rw: process (clk)
+ begin
+ if rising_edge(clk) then
+ if xmem_we = '1' then
+ xmem(xtap_cnt_w) <= xmem_din;
+ end if;
+ xmem_dout <= xmem(xtap_cnt_r);
+ end if;
+ end process;
+
+ ----------------------------------------
+ proc_xmem_dinmux: process(new_round, clr_xmem, x_din, xmem_dout)
+ begin
+ xmem_din <= to_sfixed(0, xmem_din);
+ if new_round = '1' and clr_xmem = '0' then
+ xmem_din <= sfixed(x_din);
+ end if;
+ end process;
+
+ ----------------------------------------
+ proc_xmem_pointer: process(clk, new_round ,clr_xmem)
+ begin
+ xmem_we <= clr_xmem or new_round;
+ if rising_edge(clk) then
+ if srst = '1' then
+ xtap_cnt_w <= tap_cnt_t'high;
+ elsif xmem_we = '1' then
+ if xtap_cnt_w /= tap_cnt_t'low then
+ xtap_cnt_w <= xtap_cnt_w - 1;
+ else
+ xtap_cnt_w <= tap_cnt_t'high;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ ----------------------------------------
+ proc_h_addr: process(htap_cnt)
+ begin
+ if fir_mode = symmetric then
+ if ntaps_is_even then
+ if htap_cnt > ntaps/2-1 then
+ h_addr <= ntaps - htap_cnt - 1;
+ else
+ h_addr <= htap_cnt;
+ end if;
+ else
+ if htap_cnt > (ntaps-1)/2 then
+ h_addr <= ntaps - htap_cnt - 1;
+ else
+ h_addr <= htap_cnt;
+ end if;
+ end if;
+ else
+ h_addr <= htap_cnt;
+ end if;
+ end process;
+
+ ----------------------------------------
+ proc_tap_counter: process(cnt_reset, clk, htap_cnt, xtap_cnt_r, xtap_cnt_w, cnt_en)
+ begin
+ if rising_edge(clk) then
+ if cnt_reset = '1' then
+ htap_cnt <= tap_cnt_t'low;
+ xtap_cnt_r <= xtap_cnt_w;
+ elsif cnt_en = '1' then
+ if htap_cnt /= tap_cnt_t'high then
+ htap_cnt <= htap_cnt + 1;
+ else
+ htap_cnt <= tap_cnt_t'low;
+ end if;
+ if xtap_cnt_r /= tap_cnt_t'high then
+ xtap_cnt_r <= xtap_cnt_r + 1;
+ else
+ xtap_cnt_r <= tap_cnt_t'low;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ ----------------------------------------
+ proc_valid_out: process(srst, clk, valid, new_round)
+ variable val_pipe : unsigned(4 downto 0);
+ variable ctrl_pipe : unsigned(2 downto 0);
+
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ ctrl_pipe := (others => '0');
+ fir_stage_en <= '0';
+ fir_stage_clr <= '0';
+ else
+ ctrl_pipe := ctrl_pipe(ctrl_pipe'left-1 downto ctrl_pipe'right) & new_round;
+ fir_stage_en <= stage_en;
+ fir_stage_clr <= ctrl_pipe(2);
+ end if;
+ end if;
+ cnt_reset <= new_round;
+ end process;
+
+ ----------------------------------------
+ proc_fsm: process(s, x_valid, htap_cnt, xtap_cnt_w)
+ begin
+ clr_xmem <= '0';
+ new_round <= '0';
+ cnt_en <= '0';
+ ready <= '0';
+ valid <= '0';
+ sn <= s;
+ stage_en <= '0';
+ y_valid <= '0';
+
+ case s is
+ when init =>
+ clr_xmem <= '1';
+ if xtap_cnt_w = tap_cnt_t'low then
+ sn <= idle;
+ end if;
+
+ when idle =>
+ ready <= '1';
+ if x_valid = '1' then
+ sn <= start;
+ end if;
+
+ when start =>
+ new_round <= '1';
+ sn <= proc;
+
+ when proc =>
+ stage_en <= '1';
+ cnt_en <= '1';
+ if htap_cnt = tap_cnt_t'high then
+ sn <= p1;
+ end if;
+
+ when p1 =>
+ sn <= p2;
+
+ when p2 =>
+ sn <= output;
+ ready <= '1';
+
+ when output =>
+ sn <= idle;
+ y_valid <= '1';
+ ready <= '1';
+ if x_valid = '1' then
+ sn <= start;
+ end if;
+
+ when others => null;
+ end case;
+ end process;
+
+ proc_fsm_next: process(srst, clk, sn)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ s <= init;
+ else
+ s <= sn;
+ end if;
+ end if;
+ end process;
+
+ ----------------------------------------
+ inst_fir_stage: fir_stage
+ GENERIC MAP
+ (
+ nbits_in => nbits_stages,
+ nbits_in_frac => nbits_stages_frac,
+ nbits_out => nbits_stages,
+ nbits_out_frac => nbits_stages_frac,
+ has_in_reg => true,
+ has_pipe_reg => true,
+ fir_mode => fir_stage_mode,
+ rounding => false,
+ saturating => false
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => fir_stage_en,
+ x_in => x_stage,
+ y_in => y_stage,
+ h_in => h_din,
+ out_valid => stage_valid,
+ x_out => xo,
+ y_out_clr => fir_stage_clr,
+ y_out => y_stage
+ );
+
+ ----------------------------------------
+ -- Finished instantiation
+ ----------------------------------------
+
+end Behavioral;
diff --git a/lib/filter/src/fir_iterative_pkg.vhd b/lib/filter/src/fir_iterative_pkg.vhd
new file mode 100644
index 0000000..3d71626
--- /dev/null
+++ b/lib/filter/src/fir_iterative_pkg.vhd
@@ -0,0 +1,45 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+use ieee.numeric_std.all;
+use work.fixed_pkg.all;
+use work.filter_pkg.all;
+
+-------------------------------------------------------------------------------
+package fir_iterative_pkg is
+
+ type fir_iterative_mode_t is (normal, symmetric);
+
+ function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer;
+ function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer;
+
+end; -- package fir_iterative_pkg;
+
+-------------------------------------------------------------------------------
+package body fir_iterative_pkg is
+
+ function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is
+ variable res : integer;
+ begin
+ res := NextPowerOfTwo(real(ntaps_addr(ntaps, mode)));
+ return res;
+ end taps_nbits;
+
+ function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is
+ constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
+ variable res : integer := ntaps;
+ begin
+ if mode = symmetric then
+ if ntaps_is_even then
+ res := ntaps/2;
+ else
+ res := (ntaps-1)/2 + 1;
+ end if;
+ end if;
+ return res;
+ end ntaps_addr;
+
+end; -- package fir_iterative_pkg;
+
+-------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_parallel.vhd b/lib/filter/src/fir_parallel.vhd
new file mode 100644
index 0000000..a46dba9
--- /dev/null
+++ b/lib/filter/src/fir_parallel.vhd
@@ -0,0 +1,208 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: fir_parallel - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.fir_stage_pkg.all;
+use work.fir_parallel_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity fir_parallel is
+Generic
+(
+ ntaps : integer := 33;
+ nbits_in : integer := 12;
+ nbits_in_frac : integer := 11;
+ nbits_stages : integer := 13;
+ nbits_stages_frac : integer := 11;
+ nbits_out : integer := 12;
+ nbits_out_frac : integer := 11;
+ has_in_reg : boolean := false;
+ has_pipe_reg : boolean := false;
+ has_out_reg : boolean := false;
+ fir_mode : fir_parallel_mode_t := transposed;
+ rounding : boolean := true;
+ saturating : boolean := true
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ h_in : in sfixed_array_t;
+ in_valid : in std_logic;
+ d_in : in sfixed;
+ out_valid : out std_logic;
+ d_out : out sfixed
+);
+end fir_parallel;
+
+architecture Behavioral of fir_parallel is
+
+-------------------------------------------------------------------------------
+ -- Component Declaration for FIR stage
+ COMPONENT fir_stage
+ GENERIC
+ (
+ nbits_in : integer;
+ nbits_in_frac : integer;
+ nbits_out : integer;
+ nbits_out_frac : integer;
+ has_in_reg : boolean;
+ has_pipe_reg : boolean;
+ has_out_reg : boolean;
+ fir_mode : fir_stage_mode_t;
+ rounding : boolean;
+ saturating : boolean
+ );
+ PORT
+ (
+ srst : in std_logic;
+ clk : in std_logic;
+ in_valid : in std_logic;
+ x_in : in sfixed;
+ y_in : in sfixed;
+ h_in : in sfixed;
+ out_valid : out std_logic;
+ x_out : out sfixed;
+ y_out : out sfixed
+ );
+ END COMPONENT;
+
+ -------------------------------------------------------------------------------
+ type coeff_array_t is array (natural range <>) of sfixed(SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac));
+ type stages_array_t is array (natural range <>) of sfixed(SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac));
+
+ constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
+ constant fir_stage_mode : fir_stage_mode_t := transposed;
+
+ SIGNAL x_out : sfixed(SFix_high(nbits_out, nbits_out_frac) downto SFix_low(nbits_out, nbits_out_frac));
+
+ SIGNAL x : stages_array_t(0 to ntaps-2);
+ SIGNAL y : stages_array_t(0 to ntaps-2);
+ SIGNAL h : coeff_array_t(0 to ntaps-1);
+
+ -------------------------------------------------------------------------------
+begin
+
+ -- Assign coefficients
+ assign_coeffs:
+ for i in 0 to ntaps-1 generate
+ h(i) <= to_sfixed(h_in, i);
+ end generate;
+
+ ----------------------------------------
+ -- Instantiate the FIR stages
+ ----------------------------------------
+ uut_first_stage: fir_stage
+ GENERIC MAP
+ (
+ nbits_in => nbits_in,
+ nbits_in_frac => nbits_in_frac,
+ nbits_out => nbits_stages,
+ nbits_out_frac => nbits_stages_frac,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ fir_mode => fir_stage_mode,
+ rounding => false,
+ saturating => false
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => in_valid,
+ x_in => d_in,
+ y_in => zero_in,
+ h_in => h(ntaps-1),
+ out_valid => out_valid,
+ x_out => x(0),
+ y_out => y(0)
+ );
+
+ ----------------------------------------
+ gen_stages:
+ for i in 1 to ntaps-2 generate
+ uut_stages: fir_stage
+ GENERIC MAP
+ (
+ nbits_in => nbits_stages,
+ nbits_in_frac => nbits_stages_frac,
+ nbits_out => nbits_stages,
+ nbits_out_frac => nbits_stages_frac,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ fir_mode => fir_stage_mode,
+ rounding => false,
+ saturating => false
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => in_valid,
+ x_in => x(i-1),
+ y_in => y(i-1),
+ h_in => h(ntaps-i-1),
+ out_valid => open,
+ x_out => x(i),
+ y_out => y(i)
+ );
+ end generate;
+
+ ----------------------------------------
+ uut_last_stage: fir_stage
+ GENERIC MAP
+ (
+ nbits_in => nbits_stages,
+ nbits_in_frac => nbits_stages_frac,
+ nbits_out => nbits_out,
+ nbits_out_frac => nbits_out_frac,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ fir_mode => fir_stage_mode,
+ rounding => rounding,
+ saturating => saturating
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => in_valid,
+ x_in => x(ntaps-2),
+ y_in => y(ntaps-2),
+ h_in => h(0),
+ out_valid => open,
+ x_out => x_out,
+ y_out => d_out
+ );
+
+ ----------------------------------------
+ -- Finished instantiation
+ ----------------------------------------
+
+end Behavioral;
diff --git a/lib/filter/src/fir_parallel_pkg.vhd b/lib/filter/src/fir_parallel_pkg.vhd
new file mode 100644
index 0000000..1f8c44c
--- /dev/null
+++ b/lib/filter/src/fir_parallel_pkg.vhd
@@ -0,0 +1,76 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.fixed_pkg.all;
+use work.filter_pkg.all;
+
+-------------------------------------------------------------------------------
+package fir_parallel_pkg is
+
+ type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
+ type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
+
+ type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym);
+
+ function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t;
+ function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t;
+
+ -- Slicing functions for unconstrained array types
+ function to_ufixed(src : ufixed_array_t; index : integer) return ufixed;
+ function to_sfixed(src : sfixed_array_t; index : integer) return sfixed;
+
+end; -- package fir_parallel_pkg;
+
+-------------------------------------------------------------------------------
+package body fir_parallel_pkg is
+
+ function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is
+ variable res : sfixed_array_t(0 to x'length-1, proto'range);
+ variable tt : sfixed(proto'range);
+ begin
+ for i in x'range loop
+ tt := to_sfixed(x(i), proto);
+ for j in proto'range loop
+ res(i,j) := tt(j);
+ end loop;
+ end loop;
+ return res;
+ end to_sfixed_array;
+
+ ---------------------------------------------------------------------------
+ function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is
+ variable p : sfixed(SFix_high(nbits, nbits_int) downto SFix_low(nbits, nbits_int));
+ begin
+ return to_sfixed_array(x, p);
+ end to_sfixed_array;
+
+ -------------------------------------------------------------------------------
+ -- ufixed <= ufixed_array(i)
+ function to_ufixed(src : ufixed_array_t; index : integer) return ufixed is
+ variable dst : ufixed(src'range(2));
+ begin
+ for j in src'range(2) loop
+ dst(j) := src(index, j);
+ end loop;
+
+ return dst;
+
+ end to_ufixed;
+
+ -------------------------------------------------------------------------------
+ -- sfixed <= sfixed_array(i)
+ function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is
+ variable dst : sfixed(src'range(2));
+ begin
+ for j in src'range(2) loop
+ dst(j) := src(index, j);
+ end loop;
+
+ return dst;
+
+ end to_sfixed;
+
+end; -- package fir_parallel_pkg;
+
+-------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_stage.vhd b/lib/filter/src/fir_stage.vhd
new file mode 100644
index 0000000..c8c4a7c
--- /dev/null
+++ b/lib/filter/src/fir_stage.vhd
@@ -0,0 +1,150 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: fir_stage - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.fir_stage_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity fir_stage is
+Generic
+(
+ nbits_in : integer := 12;
+ nbits_in_frac : integer := 12;
+ nbits_out : integer := 12;
+ nbits_out_frac : integer := 12;
+ has_in_reg : boolean := false;
+ has_pipe_reg : boolean := false;
+ has_out_reg : boolean := false;
+ fir_mode : fir_stage_mode_t := transposed;
+ rounding : boolean := true;
+ saturating : boolean := true
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ in_valid : in std_logic;
+ x_in : in sfixed;
+ y_in : in sfixed;
+ h_in : in sfixed;
+ out_valid : out std_logic;
+ x_out : out sfixed;
+ y_out : out sfixed;
+ y_out_clr : in std_logic
+);
+end fir_stage;
+
+architecture Behavioral of fir_stage is
+
+signal xin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+signal yin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+signal hin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+signal prod : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+signal valid, p_valid : std_logic;
+------------------------------------------------------------
+begin
+
+
+------------------------------------------------------------
+ proc_in_reg_y: process(clk)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' or y_out_clr = '1' then
+ yin <= to_sfixed(0, yin);
+ else
+ yin <= resize(y_in, yin);
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_in_reg_hx: process(srst, clk, in_valid, x_in, h_in)
+ variable p : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ begin
+ if has_in_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ xin <= to_sfixed(0, xin);
+ hin <= to_sfixed(0, hin);
+ valid <= '0';
+ else
+ valid <= in_valid;
+ if in_valid = '1' then
+ xin <= resize(x_in, xin);
+ hin <= resize(h_in, hin);
+ end if;
+ end if;
+ end if;
+ else
+ xin <= resize(x_in, xin);
+ hin <= resize(h_in, hin);
+ valid <= in_valid;
+ end if;
+ x_out <= resize(x_in, p);
+
+ end process;
+
+------------------------------------------------------------
+ proc_pipe_reg: process(srst, clk, valid, xin, hin)
+ variable p : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ begin
+ p := resize(xin * hin, p);
+ if has_pipe_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ prod <= to_sfixed(0, prod);
+ p_valid <= '0';
+ else
+ prod <= p;
+ p_valid <= valid;
+ end if;
+ end if;
+ else
+ prod <= p;
+ p_valid <= valid;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_out_reg: process(srst, clk, p_valid, prod, yin)
+ variable yout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ begin
+ yout := resize(yin + prod, yout, rounding, saturating);
+-- if rising_edge(clk) then
+-- if srst = '1' or y_out_clr = '1' then
+-- y_out <= to_sfixed(0, yout);
+-- out_valid <= '0';
+-- else
+-- y_out <= yout;
+-- out_valid <= p_valid;
+-- end if;
+-- end if;
+ out_valid <= p_valid;
+ y_out <= yout;
+ end process;
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/filter/src/fir_stage_pkg.vhd b/lib/filter/src/fir_stage_pkg.vhd
new file mode 100644
index 0000000..8bccba2
--- /dev/null
+++ b/lib/filter/src/fir_stage_pkg.vhd
@@ -0,0 +1,38 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.fixed_pkg.all;
+
+package fir_stage_pkg is
+
+type fir_stage_mode_t is (transposed, systolic);
+
+ -------------------------------------------------------------
+ -- Constructor helpers
+ -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
+ function uproto (nbits : integer; nbits_frac : integer) return ufixed;
+
+ -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
+ function sproto (nbits : integer; nbits_frac : integer) return sfixed;
+
+end; -- package fir_stage_pkg;
+
+package body fir_stage_pkg is
+
+ -------------------------------------------------------------
+ -- Constuctor helpers
+ function uproto (nbits : integer; nbits_frac : integer) return ufixed is
+ constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0');
+ begin
+ return result(nbits-nbits_frac-1 downto -nbits_frac);
+ end uproto;
+
+ -------------------------------------------------------------
+ function sproto (nbits : integer; nbits_frac : integer) return sfixed is
+ constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0');
+ begin
+ return result(nbits-nbits_frac downto -nbits_frac+1);
+ end sproto;
+
+end; -- package fir_stage_pkg;
diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd
new file mode 100644
index 0000000..2621a05
--- /dev/null
+++ b/lib/filter/src/tb_fir_iterative.vhd
@@ -0,0 +1,231 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:16:42 13.05.2007
+-- Design Name: tb_fir_stage
+-- Module Name: tb_fir_stage.vhd
+-- Project Name: fir_stage
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; -- Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.filter_pkg.all;
+use work.fir_stage_pkg.all;
+use work.fir_iterative_pkg.all;
+
+use work.PCK_FIO.all;
+
+ENTITY tb_fir_iterative IS
+ Generic (
+ ntaps : integer := 11;
+ nbits_in : integer := 15;
+ nbits_in_frac : integer := 15;
+ nbits_stages : integer := 15;
+ nbits_stages_frac : integer := 15;
+ nbits_out : integer := 15;
+ nbits_out_frac : integer := 15;
+ fir_mode : fir_iterative_mode_t := symmetric;
+ rounding : boolean := true;
+ saturating : boolean := true
+ );
+END tb_fir_iterative;
+
+ARCHITECTURE behavior OF tb_fir_iterative IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT fir_iterative
+ GENERIC
+ (
+ ntaps : integer;
+ nbits_in : integer;
+ nbits_in_frac : integer;
+ nbits_stages : integer;
+ nbits_stages_frac : integer;
+ nbits_out : integer;
+ nbits_out_frac : integer;
+ fir_mode : fir_iterative_mode_t;
+ rounding : boolean;
+ saturating : boolean
+ );
+ PORT
+ (
+ srst : in std_logic;
+ clk : in std_logic;
+ h_din : in sfixed;
+ h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
+ ready : out std_logic;
+ x_valid : in std_logic;
+ x_din : in sfixed;
+ y_dout_valid : out std_logic;
+ y_dout : out sfixed
+ );
+ END COMPONENT;
+
+ -------------------------------------------------------------------------------
+ --Constants
+ constant nsamples : integer := 32;
+
+ constant PERIOD : time := 10 ns;
+ constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
+
+ --Inputs
+ SIGNAL clk : std_logic := '0';
+ SIGNAL srst : std_logic := '1';
+ SIGNAL x_valid : std_logic := '0';
+ SIGNAL h_din : sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
+ SIGNAL x_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+
+ --Outputs
+ SIGNAL y_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ SIGNAL y_valid : std_logic;
+ SIGNAL ready : std_logic;
+
+ SIGNAL fileout_enable : std_logic := '1';
+
+ -- Test coefficients
+-- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, 10, 0.999)(0 to ntaps_addr(ntaps, fir_mode)-1);
+ SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1);
+-- SIGNAL coeffs : real_array_t(0 to ntaps-1) := FilterTestCoef(ntaps);
+ signal x_input : real_array_t(0 to nsamples-1) :=
+ (
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.9999,
+ -0.0000,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0,
+ 0.0
+
+ );
+ type ymem_t is array (0 to nsamples-1) of sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ signal ymem : ymem_t;
+
+ signal y_cnt : integer ;
+ SIGNAL xi, yo : real := 0.0;
+ SIGNAL h_addr : unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0);
+
+ -- file I/O
+ subtype sample_t is integer range -32768 to 32767;
+ type file_t is file of sample_t;
+
+ -------------------------------------------------------------------------------
+BEGIN
+
+ xi <= to_real(x_din);
+ yo <= to_real(y_dout);
+
+ ----------------------------------------
+ -- Instantiate the Unit Under Test (UUT)
+ ----------------------------------------
+ uut_fir_iterative: fir_iterative
+ GENERIC MAP
+ (
+ ntaps => ntaps,
+ nbits_in => nbits_in,
+ nbits_in_frac => nbits_in_frac,
+ nbits_out => nbits_out,
+ nbits_out_frac => nbits_out_frac,
+ nbits_stages => nbits_stages,
+ nbits_stages_frac => nbits_stages_frac,
+ fir_mode => fir_mode,
+ rounding => rounding,
+ saturating => saturating
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ h_din => h_din,
+ h_addr_out => h_addr,
+ ready => ready,
+ x_valid => x_valid,
+ x_din => x_din,
+ y_dout_valid => y_valid,
+ y_dout => y_dout
+ );
+
+ ----------------------------------------
+ -- Finished instantiation
+ ----------------------------------------
+ tb_clk : PROCESS
+ BEGIN
+ clk <= not clk;
+ wait for PERIOD/2;
+ END PROCESS;
+
+ tb : PROCESS
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 4*PERIOD;
+ srst <= '0';
+ ------------------------------------------
+ wait for 2*PERIOD;
+
+ for i in 0 to nsamples-1 loop
+ if i = nsamples/2 then
+ wait for 43*PERIOD;
+ end if;
+ ------------------------------------------
+ wait until rising_edge(clk) and ready = '1';
+ x_din <= to_sfixed(x_input(i), x_din);
+ x_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_valid <= '0';
+ end loop;
+
+ assert false report "Test finished" severity error;
+ wait;
+ END PROCESS;
+
+ process(srst, clk, y_valid)
+ begin
+ if rising_edge(clk) then
+ h_din <= to_sfixed(coeffs(to_integer(h_addr)), h_din);
+ if srst = '1' then
+ y_cnt <= 0;
+
+ elsif y_valid = '1' then
+ ymem(y_cnt) <= y_dout;
+ y_cnt <= y_cnt + 1;
+ end if;
+ end if;
+ end process;
+
+END;
diff --git a/lib/filter/src/tb_fir_parallel.vhd b/lib/filter/src/tb_fir_parallel.vhd
new file mode 100644
index 0000000..bb87e21
--- /dev/null
+++ b/lib/filter/src/tb_fir_parallel.vhd
@@ -0,0 +1,189 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:16:42 13.05.2007
+-- Design Name: tb_fir_stage
+-- Module Name: tb_fir_stage.vhd
+-- Project Name: fir_stage
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; -- Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.fir_parallel_pkg.all;
+use work.filter_pkg.all;
+
+use work.PCK_FIO.all;
+
+ENTITY tb_fir_parallel IS
+ Generic (
+ ntaps : integer := 33;
+ nbits_in : integer := 15;
+ nbits_in_frac : integer := 15;
+ nbits_stages : integer := 16;
+ nbits_stages_frac : integer := 15;
+ nbits_out : integer := 15;
+ nbits_out_frac : integer := 15;
+ has_in_reg : boolean := false;
+ has_pipe_reg : boolean := true;
+ has_out_reg : boolean := false;
+ fir_mode : fir_parallel_mode_t := transposed;
+ rounding : boolean := true;
+ saturating : boolean := true
+ );
+END tb_fir_parallel;
+
+ARCHITECTURE behavior OF tb_fir_parallel IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT fir_parallel
+ GENERIC
+ (
+ ntaps : integer;
+ nbits_in : integer;
+ nbits_in_frac : integer;
+ nbits_stages : integer;
+ nbits_stages_frac : integer;
+ nbits_out : integer;
+ nbits_out_frac : integer;
+ has_in_reg : boolean;
+ has_pipe_reg : boolean;
+ has_out_reg : boolean;
+ fir_mode : fir_parallel_mode_t;
+ rounding : boolean;
+ saturating : boolean
+ );
+ PORT
+ (
+ srst : in std_logic;
+ clk : in std_logic;
+ h_in : in sfixed_array_t;
+ in_valid : in std_logic;
+ d_in : in sfixed;
+ out_valid : out std_logic;
+ d_out : out sfixed
+ );
+ END COMPONENT;
+
+ -------------------------------------------------------------------------------
+ --Constants
+ constant PERIOD : time := 10 ns;
+ constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
+
+ --Inputs
+ SIGNAL clk : std_logic := '0';
+ SIGNAL srst : std_logic := '1';
+ SIGNAL in_valid : std_logic := '0';
+ SIGNAL x_in : sfixed(SFix_high(nbits_in, nbits_in_frac) downto SFix_low(nbits_in, nbits_in_frac));
+
+ --Outputs
+ SIGNAL y_out : sfixed(SFix_high(nbits_out, nbits_out_frac) downto SFix_low(nbits_out, nbits_out_frac));
+ SIGNAL out_valid : std_logic := '0';
+
+ SIGNAL fileout_enable : std_logic := '1';
+
+ -- Test coefficients
+ SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac);
+
+ SIGNAL xi, yo : real := 0.0;
+
+ -- file I/O
+ subtype sample_t is integer range -32768 to 32767;
+ type file_t is file of sample_t;
+
+ -------------------------------------------------------------------------------
+BEGIN
+
+ xi <= to_real(x_in);
+ yo <= to_real(y_out);
+
+ ----------------------------------------
+ -- Instantiate the Unit Under Test (UUT)
+ ----------------------------------------
+ uut_fir_parallel: fir_parallel
+ GENERIC MAP
+ (
+ ntaps => ntaps,
+ nbits_in => nbits_in,
+ nbits_in_frac => nbits_in_frac,
+ nbits_out => nbits_out,
+ nbits_out_frac => nbits_out_frac,
+ nbits_stages => nbits_stages,
+ nbits_stages_frac => nbits_stages_frac,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ fir_mode => fir_mode,
+ rounding => rounding,
+ saturating => saturating
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ h_in => coeff_in,
+ in_valid => in_valid,
+ d_in => x_in,
+ out_valid => out_valid,
+ d_out => y_out
+ );
+
+ ----------------------------------------
+ -- Finished instantiation
+ ----------------------------------------
+ tb_clk : PROCESS
+ BEGIN
+ clk <= not clk;
+ wait for PERIOD/2;
+ END PROCESS;
+
+ tb : PROCESS
+ file fi : file_t open read_mode is "wav_in.dat";
+ variable si : sample_t;
+
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 4*PERIOD;
+ srst <= '0';
+ ------------------------------------------
+ wait for 2*PERIOD;
+
+ while not endfile(fi) loop
+ read(fi, si);
+ x_in <= to_sfixed(to_signed(si, 16));
+ in_valid <= '1';
+ wait for PERIOD;
+ wait until rising_edge(clk);
+ end loop;
+ ------------------------------------------
+ in_valid <= '0';
+
+ wait for 20*PERIOD;
+
+ assert false report "Test finished" severity error;
+ wait;
+ END PROCESS;
+
+ tb_fo : PROCESS(clk, fileout_enable, out_valid)
+ file fo : file_t open write_mode is "wav_out.dat";
+ variable so : sample_t;
+
+ BEGIN
+ if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
+ so := to_integer(y_out);
+ write(fo, so);
+ end if;
+
+ END PROCESS;
+
+END;
diff --git a/lib/filter/src/tb_fir_stage.vhd b/lib/filter/src/tb_fir_stage.vhd
new file mode 100644
index 0000000..159f13a
--- /dev/null
+++ b/lib/filter/src/tb_fir_stage.vhd
@@ -0,0 +1,268 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:16:42 13.05.2007
+-- Design Name: tb_fir_stage
+-- Module Name: tb_fir_stage.vhd
+-- Project Name: fir_stage
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; -- Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.fir_stage_pkg.all;
+use work.filter_pkg.all;
+
+use work.PCK_FIO.all;
+
+ENTITY tb_fir_stage IS
+ Generic (
+ ntaps : integer := 33;
+ nbits_in : integer := 24;
+ nbits_in_frac : integer := 23;
+ nbits_stages : integer := 25;
+ nbits_stages_frac : integer := 23;
+ nbits_out : integer := 24;
+ nbits_out_frac : integer := 22;
+ has_in_reg : boolean := true;
+ has_pipe_reg : boolean := true;
+ has_out_reg : boolean := false;
+ fir_mode : fir_stage_mode_t := transposed;
+ rounding : boolean := true;
+ saturating : boolean := true
+ );
+END tb_fir_stage;
+
+ARCHITECTURE behavior OF tb_fir_stage IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT fir_stage
+ GENERIC
+ (
+ nbits_in : integer;
+ nbits_in_frac : integer;
+ nbits_out : integer;
+ nbits_out_frac : integer;
+ has_in_reg : boolean;
+ has_pipe_reg : boolean;
+ has_out_reg : boolean;
+ fir_mode : fir_stage_mode_t;
+ rounding : boolean;
+ saturating : boolean
+ );
+ PORT
+ (
+ srst : in std_logic;
+ clk : in std_logic;
+ in_valid : in std_logic;
+ x_in : in sfixed;
+ y_in : in sfixed;
+ h_in : in sfixed;
+ out_valid : out std_logic;
+ x_out : out sfixed;
+ y_out : out sfixed
+ );
+ END COMPONENT;
+
+ type stages_t is array (natural range <>) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low);
+
+ --Constants
+ constant PERIOD : time := 10 ns;
+ constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
+
+ --Inputs
+ SIGNAL clk : std_logic := '0';
+ SIGNAL srst : std_logic := '1';
+ SIGNAL in_valid : std_logic := '0';
+ SIGNAL x_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+
+ --Outputs
+ SIGNAL x_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ SIGNAL y_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ SIGNAL out_valid : std_logic := '0';
+
+ SIGNAL x : stages_t(0 to ntaps-2);
+ SIGNAL y : stages_t(0 to ntaps-2);
+
+ SIGNAL fileout_enable : std_logic := '1';
+
+ -- Test coefficients
+ function to_sfixed(x_real : real_array_t) return stages_t is
+ variable res : stages_t(x_real'range);
+ begin
+ for i in x_real'range loop
+ res(i) := to_sfixed(x_real(i), res(i), true, true);
+ end loop;
+
+ return res;
+ end to_sfixed;
+
+ constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0));
+
+ SIGNAL xi, yo : real := 0.0;
+
+BEGIN
+
+ xi <= to_real(x_in);
+ yo <= to_real(y_out);
+
+ ----------------------------------------
+ -- Instantiate the Unit Under Test (UUT)
+ ----------------------------------------
+ uut_first_stage: fir_stage
+ GENERIC MAP
+ (
+ nbits_in => nbits_in,
+ nbits_in_frac => nbits_in_frac,
+ nbits_out => nbits_stages,
+ nbits_out_frac => nbits_stages_frac,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ fir_mode => fir_mode,
+ rounding => false,
+ saturating => false
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => in_valid,
+ x_in => x_in,
+ y_in => zero_in,
+ h_in => h(ntaps-1),
+ out_valid => out_valid,
+ x_out => x(0),
+ y_out => y(0)
+ );
+
+ ----------------------------------------
+ gen_stages:
+ for i in 1 to ntaps-2 generate
+ uut_stages: fir_stage
+ GENERIC MAP
+ (
+ nbits_in => nbits_stages,
+ nbits_in_frac => nbits_stages_frac,
+ nbits_out => nbits_stages,
+ nbits_out_frac => nbits_stages_frac,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ fir_mode => fir_mode,
+ rounding => false,
+ saturating => false
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => in_valid,
+ x_in => x(i-1),
+ y_in => y(i-1),
+ h_in => h(ntaps-i-1),
+ out_valid => open,
+ x_out => x(i),
+ y_out => y(i)
+ );
+ end generate;
+
+ ----------------------------------------
+ uut_last_stage: fir_stage
+ GENERIC MAP
+ (
+ nbits_in => nbits_stages,
+ nbits_in_frac => nbits_stages_frac,
+ nbits_out => nbits_out,
+ nbits_out_frac => nbits_out_frac,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ fir_mode => fir_mode,
+ rounding => rounding,
+ saturating => saturating
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => in_valid,
+ x_in => x(ntaps-2),
+ y_in => y(ntaps-2),
+ h_in => h(0),
+ out_valid => open,
+ x_out => x_out,
+ y_out => y_out
+ );
+
+ ----------------------------------------
+ -- Finished instantiation
+ ----------------------------------------
+ tb_clk : PROCESS
+ BEGIN
+ clk <= not clk;
+ wait for PERIOD/2;
+ END PROCESS;
+
+ tb : PROCESS
+
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 4*PERIOD;
+ srst <= '0';
+ ------------------------------------------
+ wait for 2*PERIOD;
+
+ x_in <= to_sfixed(0.0, x_in);
+
+ wait until rising_edge(clk);
+ in_valid <= '1';
+
+ wait until rising_edge(clk);
+ x_in <= to_sfixed(0.0, x_in);
+
+ wait for 20*PERIOD;
+ wait until rising_edge(clk);
+ x_in <= to_sfixed(0.0, x_in);
+ wait until rising_edge(clk);
+ x_in <= to_sfixed(1.0, x_in);
+ wait until rising_edge(clk);
+ x_in <= to_sfixed(0.0, x_in);
+ wait until rising_edge(clk);
+ x_in <= to_sfixed(0.0, x_in);
+ wait until rising_edge(clk);
+ x_in <= to_sfixed(0.0, x_in);
+
+ wait for 150*PERIOD;
+
+ wait until rising_edge(clk);
+ in_valid <= '0';
+
+ wait for 20*PERIOD;
+
+ assert false report "Test finished" severity error;
+ wait;
+ END PROCESS;
+
+ tb_fo : PROCESS(clk, fileout_enable, out_valid)
+ file RESULT_FIR: text open write_mode is "fir.txt";
+ variable L: line;
+
+ BEGIN
+ if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
+ fprint(RESULT_FIR, L,"%s\n", REAL'image(yo));
+ end if;
+
+ END PROCESS;
+
+END;
diff --git a/lib/fix_std/fix_std.vhd b/lib/fix_std/fix_std.vhd
new file mode 100644
index 0000000..6397ebc
--- /dev/null
+++ b/lib/fix_std/fix_std.vhd
@@ -0,0 +1,1007 @@
+---------------------------------------------------------------------
+--
+-- Package fix_std
+-- Fixed point arithmetic based on numeric_std
+--
+---------------------------------------------------------------------
+--
+-- This document describes a VHDL package of definitions and subprograms
+-- intended to support the use of fixed-point arithmetic in test benches
+-- and synthesisable designs. This document and the package it describes
+-- are made freely available to the HDL design community without warranty
+-- of any kind. You are welcome to make use of this information for your
+-- own private study and in your own designs. If you make use of the
+-- package, you accept sole responsibility for its fitness for purpose
+-- and its suitability in your application. You are free to modify the
+-- package in any way, and to record your contribution to it, but this
+-- notice must appear in a prominent place in any modified or derived
+-- version of the package or its supporting documentation.
+--
+-- The author wishes to thank his employer Doulos Ltd for making
+-- available the facilities used to develop, test and distribute this
+-- package. However, Doulos Ltd accepts no responsibility for the
+-- package's contents and cannot support it in any way.
+--
+---------------------------------------------------------------------
+-- Revision information:
+--
+-- Version 0.1 06-May-2003
+-- Alpha version, for review
+-- No division operators are provided, pending detailed
+-- consultation on their functionality.
+-- Some subprogram implementations are unnecessarily inefficient.
+-- Version 0.2 11-Jun-2003
+-- Fixes aiming to make the package portable across all synthesis tools:
+-- * Removed deferred constants, made them package constants
+-- * Removed all variable initialisations in procedures, made them
+-- procedural initialisations in the code
+---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package fix_std is
+
+ --------------------------------------------------------------------
+
+ -- Integer subtype specifying legal values for a bit index.
+ -- At present it's restricted to 'natural' to conform with
+ -- the behaviour of mainstream synthesis tools. For simulation,
+ -- or in the future when synthesis tools are able to cope, it
+ -- would be possible to change this subtype to be the full
+ -- integer range, thus allowing negative subscripts for
+ -- fraction bits.
+ --
+ subtype Fix_Subscr is natural;
+
+ -- Fixed-point offset, the bit number (subscript) used for
+ -- the bit in a UFix or SFix vector having binary weight 2^0
+ -- (the units bit).
+ --
+ constant FixP: Fix_Subscr := 100;
+
+ -- Type declarations for the basic unsigned and signed fixed point
+ -- data types:
+ --
+ type UFix is array (Fix_Subscr range <>) of std_logic;
+ type SFix is array (Fix_Subscr range <>) of std_logic;
+
+ -- Type declarations for control of rounding and overflow modes:
+ --
+ type Fix_Rounding_Mode is (
+ clip_LS, -- Throw away unwanted least significant bits
+ towards_zero, -- Round towards zero - same as clip_LS for UFix
+ to_nearest -- Round to nearest. Exact halves round up.
+ );
+ type Fix_Overflow_Mode is (
+ clip_MS, -- Throw away unwanted most significant bits
+ saturate -- Saturate overflow to nearest representable value
+ );
+
+ -- Defaults for these modes:
+ --
+ constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS;
+ constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS;
+
+ --------------------------------------------------------------------
+
+ ---------------------------
+ -- E. Extraction functions
+ ---------------------------
+
+ -- E.1. Return the integral part of a UFix value
+ function Int(U: UFix) return UFix;
+
+ -- E.2. Return the fractional part of a UFix value
+ function Frac(U: UFix) return UFix;
+
+ -- E.3. Return the integral part of a SFix value
+ function Int(S: SFix) return SFix;
+
+ -- E.4. Return the fractional part of a SFix value
+ function Frac(S: SFix) return UFix;
+
+ -- E.5. Widen a SFix value if necessary so that
+ -- its range adjoins or spans the binary point
+ function Span(S: SFix) return SFix;
+
+ -- E.6. Widen a UFix value if necessary so that
+ -- its range adjoins or spans the binary point
+ function Span(U: UFix) return UFix;
+
+ ---------------------------
+ -- T. Conversion functions
+ ---------------------------
+
+ -- T.1 to T.8: Unsigned conversions
+ --
+ -- T.1. Resizing an existing UFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_UFix(
+ N : UFix;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return UFix;
+
+ -- T.2. Resizing an existing SFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_UFix(
+ N : SFix;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return UFix;
+
+ -- T.3. Conversion from integer to UFix. Provide number of
+ -- integer bits and number of fraction bits. Note that
+ -- negative input is tolerated!
+ --
+ function to_UFix(
+ N : integer;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return UFix;
+
+ -- T.4. Conversion from unsigned to UFix. Provide subscripts of
+ -- MS and (optionally) LS bit of the resulting UFix.
+ --
+ function to_UFix(
+ N : unsigned;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return UFix;
+
+ -- T.5. Conversion from unsigned to UFix. Automatically set the
+ -- range of the resulting UFix to match the unsigned value,
+ -- as an integral UFix value with no fraction bits.
+ --
+ function to_UFix( N : unsigned ) return UFix;
+
+ -- T.6. Conversion from UFix to unsigned. All integer bits are
+ -- preserved (including adding LS scale bits if necessary).
+ --
+ function to_unsigned(
+ N : UFix;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return unsigned;
+
+ -- T.7. Conversion from UFix to unsigned. Caller specifies
+ -- required number of bits in unsigned result.
+ --
+ function to_unsigned(
+ N : UFix;
+ bits : positive;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return unsigned;
+
+ -- T.8. Conversion from UFix to integer. Up to 31 integer bits are
+ -- preserved (including adding LS scale bits if necessary).
+ --
+ function to_integer(
+ N : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return integer;
+
+
+ -- T.9 to T.16: Signed conversions
+ --
+ -- T.9. Resizing an existing UFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_SFix(
+ N : UFix;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return SFix;
+
+ -- T.10. Resizing an existing SFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_SFix(
+ N : SFix;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return SFix;
+
+ -- T.11. Conversion from integer to SFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_SFix(
+ N : integer;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return SFix;
+
+ -- T.12. Conversion from signed to SFix. Provide subscripts of
+ -- MS and (optionally) LS bit of the resulting SFix.
+ --
+ function to_SFix(
+ N : signed;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return SFix;
+
+ -- T.13. Conversion from signed to SFix. Automatically set the
+ -- range of the resulting SFix to match the signed value,
+ -- as an integral SFix value with no fraction bits.
+ --
+ function to_SFix( N : signed ) return SFix;
+
+ -- T.14. Conversion from SFix to signed. All integer bits are
+ -- preserved (including adding LS scale bits if necessary).
+ --
+ function to_signed(
+ N : SFix;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return signed;
+
+ -- T.15. Conversion from SFix to signed. Caller specifies
+ -- required number of bits in signed result.
+ --
+ function to_signed(
+ N : SFix;
+ bits : positive;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return signed;
+
+ -- T.16. Conversion from SFix to integer. Up to 32 integer bits are
+ -- preserved (including adding LS scale bits if necessary).
+ --
+ function to_integer(
+ N : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return integer;
+
+ -- T.17. Conversion from UFix to SFix. This simply adds
+ -- an extra more significant bit, set to zero.
+ --
+ function to_SFix(U: UFix) return SFix;
+
+ ----------------------------------
+ -- V. Copy-to-variable procedures
+ ----------------------------------
+
+ -- Range-aware copying of an expression into a variable. The
+ -- ranges of destination variable and source expression are
+ -- used to determine correct rounding, overflow and scaling
+ -- behaviour.
+
+ -- V.1 to V.5: Copy an expression into a UFix variable
+ --
+
+ -- V.1. Copy UFix to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+ --
+ -- V.2. Copy SFix to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- V.3. Copy UNSIGNED to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : unsigned;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- V.4. Copy SIGNED to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : signed;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- V.5. Copy integer to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : integer;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- V.6 to V.10: Copy an expression into a SFix variable
+ --
+
+ -- V.6. Copy UFix to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- V.7. Copy SFix to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- V.8. Copy UNSIGNED to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : unsigned;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- V.9. Copy SIGNED to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : signed;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- V.10. Copy integer to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : integer;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+
+ --------------------------------
+ -- S. Copy-to-signal procedures
+ --------------------------------
+ --
+ -- Range-aware copying of an expression into a signal. The
+ -- ranges of destination signal and source expression are
+ -- used to determine correct rounding, overflow and scaling
+ -- behaviour.
+
+ -- S.1 to S.5: Copy an expression into a UFix signal
+ --
+
+ -- S.1. Copy UFix to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.1. Copy SFix to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.3. Copy UNSIGNED to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : unsigned;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.4. Copy SIGNED to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : signed;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.5. Copy integer to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : integer;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.6 to S.10: Copy an expression into a SFix signal
+ --
+
+ -- S.6. Copy UFix to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.7. Copy SFix to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.8. Copy UNSIGNED to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : unsigned;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.9. Copy SIGNED to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : signed;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+ -- S.10. Copy integer to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : integer;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ );
+
+
+ ------------------------------------------------------------------
+ -- A. Arithmetic operations involving UFix, SFix and other
+ -- numeric types.
+ -- The operators are overloaded for most of the sensible
+ -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
+ --
+ -- IMPORTANT NOTE:
+ -- Arithmetic operators return a result that is wide enough
+ -- and precise enough so that no information is lost. THIS IS
+ -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std.
+ -- In the detailed description that follow, "scaling" means
+ -- the numerical value (weight) of the least significant bit
+ -- in a fixed-point value.
+ --
+ -- ADDITION returns a result whose least significant bit
+ -- is the same as the least significant bit in either operand,
+ -- and whose most significant bit is one position higher than
+ -- the most significant bit in either operand. Addition of
+ -- two operands having the same bounds therefore results in
+ -- a growth of one bit at the most significant end.
+ --
+ -- SUBTRACTION where one or both operands are signed behaves
+ -- in the same way as addition. Subtraction where both operands
+ -- are unsigned returns a result whose most significant bit
+ -- position is the same as the most significant bit in either
+ -- operand, and whose least significant bit is the same as the
+ -- least significant bit in either operand.
+ --
+ -- MULTIPLICATION returns a result whose width is the sum of
+ -- the widths of its two operands, and whose scaling is the
+ -- product of its two operands' scalings.
+ --
+ -- UNARY NEGATION always gives a result having one more
+ -- significant bit than the operand.
+ --
+ -- ABSOLUTE VALUE always gives a result having exactly the
+ -- same subtype as its operand.
+ --
+ -- In binary operations where one operand is a fixed-point type
+ -- and the other is an integer numeric type, the integer operand
+ -- is first converted to a fixed-point type of the same subtype
+ -- as the other operand using Copy_V with default rounding and
+ -- overflow modes. The operation is then performed between two
+ -- fixed-point operands in the normal way.
+ --
+ ------------------------------------------------------------------
+
+
+ ------------------------------------
+ -- A.1. Unary "-" negation operator
+ ------------------------------------
+
+ -- A.1.1. SFix := - UFix
+ function "-" (R: UFix) return SFix;
+
+ -- A.1.2. SFix := - SFix
+ function "-" (R: SFix) return SFix;
+
+
+ --------------------------------------------
+ -- A.2. Unary "abs" absolute-value operator
+ --------------------------------------------
+
+ -- A.2.1. SFix := abs SFix
+ function "abs" (R: SFix) return SFix;
+
+
+ -------------------------------------
+ -- A.3. Binary "+" addition operator
+ -------------------------------------
+
+ -- A.3.1. UFix := UFix + UFix
+ function "+" (L: UFix; R: UFix) return UFix;
+
+ -- A.3.2. UFix := UFix + unsigned
+ function "+" (L: UFix; R: unsigned) return UFix;
+
+ -- A.3.3. UFix := unsigned + UFix
+ function "+" (L: unsigned; R: UFix) return UFix;
+
+ -- A.3.4. UFix := UFix + natural
+ function "+" (L: UFix; R: natural) return UFix;
+
+ -- A.3.5. UFix := natural + UFix
+ function "+" (L: natural; R: UFix) return UFix;
+
+ -- A.3.6. SFix := SFix + SFix
+ function "+" (L: SFix; R: SFix) return SFix;
+
+ -- A.3.7. SFix := SFix + UFix
+ function "+" (L: SFix; R: UFix) return SFix;
+
+ -- A.3.8. SFix := UFix + SFix
+ function "+" (L: UFix; R: SFix) return SFix;
+
+ -- A.3.9. SFix := SFix + signed
+ function "+" (L: SFix; R: signed) return SFix;
+
+ -- A.3.10. SFix := signed + SFix
+ function "+" (L: signed; R: SFix) return SFix;
+
+ -- A.3.11. SFix := SFix + integer
+ function "+" (L: SFix; R: integer) return SFix;
+
+ -- A.3.12. SFix := integer + SFix
+ function "+" (L: integer; R: SFix) return SFix;
+
+
+ ----------------------------------------
+ -- A.4. Binary "-" subtraction operator
+ ----------------------------------------
+ --
+ -- NOTE: There is a special problem with subtraction
+ -- operators that return a UFix result if that result
+ -- goes negative. Our arbitrary decision is that we
+ -- truncate most-significant bits in this case. If you
+ -- wish to avoid the risk of this arbitrarily-defined
+ -- truncation behaviour, change one or more of your
+ -- operands to SFix and get a SFix result using this
+ -- idiom:
+ -- SFix := UFix + (-UFix)
+ -- or copy one of the UFix operands into a SFix that's
+ -- one bit wider, before performing the operation.
+ --
+ -- Subtractions returning a UFix result take unsigned
+ -- operands and do not exhibit bit growth.
+ -- Subtractions returning a SFix result take signed or
+ -- unsigned operands and exhibit one-bit growth like addition.
+
+ -- A.4.1. UFix := UFix - UFix
+ function "-" (L: UFix; R: UFix) return UFix;
+
+ -- A.4.2. UFix := UFix - unsigned
+ function "-" (L: UFix; R: unsigned) return UFix;
+
+ -- A.4.3. UFix := unsigned - UFix
+ function "-" (L: unsigned; R: UFix) return UFix;
+
+ -- A.4.4. UFix := UFix - natural
+ function "-" (L: UFix; R: natural) return UFix;
+
+ -- A.4.5. UFix := natural - UFix
+ function "-" (L: natural; R: UFix) return UFix;
+
+ -- A.4.6. SFix := SFix - SFix
+ function "-" (L: SFix; R: SFix) return SFix;
+
+ -- A.4.7. SFix := SFix - UFix
+ function "-" (L: SFix; R: UFix) return SFix;
+
+ -- A.4.8. SFix := UFix - SFix
+ function "-" (L: UFix; R: SFix) return SFix;
+
+ -- A.4.9. SFix := SFix - signed
+ function "-" (L: SFix; R: signed) return SFix;
+
+ -- A.4.10. SFix := signed - SFix
+ function "-" (L: signed; R: SFix) return SFix;
+
+ -- A.4.11. SFix := SFix - integer
+ function "-" (L: SFix; R: integer) return SFix;
+
+ -- A.4.12. SFix := integer - SFix
+ function "-" (L: integer; R: SFix) return SFix;
+
+
+ -------------------------------------------
+ -- A.5. Binary "*" multiplication operator
+ -------------------------------------------
+
+ -- A.5.1. UFix := UFix * UFix
+ function "*" (L: UFix; R: UFix) return UFix;
+
+ -- A.5.2. UFix := UFix * unsigned
+ function "*" (L: UFix; R: unsigned) return UFix;
+
+ -- A.5.3. UFix := unsigned * UFix
+ function "*" (L: unsigned; R: UFix) return UFix;
+
+ -- A.5.4. UFix := UFix * natural
+ function "*" (L: UFix; R: natural) return UFix;
+
+ -- A.5.5. UFix := natural * UFix
+ function "*" (L: natural; R: UFix) return UFix;
+
+ -- A.5.6. SFix := SFix * SFix
+ function "*" (L: SFix; R: SFix) return SFix;
+
+ -- A.5.7. SFix := SFix * UFix
+ function "*" (L: SFix; R: UFix) return SFix;
+
+ -- A.5.8. SFix := UFix * SFix
+ function "*" (L: UFix; R: SFix) return SFix;
+
+ -- A.5.9. SFix := SFix * signed
+ function "*" (L: SFix; R: signed) return SFix;
+
+ -- A.5.10. SFix := signed * SFix
+ function "*" (L: signed; R: SFix) return SFix;
+
+ -- A.5.11. SFix := SFix * integer
+ function "*" (L: SFix; R: integer) return SFix;
+
+ -- A.5.12. SFix := integer * SFix
+ function "*" (L: integer; R: SFix) return SFix;
+
+
+ ------------------------------------------------------------------
+ -- R. Relational operators - arithmetic comparisons involving
+ -- UFix, SFix and other numeric types.
+ -- The operators are overloaded for most of the sensible
+ -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
+ -- Note that in all cases comparisons are exact; if one
+ -- operand has more fraction bits than the other, the less
+ -- precise operand will have its LSBs zero-extended, and
+ -- these zero bits will take part in comparison with whatever
+ -- LSBs exist in the more precise operand.
+ ------------------------------------------------------------------
+
+ -------------------------------------
+ -- R.1. Binary "=" equality operator
+ -------------------------------------
+
+ -- R.1.1. UFix = UFix
+ function "=" (L: UFix; R: UFix) return boolean;
+
+ -- R.1.2. UFix = unsigned
+ function "=" (L: UFix; R: unsigned) return boolean;
+
+ -- R.1.3. unsigned = UFix
+ function "=" (L: unsigned; R: UFix) return boolean;
+
+ -- R.1.4. UFix = integer
+ function "=" (L: UFix; R: integer) return boolean;
+
+ -- R.1.5. integer = UFix
+ function "=" (L: integer; R: UFix) return boolean;
+
+ -- R.1.6. SFix = SFix
+ function "=" (L: SFix; R: SFix) return boolean;
+
+ -- R.1.7. SFix = UFix
+ function "=" (L: SFix; R: UFix) return boolean;
+
+ -- R.1.8. UFix = SFix
+ function "=" (L: UFix; R: SFix) return boolean;
+
+ -- R.1.9. SFix = signed
+ function "=" (L: SFix; R: signed) return boolean;
+
+ -- R.1.10. signed = SFix
+ function "=" (L: signed; R: SFix) return boolean;
+
+ -- R.1.11. SFix = integer
+ function "=" (L: SFix; R: integer) return boolean;
+
+ -- R.1.12. integer = SFix
+ function "=" (L: integer; R: SFix) return boolean;
+
+
+ --------------------------------------
+ -- R.2. Binary "<" less-than operator
+ --------------------------------------
+
+ -- R.2.1. UFix < UFix
+ function "<" (L: UFix; R: UFix) return boolean;
+
+ -- R.2.2. UFix < unsigned
+ function "<" (L: UFix; R: unsigned) return boolean;
+
+ -- R.2.3. unsigned < UFix
+ function "<" (L: unsigned; R: UFix) return boolean;
+
+ -- R.2.4. UFix < integer
+ function "<" (L: UFix; R: integer) return boolean;
+
+ -- R.2.5. integer < UFix
+ function "<" (L: integer; R: UFix) return boolean;
+
+ -- R.2.6. SFix < SFix
+ function "<" (L: SFix; R: SFix) return boolean;
+
+ -- R.2.7. SFix < UFix
+ function "<" (L: SFix; R: UFix) return boolean;
+
+ -- R.2.8. UFix < SFix
+ function "<" (L: UFix; R: SFix) return boolean;
+
+ -- R.2.9. SFix < signed
+ function "<" (L: SFix; R: signed) return boolean;
+
+ -- R.2.10. signed < SFix
+ function "<" (L: signed; R: SFix) return boolean;
+
+ -- R.2.11. SFix < integer
+ function "<" (L: SFix; R: integer) return boolean;
+
+ -- R.2.12. integer < SFix
+ function "<" (L: integer; R: SFix) return boolean;
+
+
+ ----------------------------------------
+ -- R.3. Binary "/=" inequality operator
+ ----------------------------------------
+
+ -- R.3.1. UFix /= UFix
+ function "/=" (L: UFix; R: UFix) return boolean;
+
+ -- R.3.2. UFix /= unsigned
+ function "/=" (L: UFix; R: unsigned) return boolean;
+
+ -- R.3.3. unsigned /= UFix
+ function "/=" (L: unsigned; R: UFix) return boolean;
+
+ -- R.3.4. UFix /= integer
+ function "/=" (L: UFix; R: integer) return boolean;
+
+ -- R.3.5. integer /= UFix
+ function "/=" (L: integer; R: UFix) return boolean;
+
+ -- R.3.6. SFix /= SFix
+ function "/=" (L: SFix; R: SFix) return boolean;
+
+ -- R.3.7. SFix /= UFix
+ function "/=" (L: SFix; R: UFix) return boolean;
+
+ -- R.3.8. UFix /= SFix
+ function "/=" (L: UFix; R: SFix) return boolean;
+
+ -- R.3.9. SFix /= signed
+ function "/=" (L: SFix; R: signed) return boolean;
+
+ -- R.3.10. signed /= SFix
+ function "/=" (L: signed; R: SFix) return boolean;
+
+ -- R.3.11. SFix /= integer
+ function "/=" (L: SFix; R: integer) return boolean;
+
+ -- R.3.12. integer /= SFix
+ function "/=" (L: integer; R: SFix) return boolean;
+
+
+ -----------------------------------------
+ -- R.4. Binary ">" greater-than operator
+ -----------------------------------------
+
+ -- R.4.1. UFix > UFix
+ function ">" (L: UFix; R: UFix) return boolean;
+
+ -- R.4.2. UFix > unsigned
+ function ">" (L: UFix; R: unsigned) return boolean;
+
+ -- R.4.3. unsigned > UFix
+ function ">" (L: unsigned; R: UFix) return boolean;
+
+ -- R.4.4. UFix > integer
+ function ">" (L: UFix; R: integer) return boolean;
+
+ -- R.4.5. integer > UFix
+ function ">" (L: integer; R: UFix) return boolean;
+
+ -- R.4.6. SFix > SFix
+ function ">" (L: SFix; R: SFix) return boolean;
+
+ -- R.4.7. SFix > UFix
+ function ">" (L: SFix; R: UFix) return boolean;
+
+ -- R.4.8. UFix > SFix
+ function ">" (L: UFix; R: SFix) return boolean;
+
+ -- R.4.9. SFix > signed
+ function ">" (L: SFix; R: signed) return boolean;
+
+ -- R.4.10. signed > SFix
+ function ">" (L: signed; R: SFix) return boolean;
+
+ -- R.4.11. SFix > integer
+ function ">" (L: SFix; R: integer) return boolean;
+
+ -- R.4.12. integer > SFix
+ function ">" (L: integer; R: SFix) return boolean;
+
+
+ ----------------------------------------------
+ -- R.5. Binary ">=" greater-or-equal operator
+ ----------------------------------------------
+
+ -- R.5.1. UFix >= UFix
+ function ">=" (L: UFix; R: UFix) return boolean;
+
+ -- R.5.2. UFix >= unsigned
+ function ">=" (L: UFix; R: unsigned) return boolean;
+
+ -- R.5.3. unsigned >= UFix
+ function ">=" (L: unsigned; R: UFix) return boolean;
+
+ -- R.5.4. UFix >= integer
+ function ">=" (L: UFix; R: integer) return boolean;
+
+ -- R.5.5. integer >= UFix
+ function ">=" (L: integer; R: UFix) return boolean;
+
+ -- R.5.6. SFix >= SFix
+ function ">=" (L: SFix; R: SFix) return boolean;
+
+ -- R.5.7. SFix >= UFix
+ function ">=" (L: SFix; R: UFix) return boolean;
+
+ -- R.5.8. UFix >= SFix
+ function ">=" (L: UFix; R: SFix) return boolean;
+
+ -- R.5.9. SFix >= signed
+ function ">=" (L: SFix; R: signed) return boolean;
+
+ -- R.5.10. signed >= SFix
+ function ">=" (L: signed; R: SFix) return boolean;
+
+ -- R.5.11. SFix >= integer
+ function ">=" (L: SFix; R: integer) return boolean;
+
+ -- R.5.12. integer >= SFix
+ function ">=" (L: integer; R: SFix) return boolean;
+
+
+ -------------------------------------------
+ -- R.6. Binary "<=" less-or-equal operator
+ -------------------------------------------
+
+ -- R.6.1. UFix <= UFix
+ function "<=" (L: UFix; R: UFix) return boolean;
+
+ -- R.6.2. UFix <= unsigned
+ function "<=" (L: UFix; R: unsigned) return boolean;
+
+ -- R.6.3. unsigned <= UFix
+ function "<=" (L: unsigned; R: UFix) return boolean;
+
+ -- R.6.4. UFix <= integer
+ function "<=" (L: UFix; R: integer) return boolean;
+
+ -- R.6.5. integer <= UFix
+ function "<=" (L: integer; R: UFix) return boolean;
+
+ -- R.6.6. SFix <= SFix
+ function "<=" (L: SFix; R: SFix) return boolean;
+
+ -- R.6.7. SFix <= UFix
+ function "<=" (L: SFix; R: UFix) return boolean;
+
+ -- R.6.8. UFix <= SFix
+ function "<=" (L: UFix; R: SFix) return boolean;
+
+ -- R.6.9. SFix <= signed
+ function "<=" (L: SFix; R: signed) return boolean;
+
+ -- R.6.10. signed <= SFix
+ function "<=" (L: signed; R: SFix) return boolean;
+
+ -- R.6.11. SFix <= integer
+ function "<=" (L: SFix; R: integer) return boolean;
+
+ -- R.6.12. integer <= SFix
+ function "<=" (L: integer; R: SFix) return boolean;
+
+
+ ------------------------------------------------------------------
+ -- C. Concatenation operators between fixed-point operands, and
+ -- between fixed-point operands and other reasonable types.
+ -- Unlike the implicitly defined "&" operator, they preserve
+ -- place value and return an appropriately aligned subtype.
+ -- Preservation of place value means that some concatenation
+ -- operations are illegal. In particular, operations
+ -- [SFix & SFix] and [UFix & SFix] are illegal, and
+ -- the place values of operands in [SFix & UFix] and
+ -- [UFix & UFix] must match up - the rightmost subscript of
+ -- the left operand must be one higher than the leftmost
+ -- subscript of the right operand.
+ -- Single bits of type std_ulogic may be concatenated with
+ -- fixed-point types where there is no risk of losing
+ -- sign-extension information.
+ -- Because of the way VHDL defines implicit concatenation,
+ -- it is impossible to detect all these errors at compile time.
+ -- Instead they are detected by assertion statements at run time.
+ -- Tool vendors may choose to implement compile-time checks
+ -- so that the run-time checking overhead can be avoided.
+ ------------------------------------------------------------------
+
+ -- C.1.1. UFix := UFix & UFix
+ function "&" (L: UFix; R: UFix) return UFix;
+
+ -- No need to define "&"[UFix, SFix] explicitly, because
+ -- the types are incompatible and so there's no default
+
+ -- C.1.2. UFix := UFix & std_ulogic
+ function "&" (L: UFix; R: std_ulogic) return UFix;
+
+ -- C.1.3. UFix := std_ulogic & UFix
+ function "&" (L: std_ulogic; R: UFix) return UFix;
+
+
+ -- C.2.1. SFix := SFix & UFix
+ function "&" (L: SFix; R: UFix) return SFix;
+
+ -- C.2.2. SFix := SFix & SFix -- ILLEGAL
+ function "&" (L: SFix; R: SFix) return SFix;
+
+ -- C.2.3. SFix := SFix & std_ulogic
+ function "&" (L: SFix; R: std_ulogic) return SFix;
+
+ -- C.2.4. SFix := std_ulogic & SFix
+ function "&" (L: std_ulogic; R: SFix) return SFix;
+
+
+end; -- package fix_std;
diff --git a/lib/fix_std/fix_stdb.vhd b/lib/fix_std/fix_stdb.vhd
new file mode 100644
index 0000000..695cd11
--- /dev/null
+++ b/lib/fix_std/fix_stdb.vhd
@@ -0,0 +1,1910 @@
+---------------------------------------------------------------------
+--
+-- Package body fix_std
+-- Fixed point arithmetic based on numeric_std
+-- Compile using VHDL-93 (required to support 'ASCENDING
+-- array attribute).
+--
+---------------------------------------------------------------------
+--
+-- This document describes a VHDL package of definitions and subprograms
+-- intended to support the use of fixed-point arithmetic in test benches
+-- and synthesisable designs. This document and the package it describes
+-- are made freely available to the HDL design community without warranty
+-- of any kind. You are welcome to make use of this information for your
+-- own private study and in your own designs. If you make use of the
+-- package, you accept sole responsibility for its fitness for purpose
+-- and its suitability in your application. You are free to modify the
+-- package in any way, and to record your contribution to it, but this
+-- notice must appear in a prominent place in any modified or derived
+-- version of the package or its supporting documentation.
+--
+-- The author wishes to thank his employer Doulos Ltd for making
+-- available the facilities used to develop, test and distribute this
+-- package. However, Doulos Ltd accepts no responsibility for the
+-- package's contents and cannot support it in any way.
+--
+---------------------------------------------------------------------
+-- Revision information:
+--
+-- Version 0.1 06-May-2003
+-- Alpha version, for review
+-- No division operators are provided, pending detailed
+-- consultation on their functionality.
+-- Some subprogram implementations are unnecessarily inefficient.
+-- Version 0.2 11-Jun-2003
+-- Fixes aiming to make the package portable across all synthesis tools:
+-- * Removed deferred constants, made them package constants
+-- * Removed all variable initialisations in procedures, made them
+-- procedural initialisations in the code
+-- * Fixed definition of extract functions to return just one bit
+-- if their results would otherwise be null
+---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package body fix_std is
+
+ --------------------------------------------------------------------
+ -- DEFERRED CONSTANTS
+ --------------------------------------------------------------------
+ -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC
+ -- IMPLEMENTATIONS OR APPLICATIONS.
+ --------------------------------------------------------------------
+
+ -- Fixed-point offset, the bit number (subscript) used for
+ -- the bit in a UFix or SFix vector having binary weight 2^0
+ -- (the units bit).
+ --
+ -- constant FixP : Fix_Subscr := 100;
+
+ -- Default values for overflow and rounding modes:
+ --
+ -- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS;
+ -- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS;
+
+ --------------------------------------------------------------------
+ -- END OF DEFERRED CONSTANTS
+ --------------------------------------------------------------------
+
+ --------------------------------------------------------------------
+ -- IMPLEMENTATION CONSTANTS
+ --------------------------------------------------------------------
+ -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC
+ -- IMPLEMENTATIONS OR APPLICATIONS.
+ --------------------------------------------------------------------
+
+ -- Severity levels for various errors
+
+ -- Concatenation errors - bad sign extension, discontiguous range etc
+ -- These are only warnings - they just give the wrong answer.
+ --
+ constant concat_severity : severity_level := WARNING;
+
+ -- Subtype direction errors - the present implementation can't
+ -- handle fixed-point objects with ascending ranges. These messages
+ -- are intended to give early warning of problems that would
+ -- definitely cause other fatal errors at elaboration or run time.
+ --
+ constant direction_severity : severity_level := FAILURE;
+
+ -- Assertion error message constants
+
+ constant bad_direction_msg : string :=
+ " has ascending range";
+
+ constant concat_range_msg : string :=
+ "Concatenation bounds should have contiguous ranges";
+
+ constant concat_sxt_msg : string :=
+ "Concatenation corrupts sign of result";
+
+ constant concat_signLS_msg : string :=
+ "RHS of concatenation should be unsigned";
+
+ constant compare_meta_msg : string :=
+ "Metavalue detected in FIX_STD comparison, returning FALSE";
+
+ --------------------------------------------------------------------
+ -- END OF IMPLEMENTATION CONSTANTS
+ --------------------------------------------------------------------
+
+ --------------------------------------------------------------------
+ -- DO NOT MODIFY ANY CODE BELOW THIS POINT.
+ --------------------------------------------------------------------
+
+ -- Assumed bit width of INTEGER type in VHDL
+ --
+ constant INT_WIDTH : positive := 32;
+
+ -- Single-bit zero values
+ subtype Izero_UFixT is UFix(FixP downto FixP);
+ subtype Izero_SFixT is SFix(FixP downto FixP);
+ subtype Fzero_UFixT is UFix(FixP-1 downto FixP-1);
+ constant Izero_UFix: Izero_UFixT := "0";
+ constant Izero_SFix: Izero_SFixT := "0";
+ constant Fzero_UFix: Fzero_UFixT := "0";
+
+ --------------------------------------------------------------------
+ -- LOCAL PRIVATE SUBPROGRAMS
+ --------------------------------------------------------------------
+
+ -- Min, Max: Find minimum and maximum of two integers.
+ -- Useful for determining appropriate range for operation results.
+ --
+ function Max(L, R: Fix_Subscr) return Fix_Subscr is
+ begin
+ if L>R then
+ return L;
+ else
+ return R;
+ end if;
+ end;
+ --
+ function Min(L, R: Fix_Subscr) return Fix_Subscr is
+ begin
+ if L FixP then
+ return Span(U);
+ else
+ return U(U'LEFT downto FixP);
+ end if;
+ end;
+
+ -- E.2. Return the fractional part of a UFix value
+ function Frac(U: UFix) return UFix is
+ begin
+ if U'LEFT < FixP-1 then
+ return Span(U);
+ elsif U'RIGHT >= FixP then
+ return Fzero_UFix;
+ else
+ return U(FixP-1 downto U'RIGHT);
+ end if;
+ end;
+
+ -- E.3. Return the integral part of a SFix value
+ function Int(S: SFix) return SFix is
+ begin
+ if S'LENGTH = 0 then
+ return Izero_SFix;
+ elsif S'LEFT <= FixP then
+ return SFix'(FixP => S(S'LEFT));
+ elsif S'RIGHT > FixP then
+ return Span(S);
+ else
+ return S(S'LEFT downto FixP);
+ end if;
+ end;
+
+ -- E.4. Return the fractional part of a SFix value
+ function Frac(S: SFix) return UFix is
+ variable P: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP));
+ begin
+ if S'LEFT < FixP then
+ for I in FixP-1 downto S'LEFT+1 loop
+ P(I) := S(S'LEFT);
+ end loop;
+ P(S'RANGE) := S;
+ return UFix(S(FixP-1 downto S'RIGHT));
+ elsif S'RIGHT >= FixP then
+ return Fzero_UFix;
+ else
+ return UFix(S(FixP-1 downto S'RIGHT));
+ end if;
+ end;
+
+ -- E.5. Widen a SFix value if necessary so that
+ -- its range adjoins or spans the binary point
+ function Span(S: SFix) return SFix is
+ variable F: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP));
+ begin
+ F(S'RANGE) := S;
+ for I in F'LEFT downto S'LEFT+1 loop
+ F(I) := S(S'LEFT);
+ end loop;
+ for I in S'RIGHT-1 downto F'RIGHT loop
+ F(I) := '0';
+ end loop;
+ return F;
+ end;
+
+ -- E.6. Widen a UFix value if necessary so that
+ -- its range adjoins or spans the binary point
+ function Span(U: UFix) return UFix is
+ variable F: UFix(Max(U'LEFT, FixP-1) downto Min(U'RIGHT, FixP));
+ begin
+ F(U'RANGE) := U;
+ for I in F'LEFT downto U'LEFT+1 loop
+ F(I) := '0';
+ end loop;
+ for I in U'RIGHT-1 downto F'RIGHT loop
+ F(I) := '0';
+ end loop;
+ return F;
+ end;
+
+ ---------------------------
+ -- T. Conversion functions
+ ---------------------------
+
+ -- T.1 to T.8: Unsigned conversions
+
+ -- T.1. Resizing an existing UFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_UFix(
+ N : UFix;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return UFix is
+ variable F: UFix(MSB_index downto LSB_index);
+ begin
+ Copy_V(F, N, overflow, rounding);
+ return F;
+ end;
+
+ -- T.2. Resizing an existing SFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_UFix(
+ N : SFix;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return UFix is
+ variable F: UFix(MSB_index downto LSB_index);
+ begin
+ Copy_V(F, N, overflow, rounding);
+ return F;
+ end;
+
+ -- T.3. Conversion from integer to UFix. Provide number of
+ -- integer bits and number of fraction bits. Note that
+ -- negative input is tolerated!
+ --
+ function to_UFix(
+ N : integer;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return UFix is
+ variable F: UFix(MSB_index downto LSB_index);
+ begin
+ Copy_V(F, N, overflow, rounding);
+ return F;
+ end;
+
+ -- T.4. Conversion from unsigned to UFix. Provide subscripts of
+ -- MS and (optionally) LS bit of the resulting UFix.
+ --
+ function to_UFix(
+ N : unsigned;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return UFix is
+ variable F: UFix(MSB_index downto LSB_index);
+ begin
+ Copy_V(F, N, overflow, rounding);
+ return F;
+ end;
+
+ -- T.5. Conversion from unsigned to UFix. Automatically set the
+ -- range of the resulting UFix to match the unsigned value,
+ -- as an integral UFix value with no fraction bits.
+ --
+ function to_UFix( N : unsigned ) return UFix is
+ variable F: UFix(FixP+N'LENGTH-1 downto FixP);
+ begin
+ F := UFix(N);
+ return F;
+ end;
+
+ -- T.6. Conversion from UFix to unsigned. All integer bits are
+ -- preserved (including adding LS scale bits if necessary).
+ --
+ function to_unsigned(
+ N : UFix;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return unsigned is
+ variable F_UFix: UFix(N'LEFT downto FixP);
+ variable F: unsigned(F_UFix'LENGTH-1 downto 0);
+ begin
+ Copy_V(F_UFix, N, rounding=>rounding);
+ F := unsigned(F_UFix);
+ return F;
+ end;
+
+ -- T.7. Conversion from UFix to unsigned. Caller specifies
+ -- required number of bits in unsigned result.
+ --
+ function to_unsigned(
+ N : UFix;
+ bits : positive;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return unsigned is
+ variable F_UFix: UFix(FixP+bits-1 downto FixP);
+ variable F: unsigned(F_UFix'LENGTH-1 downto 0);
+ begin
+ Copy_V(F_UFix, N, overflow, rounding);
+ F := unsigned(F_UFix);
+ return F;
+ end;
+
+ -- T.8. Conversion from UFix to integer. Up to 31 integer bits are
+ -- preserved (including adding LS scale bits if necessary).
+ --
+ function to_integer(
+ N : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return integer is
+ variable F_UFix: UFix(Min(FixP+INT_WIDTH-2, N'LEFT) downto FixP);
+ begin
+ Copy_V(F_UFix, N, overflow, rounding);
+ return to_integer(unsigned(F_UFix));
+ end;
+
+ -- T.9 to T.16: Signed conversions
+
+ -- T.9. Resizing an existing UFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_SFix(
+ N : UFix;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return SFix is
+ variable F: SFix(MSB_index downto LSB_index);
+ begin
+ Copy_V(F, N, overflow, rounding);
+ return F;
+ end;
+
+ -- T.10. Resizing an existing SFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_SFix(
+ N : SFix;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return SFix is
+ variable F: SFix(MSB_index downto LSB_index);
+ begin
+ Copy_V(F, N, overflow, rounding);
+ return F;
+ end;
+
+ -- T.11. Conversion from integer to SFix. Provide number of
+ -- integer bits and number of fraction bits.
+ --
+ function to_SFix(
+ N : integer;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return SFix is
+ variable F: SFix(MSB_index downto LSB_index);
+ begin
+ Copy_V(F, N, overflow, rounding);
+ return F;
+ end;
+
+ -- T.12. Conversion from signed to SFix. Provide subscripts of
+ -- MS and (optionally) LS bit of the resulting SFix.
+ --
+ function to_SFix(
+ N : signed;
+ MSB_index : Fix_Subscr;
+ LSB_index : Fix_Subscr := FixP;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return SFix is
+ variable F: SFix(MSB_index downto LSB_index);
+ begin
+ Copy_V(F, N, overflow, rounding);
+ return F;
+ end;
+
+ -- T.13. Conversion from signed to SFix. Automatically set the
+ -- range of the resulting SFix to match the signed value,
+ -- as an integral SFix value with no fraction bits.
+ --
+ function to_SFix( N : signed ) return SFix is
+ variable F: SFix(FixP+N'LENGTH-1 downto FixP);
+ begin
+ F := SFix(N);
+ return F;
+ end;
+
+ -- T.14. Conversion from SFix to signed. All integer bits are
+ -- preserved (including adding LS scale bits if necessary).
+ --
+ function to_signed(
+ N : SFix;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return signed is
+ variable F_SFix: SFix(N'LEFT downto FixP);
+ variable F: signed(F_SFix'LENGTH-1 downto 0);
+ begin
+ Copy_V(F_SFix, N, rounding=>rounding);
+ F := signed(F_SFix);
+ return F;
+ end;
+
+ -- T.15. Conversion from SFix to signed. Caller specifies
+ -- required number of bits in signed result.
+ --
+ function to_signed(
+ N : SFix;
+ bits : positive;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return signed is
+ variable F_SFix: UFix(FixP+bits-1 downto FixP);
+ variable F: signed(F_SFix'LENGTH-1 downto 0);
+ begin
+ Copy_V(F_SFix, N, overflow, rounding);
+ F := signed(F_SFix);
+ return F;
+ end;
+
+ -- T.16. Conversion from SFix to integer. Up to 32 integer bits are
+ -- preserved (including adding LS scale bits if necessary).
+ --
+ function to_integer(
+ N : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) return integer is
+ variable F_SFix: SFix(Min(FixP+INT_WIDTH-1, N'LEFT) downto FixP);
+ begin
+ Copy_V(F_SFix, N, overflow, rounding);
+ return to_integer(signed(F_SFix));
+ end;
+
+ -- T.17. Conversion from UFix to SFix. This simply adds
+ -- an extra more significant bit, set to zero.
+ --
+ function to_SFix(U: UFix) return SFix is
+ variable F: SFix(U'LEFT+1 downto U'RIGHT);
+ begin
+ F := SFix('0' & U);
+ return F;
+ end;
+
+
+ ----------------------------------
+ -- V. Copy-to-variable procedures
+ ----------------------------------
+
+ -- Range-aware copying of an expression into a variable. The
+ -- ranges of destination variable and source expression are
+ -- used to determine correct rounding, overflow and scaling
+ -- behaviour.
+
+ -- V.1 to V.5: Copy an expression into a UFix variable
+
+ -- V.1. Copy UFix to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ subtype target_T is UFix(target'RANGE);
+ variable W: UFix(Max(target'LEFT, source'LEFT+1) downto
+ Min(target'RIGHT, source'RIGHT));
+ constant HighZero: UFix(W'LEFT downto target'LEFT+1) := (others => '0');
+ begin
+ assert not target'ASCENDING
+ report "target" & bad_direction_msg
+ severity direction_severity;
+ assert not source'ASCENDING
+ report "source" & bad_direction_msg
+ severity direction_severity;
+ W := (others => '0');
+ W(source'RANGE) := source;
+ if target'RIGHT > source'RIGHT then
+ case rounding is
+ when clip_LS | towards_zero =>
+ null;
+ when to_nearest =>
+ W(W'LEFT downto target'RIGHT-1) := UFix(
+ unsigned(W(W'LEFT downto target'RIGHT-1)) + 1
+ );
+ end case;
+ end if;
+ target := W(target'RANGE);
+ if HighZero'LENGTH > 0 then
+ if unsigned(W(HighZero'RANGE)) /= unsigned(HighZero) then
+ case overflow is
+ when clip_MS =>
+ null;
+ when saturate =>
+ target := target_T'(others => '1');
+ end case;
+ end if;
+ end if;
+ end;
+
+ -- V.2. Copy SFix to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable W: SFix(Max(Source'LEFT, target'LEFT) downto target'RIGHT);
+ constant target_zero: UFix(target'RANGE) := (others => '0');
+ begin
+ assert not target'ASCENDING
+ report "target" & bad_direction_msg
+ severity direction_severity;
+ assert not source'ASCENDING
+ report "source" & bad_direction_msg
+ severity direction_severity;
+ W := (others => '0');
+ -- Rounding & sign-extend
+ Copy_V(W, source, clip_MS, rounding);
+ -- Saturation?
+ if W < 0 and overflow = saturate then
+ target := target_zero;
+ else
+ Copy_V(target, UFix(W), overflow, clip_LS);
+ end if;
+ end;
+
+ -- V.3. Copy UNSIGNED to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : unsigned;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ constant U: UFix(FixP+source'LENGTH-1 downto FixP) := UFix(source);
+ begin
+ Copy_V(target, U, overflow, rounding);
+ end;
+
+ -- V.4. Copy SIGNED to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : signed;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source);
+ begin
+ Copy_V(target, S, overflow, rounding);
+ end;
+
+ -- V.5. Copy integer to UFix
+ --
+ procedure Copy_V(
+ target : out UFix;
+ source : integer;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ constant N: signed(FixP+INT_WIDTH-1 downto FixP)
+ := to_signed(source, INT_WIDTH);
+ begin
+ -- Cop-out, this is very inefficient, but will do for now.
+ Copy_V(target, N, overflow, rounding);
+ end;
+
+ -- V.6 to V.10: Copy an expression into a SFix variable
+
+ -- V.6. Copy UFix to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ constant S: SFix(FixP+source'LENGTH downto FixP) := to_SFix(source);
+ begin
+ Copy_V(target, S, overflow, rounding);
+ end;
+
+ -- V.7. Copy SFix to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ subtype target_T is SFix(target'RANGE);
+ variable W: SFix(Max(target'LEFT, source'LEFT+1) downto
+ Min(target'RIGHT, source'RIGHT));
+ variable HighSX: SFix(W'LEFT downto target'LEFT+1);
+ begin
+ for i in HighSX'RANGE loop
+ HighSX(i) := source(source'LEFT);
+ end loop;
+ assert not target'ASCENDING
+ report "target" & bad_direction_msg
+ severity direction_severity;
+ assert not source'ASCENDING
+ report "source" & bad_direction_msg
+ severity direction_severity;
+ -- Make W a copy of source, duly extended at both ends
+ W := (others => '0');
+ W(source'RANGE) := source;
+ W(HighSX'RANGE) := HighSX;
+ -- Do any rounding required
+ if target'RIGHT > source'RIGHT then
+ case rounding is
+ when clip_LS =>
+ null;
+ when towards_zero =>
+ if
+ (to_UX01(W(W'LEFT)) = '1') -- it's negative?
+ and
+ (unsigned(W(target'RIGHT-1 downto W'RIGHT)) /= 0) -- round up?
+ then
+ W(W'LEFT downto target'RIGHT) := SFix(
+ signed(W(W'LEFT downto target'RIGHT)) + 1
+ );
+ end if;
+ when to_nearest =>
+ W(W'LEFT downto target'RIGHT-1) := SFix(
+ signed(W(W'LEFT downto target'RIGHT-1)) + 1
+ );
+ end case;
+ end if;
+ -- Do any overflow required
+ target := W(target'RANGE);
+ if HighSX'LENGTH > 0 then
+ if signed(W(HighSX'RANGE)) /= signed(HighSX) then
+ case overflow is
+ when clip_MS =>
+ null;
+ when saturate =>
+ target := Target_T'(others => not W(W'LEFT));
+ target(target'LEFT) := W(W'LEFT);
+ end case;
+ end if;
+ end if;
+ end;
+
+ -- V.8. Copy UNSIGNED to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : unsigned;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ constant S: SFix(FixP+source'LENGTH downto FixP) := SFix('0' & source);
+ begin
+ Copy_V(target, S, overflow, rounding);
+ end;
+
+ -- V.9. Copy SIGNED to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : signed;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source);
+ begin
+ Copy_V(target, S, overflow, rounding);
+ end;
+
+ -- V.10. Copy integer to SFix
+ --
+ procedure Copy_V(
+ target : out SFix;
+ source : integer;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ constant N: signed(FixP+INT_WIDTH-1 downto FixP)
+ := to_signed(source, INT_WIDTH);
+ begin
+ -- Cop-out, this is very inefficient, but will do for now.
+ Copy_V(target, N, overflow, rounding);
+ end;
+
+
+ --------------------------------
+ -- S. Copy-to-signal procedures
+ --------------------------------
+ --
+ -- Range-aware copying of an expression into a signal. The
+ -- ranges of destination signal and source expression are
+ -- used to determine correct rounding, overflow and scaling
+ -- behaviour.
+
+ -- S.1 to S.5: Copy an expression into a UFix signal
+ --
+
+ -- S.1. Copy UFix to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: UFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.1. Copy SFix to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: UFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.3. Copy UNSIGNED to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : unsigned;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: UFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.4. Copy SIGNED to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : signed;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: UFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.5. Copy integer to UFix
+ --
+ procedure Copy_S(
+ signal target : out UFix;
+ source : integer;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: UFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.6 to S.10: Copy an expression into a SFix signal
+ --
+
+ -- S.6. Copy UFix to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : UFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: SFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.7. Copy SFix to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : SFix;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: SFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.8. Copy UNSIGNED to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : unsigned;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: SFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.9. Copy SIGNED to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : signed;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: SFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+ -- S.10. Copy integer to SFix
+ --
+ procedure Copy_S(
+ signal target : out SFix;
+ source : integer;
+ overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
+ rounding : Fix_Rounding_Mode := Fix_Default_Rounding
+ ) is
+ variable V: SFix(target'RANGE);
+ begin
+ Copy_V(V, source, overflow, rounding);
+ target <= V;
+ end;
+
+
+ ------------------------------------------------------------------
+ -- A. Arithmetic operations involving UFix, SFix and other
+ -- numeric types.
+ -- The operators are overloaded for most of the sensible
+ -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
+ --
+ -- IMPORTANT NOTE:
+ -- Arithmetic operators return a result that is wide enough
+ -- and precise enough so that no information is lost. THIS IS
+ -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std.
+ -- In the detailed description that follow, "scaling" means
+ -- the numerical value (weight) of the least significant bit
+ -- in a fixed-point value.
+ --
+ -- ADDITION returns a result whose least significant bit
+ -- is the same as the least significant bit in either operand,
+ -- and whose most significant bit is one position higher than
+ -- the most significant bit in either operand. Addition of
+ -- two operands having the same bounds therefore results in
+ -- a growth of one bit at the most significant end. Addition
+ -- of an integer to a UFix or SFix is accomplished by first
+ -- converting the integer to the same subtype as the other
+ -- operand, thereby giving rise to one-bit growth; default
+ -- truncation and rounding modes are used for the conversion.
+ --
+ -- SUBTRACTION where one or both operands are signed behaves
+ -- in the same way as addition. Subtraction where both operands
+ -- are unsigned returns a result whose most significant bit
+ -- position is the same as the most significant bit in either
+ -- operand, and whose least significant bit is the same as the
+ -- least significant bit in either operand.
+ --
+ -- MULTIPLICATION returns a result whose width is the sum of
+ -- the widths of its two operands, and whose scaling is the
+ -- product of its two operands' scalings.
+ --
+ -- UNARY NEGATION always gives a result having one more
+ -- significant bit than the operand.
+ --
+ -- ABSOLUTE VALUE always gives a result having exactly the
+ -- same subtype as its operand.
+ --
+ -- In binary operations where one operand is a fixed-point type
+ -- and the other is an integer numeric type, the integer operand
+ -- is first converted to a fixed-point type of the same subtype
+ -- as the other operand using Copy_V with default rounding and
+ -- overflow modes. The operation is then performed between two
+ -- fixed-point operands in the normal way.
+ --
+ ------------------------------------------------------------------
+
+
+ ------------------------------------
+ -- A.1. Unary "-" negation operator
+ ------------------------------------
+
+ -- A.1.1. SFix := - UFix
+ function "-" (R: UFix) return SFix is
+ variable F: SFix(R'LEFT+1 downto R'RIGHT);
+ begin
+ F := SFix(-(signed('0' & R)));
+ return F;
+ end;
+
+ -- A.1.2. SFix := - SFix
+ function "-" (R: SFix) return SFix is
+ variable F: SFix(R'LEFT+1 downto R'RIGHT);
+ begin
+ F := SFix(-(signed(R(R'LEFT) & R)));
+ return F;
+ end;
+
+
+ --------------------------------------------
+ -- A.2. Unary "abs" absolute-value operator
+ --------------------------------------------
+
+ -- A.2.1. SFix := abs SFix
+ function "abs" (R: SFix) return SFix is
+ variable F: SFix(R'RANGE);
+ begin
+ F := R;
+ if to_X01(R(R'LEFT)) = '1' then
+ F := SFix(-(signed(R)));
+ end if;
+ return F;
+ end;
+
+
+ -------------------------------------
+ -- A.3. Binary "+" addition operator
+ -------------------------------------
+
+ -- A.3.1. UFix := UFix + UFix
+ function "+" (L: UFix; R: UFix) return UFix is
+ variable F: UFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right));
+ variable LU, RU: unsigned(F'RANGE);
+ begin
+ LU := (others => '0');
+ RU := (others => '0');
+ LU(L'RANGE) := unsigned(L);
+ RU(R'RANGE) := unsigned(R);
+ F := UFix(LU + RU);
+ return F;
+ end;
+
+ -- A.3.2. UFix := UFix + unsigned
+ function "+" (L: UFix; R: unsigned) return UFix is
+ begin
+ return L + to_UFix(R);
+ end;
+
+ -- A.3.3. UFix := unsigned + UFix
+ function "+" (L: unsigned; R: UFix) return UFix is
+ begin
+ return R+L;
+ end;
+
+ -- A.3.4. UFix := UFix + natural
+ function "+" (L: UFix; R: natural) return UFix is
+ variable R_fp: UFix(L'RANGE);
+ begin
+ Copy_V(R_fp, R);
+ return L + R_fp;
+ end;
+
+ -- A.3.5. UFix := natural + UFix
+ function "+" (L: natural; R: UFix) return UFix is
+ begin
+ return R+L;
+ end;
+
+ -- A.3.6. SFix := SFix + SFix
+ function "+" (L: SFix; R: SFix) return SFix is
+ variable F: SFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right));
+ variable LS, RS: signed(F'RANGE);
+ begin
+ LS := (others => '0');
+ RS := (others => '0');
+ LS(L'RANGE) := signed(L);
+ RS(R'RANGE) := signed(R);
+ for i in LS'LEFT downto L'LEFT+1 loop LS(i) := L(L'LEFT); end loop;
+ for i in RS'LEFT downto R'LEFT+1 loop RS(i) := R(R'LEFT); end loop;
+ F := SFix(LS + RS);
+ return F;
+ end;
+
+ -- A.3.7. SFix := SFix + UFix
+ function "+" (L: SFix; R: UFix) return SFix is
+ begin
+ return L + SFix('0' & R);
+ end;
+
+ -- A.3.8. SFix := UFix + SFix
+ function "+" (L: UFix; R: SFix) return SFix is
+ begin
+ return SFix('0' & L) + R;
+ end;
+
+ -- A.3.9. SFix := SFix + signed
+ function "+" (L: SFix; R: signed) return SFix is
+ begin
+ return L + to_SFix(R);
+ end;
+
+ -- A.3.10. SFix := signed + SFix
+ function "+" (L: signed; R: SFix) return SFix is
+ begin
+ return to_SFix(L) + R;
+ end;
+
+ -- A.3.11. SFix := SFix + integer
+ function "+" (L: SFix; R: integer) return SFix is
+ variable R_fp: SFix(L'RANGE);
+ begin
+ Copy_V(R_fp, R);
+ return L + R_fp;
+ end;
+
+ -- A.3.12. SFix := integer + SFix
+ function "+" (L: integer; R: SFix) return SFix is
+ begin
+ return R + L;
+ end;
+
+
+ ----------------------------------------
+ -- A.4. Binary "-" subtraction operator
+ ----------------------------------------
+ --
+ -- NOTE: There is a special problem with subtraction
+ -- operators that return a UFix result if that result
+ -- goes negative. Our arbitrary decision is that we
+ -- truncate most-significant bits in this case. If you
+ -- wish to avoid the risk of this arbitrarily-defined
+ -- truncation behaviour, change one or more of your
+ -- operands to SFix and get a SFix result using this
+ -- idiom:
+ -- SFix := UFix + (-UFix)
+ -- or copy one of the UFix operands into a SFix that's
+ -- one bit wider, before performing the operation.
+ --
+ -- Subtractions returning a UFix result take unsigned
+ -- operands and do not exhibit bit growth.
+ -- Subtractions returning a SFix result take signed or
+ -- unsigned operands and exhibit one-bit growth like addition.
+
+ -- A.4.1. UFix := UFix - UFix
+ function "-" (L: UFix; R: UFix) return UFix is
+ variable F, LW, RW: UFix(Max(L'LEFT, R'LEFT) downto
+ Min(L'RIGHT, R'RIGHT));
+ begin
+ LW := (others => '0');
+ RW := (others => '0');
+ LW(L'RANGE) := L;
+ RW(R'RANGE) := R;
+ F := UFix(unsigned(LW) - unsigned(RW));
+ return F;
+ end;
+
+ -- A.4.2. UFix := UFix - unsigned
+ function "-" (L: UFix; R: unsigned) return UFix is
+ begin
+ return L - to_UFix(R);
+ end;
+
+ -- A.4.3. UFix := unsigned - UFix
+ function "-" (L: unsigned; R: UFix) return UFix is
+ begin
+ return to_UFix(L) - R;
+ end;
+
+ -- A.4.4. UFix := UFix - integer
+ function "-" (L: UFix; R: natural) return UFix is
+ variable R_fp: UFix(L'RANGE);
+ begin
+ Copy_V(R_fp, R);
+ return L - R_fp;
+ end;
+
+ -- A.4.5. UFix := natural - UFix
+ function "-" (L: natural; R: UFix) return UFix is
+ variable L_fp: UFix(R'RANGE);
+ begin
+ Copy_V(L_fp, L);
+ return L_fp - R;
+ end;
+
+ -- A.4.6. SFix := SFix - SFix
+ function "-" (L: SFix; R: SFix) return SFix is
+ begin
+ return L + (-R);
+ end;
+
+ -- A.4.7. SFix := SFix - UFix
+ function "-" (L: SFix; R: UFix) return SFix is
+ begin
+ return L + (-R);
+ end;
+
+ -- A.4.8. SFix := UFix - SFix
+ function "-" (L: UFix; R: SFix) return SFix is
+ begin
+ return To_SFix(L) - R;
+ end;
+
+ -- A.4.9. SFix := SFix - signed
+ function "-" (L: SFix; R: signed) return SFix is
+ begin
+ return L - to_SFix(R);
+ end;
+
+ -- A.4.10. SFix := signed - SFix
+ function "-" (L: signed; R: SFix) return SFix is
+ begin
+ return to_SFix(L) - R;
+ end;
+
+ -- A.4.11. SFix := SFix - integer
+ function "-" (L: SFix; R: integer) return SFix is
+ variable R_fp: SFix(L'RANGE);
+ begin
+ Copy_V(R_fp, R);
+ return L - R_fp;
+ end;
+
+ -- A.4.12. SFix := integer - SFix
+ function "-" (L: integer; R: SFix) return SFix is
+ variable L_fp: SFix(R'RANGE);
+ begin
+ Copy_V(L_fp, L);
+ return L_fp - R;
+ end;
+
+
+ -------------------------------------------
+ -- A.5. Binary "*" multiplication operator
+ -------------------------------------------
+
+ -- A.5.1. UFix := UFix * UFix
+ function "*" (L: UFix; R: UFix) return UFix is
+ variable F: UFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
+ begin
+ F := UFix(unsigned(L) * unsigned(R));
+ return F;
+ end;
+
+ -- A.5.2. UFix := UFix * unsigned
+ function "*" (L: UFix; R: unsigned) return UFix is
+ begin
+ return L * to_UFix(R);
+ end;
+
+ -- A.5.3. UFix := unsigned * UFix
+ function "*" (L: unsigned; R: UFix) return UFix is
+ begin
+ return to_UFix(L) * R;
+ end;
+
+ -- A.5.4. UFix := UFix * natural
+ function "*" (L: UFix; R: natural) return UFix is
+ variable R_fp: UFix(L'RANGE);
+ begin
+ Copy_V(R_fp, R);
+ return L * R_fp;
+ end;
+
+ -- A.5.5. UFix := natural * UFix
+ function "*" (L: natural; R: UFix) return UFix is
+ begin
+ return R * L;
+ end;
+
+ -- A.5.6. SFix := SFix * SFix
+ function "*" (L: SFix; R: SFix) return SFix is
+ variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
+ begin
+ F := SFix(signed(L) * signed(R));
+ return F;
+ end;
+
+ -- A.5.7. SFix := SFix * UFix
+ function "*" (L: SFix; R: UFix) return SFix is
+ constant RS: SFix := SFix('0' & R);
+ variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
+ variable FW: SFix(F'LEFT+1 downto F'RIGHT);
+ begin
+ FW := SFix(signed(L) * signed(RS));
+ Copy_V(F, FW); -- never overflows
+ return F;
+ end;
+
+ -- A.5.8. SFix := UFix * SFix
+ function "*" (L: UFix; R: SFix) return SFix is
+ begin
+ return R * L;
+ end;
+
+ -- A.5.9. SFix := SFix * signed
+ function "*" (L: SFix; R: signed) return SFix is
+ begin
+ return L * to_SFix(R);
+ end;
+
+ -- A.5.10. SFix := signed * SFix
+ function "*" (L: signed; R: SFix) return SFix is
+ begin
+ return to_SFix(L) * R;
+ end;
+
+ -- A.5.11. SFix := SFix * integer
+ function "*" (L: SFix; R: integer) return SFix is
+ variable R_fp: SFix(L'RANGE);
+ begin
+ Copy_V(R_fp, R);
+ return L * R_fp;
+ end;
+
+ -- A.5.12. SFix := integer * SFix
+ function "*" (L: integer; R: SFix) return SFix is
+ begin
+ return R * L;
+ end;
+
+
+ ------------------------------------------------------------------
+ -- R. Relational operators - arithmetic comparisons involving
+ -- UFix, SFix and other numeric types.
+ -- The operators are overloaded for most of the sensible
+ -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
+ -- Note that in all cases comparisons are exact; if one
+ -- operand has more fraction bits than the other, the less
+ -- precise operand will have its LSBs zero-extended, and
+ -- these zero bits will take part in comparison with whatever
+ -- LSBs exist in the more precise operand.
+ --
+ -- Our implementation is based on only two operators, "=" and "<".
+ -- All other operators are derived from these two, either by
+ -- logical inversion of the result or by swapping operands.
+ ------------------------------------------------------------------
+
+ -------------------------------------
+ -- R.1. Binary "=" equality operator
+ -------------------------------------
+
+ -- R.1.1. UFix = UFix
+ function "=" (L: UFix; R: UFix) return boolean is
+ variable LW, RW: UFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT));
+ begin
+ LW := (others => '0');
+ RW := (others => '0');
+ LW(L'RANGE) := L;
+ RW(R'RANGE) := R;
+ return unsigned(LW) = unsigned(RW);
+ end;
+
+ -- R.1.2. UFix = unsigned
+ function "=" (L: UFix; R: unsigned) return boolean is
+ begin
+ return L = to_UFix(R);
+ end;
+
+ -- R.1.3. unsigned = UFix
+ function "=" (L: unsigned; R: UFix) return boolean is
+ begin
+ return to_UFix(L) = R;
+ end;
+
+ -- R.1.4. UFix = integer
+ function "=" (L: UFix; R: integer) return boolean is
+ variable RS: SFix(FixP+INT_WIDTH-1 downto FixP);
+ begin
+ Copy_V(RS, R, clip_MS, clip_LS);
+ return To_SFix(L) = RS;
+ end;
+
+ -- R.1.5. integer = UFix
+ function "=" (L: integer; R: UFix) return boolean is
+ begin
+ return R = L;
+ end;
+
+ -- R.1.6. SFix = SFix
+ function "=" (L: SFix; R: SFix) return boolean is
+ variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT));
+ begin
+ -- clip modes are OK because we aren't losing any bits
+ Copy_V(LW, L, clip_MS, clip_LS);
+ Copy_V(RW, R, clip_MS, clip_LS);
+ return signed(LW) = signed(RW);
+ end;
+
+ -- R.1.7. SFix = UFix
+ function "=" (L: SFix; R: UFix) return boolean is
+ begin
+ return L = To_SFix(R);
+ end;
+
+ -- R.1.8. UFix = SFix
+ function "=" (L: UFix; R: SFix) return boolean is
+ begin
+ return R = L;
+ end;
+
+ -- R.1.9. SFix = signed
+ function "=" (L: SFix; R: signed) return boolean is
+ begin
+ return L = to_SFix(R);
+ end;
+
+ -- R.1.10. signed = SFix
+ function "=" (L: signed; R: SFix) return boolean is
+ begin
+ return to_SFix(L) = R;
+ end;
+
+ -- R.1.11. SFix = integer
+ function "=" (L: SFix; R: integer) return boolean is
+ variable RS: SFix(FixP+INT_WIDTH-1 downto FixP);
+ begin
+ Copy_V(RS, R, clip_MS, clip_LS);
+ return L = RS;
+ end;
+
+ -- R.1.12. integer = SFix
+ function "=" (L: integer; R: SFix) return boolean is
+ begin
+ return R = L;
+ end;
+
+
+ --------------------------------------
+ -- R.2. Binary "<" less-than operator
+ --------------------------------------
+
+ -- R.2.1. UFix < UFix
+ function "<" (L: UFix; R: UFix) return boolean is
+ variable LW, RW: unsigned(Max(L'LEFT, R'LEFT) downto
+ Min(L'RIGHT, R'RIGHT));
+ begin
+ LW := (others => '0');
+ RW := (others => '0');
+ LW(L'RANGE) := unsigned(L);
+ RW(R'RANGE) := unsigned(R);
+ return unsigned(LW) < unsigned(RW);
+ end;
+
+ -- R.2.2. UFix < unsigned
+ function "<" (L: UFix; R: unsigned) return boolean is
+ begin
+ return L < To_UFix(R);
+ end;
+
+ -- R.2.3. unsigned < UFix
+ function "<" (L: unsigned; R: UFix) return boolean is
+ begin
+ return To_UFix(L) < R;
+ end;
+
+ -- R.2.4. UFix < integer
+ function "<" (L: UFix; R: integer) return boolean is
+ variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
+ begin
+ Copy_V(S, R, clip_MS, clip_LS);
+ return L < S;
+ end;
+
+ -- R.2.5. integer < UFix
+ function "<" (L: integer; R: UFix) return boolean is
+ variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
+ begin
+ Copy_V(S, L, clip_MS, clip_LS);
+ return S < R;
+ end;
+
+ -- R.2.6. SFix < SFix
+ function "<" (L: SFix; R: SFix) return boolean is
+ variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto
+ Min(L'RIGHT, R'RIGHT));
+ begin
+ Copy_V(LW, L, clip_MS, clip_LS);
+ Copy_V(RW, R, clip_MS, clip_LS);
+ return signed(LW) < signed(RW);
+ end;
+
+ -- R.2.7. SFix < UFix
+ function "<" (L: SFix; R: UFix) return boolean is
+ begin
+ return L < To_SFix(R);
+ end;
+
+ -- R.2.8. UFix < SFix
+ function "<" (L: UFix; R: SFix) return boolean is
+ begin
+ return To_SFix(L) < R;
+ end;
+
+ -- R.2.9. SFix < signed
+ function "<" (L: SFix; R: signed) return boolean is
+ begin
+ return L < To_SFix(R);
+ end;
+
+ -- R.2.10. signed < SFix
+ function "<" (L: signed; R: SFix) return boolean is
+ begin
+ return To_SFix(L) < R;
+ end;
+
+ -- R.2.11. SFix < integer
+ function "<" (L: SFix; R: integer) return boolean is
+ variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
+ begin
+ Copy_V(S, R, clip_MS, clip_LS);
+ return L < S;
+ end;
+
+ -- R.2.12. integer < SFix
+ function "<" (L: integer; R: SFix) return boolean is
+ variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
+ begin
+ Copy_V(S, L, clip_MS, clip_LS);
+ return S < R;
+ end;
+
+
+ ----------------------------------------
+ -- R.3. Binary "/=" inequality operator
+ ----------------------------------------
+
+ -- R.3.1. UFix /= UFix
+ function "/=" (L: UFix; R: UFix) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.2. UFix /= unsigned
+ function "/=" (L: UFix; R: unsigned) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.3. unsigned /= UFix
+ function "/=" (L: unsigned; R: UFix) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.4. UFix /= integer
+ function "/=" (L: UFix; R: integer) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.5. integer /= UFix
+ function "/=" (L: integer; R: UFix) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.6. SFix /= SFix
+ function "/=" (L: SFix; R: SFix) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.7. SFix /= UFix
+ function "/=" (L: SFix; R: UFix) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.8. UFix /= SFix
+ function "/=" (L: UFix; R: SFix) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.9. SFix /= signed
+ function "/=" (L: SFix; R: signed) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.10. signed /= SFix
+ function "/=" (L: signed; R: SFix) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.11. SFix /= integer
+ function "/=" (L: SFix; R: integer) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+ -- R.3.12. integer /= SFix
+ function "/=" (L: integer; R: SFix) return boolean is
+ begin
+ return not (L = R);
+ end;
+
+
+ -----------------------------------------
+ -- R.4. Binary ">" greater-than operator
+ -----------------------------------------
+
+ -- R.4.1. UFix > UFix
+ function ">" (L: UFix; R: UFix) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.2. UFix > unsigned
+ function ">" (L: UFix; R: unsigned) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.3. unsigned > UFix
+ function ">" (L: unsigned; R: UFix) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.4. UFix > integer
+ function ">" (L: UFix; R: integer) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.5. integer > UFix
+ function ">" (L: integer; R: UFix) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.6. SFix > SFix
+ function ">" (L: SFix; R: SFix) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.7. SFix > UFix
+ function ">" (L: SFix; R: UFix) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.8. UFix > SFix
+ function ">" (L: UFix; R: SFix) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.9. SFix > signed
+ function ">" (L: SFix; R: signed) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.10. signed > SFix
+ function ">" (L: signed; R: SFix) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.11. SFix > integer
+ function ">" (L: SFix; R: integer) return boolean is
+ begin
+ return R < L;
+ end;
+
+ -- R.4.12. integer > SFix
+ function ">" (L: integer; R: SFix) return boolean is
+ begin
+ return R < L;
+ end;
+
+
+ ----------------------------------------------
+ -- R.5. Binary ">=" greater-or-equal operator
+ ----------------------------------------------
+
+ -- R.5.1. UFix >= UFix
+ function ">=" (L: UFix; R: UFix) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.2. UFix >= unsigned
+ function ">=" (L: UFix; R: unsigned) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.3. unsigned >= UFix
+ function ">=" (L: unsigned; R: UFix) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.4. UFix >= integer
+ function ">=" (L: UFix; R: integer) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.5. integer >= UFix
+ function ">=" (L: integer; R: UFix) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.6. SFix >= SFix
+ function ">=" (L: SFix; R: SFix) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.7. SFix >= UFix
+ function ">=" (L: SFix; R: UFix) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.8. UFix >= SFix
+ function ">=" (L: UFix; R: SFix) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.9. SFix >= signed
+ function ">=" (L: SFix; R: signed) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.10. signed >= SFix
+ function ">=" (L: signed; R: SFix) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.11. SFix >= integer
+ function ">=" (L: SFix; R: integer) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+ -- R.5.12. integer >= SFix
+ function ">=" (L: integer; R: SFix) return boolean is
+ begin
+ return not (L < R);
+ end;
+
+
+ -------------------------------------------
+ -- R.6. Binary "<=" less-or-equal operator
+ -------------------------------------------
+
+ -- R.6.1. UFix <= UFix
+ function "<=" (L: UFix; R: UFix) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.2. UFix <= unsigned
+ function "<=" (L: UFix; R: unsigned) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.3. unsigned <= UFix
+ function "<=" (L: unsigned; R: UFix) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.4. UFix <= integer
+ function "<=" (L: UFix; R: integer) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.5. integer <= UFix
+ function "<=" (L: integer; R: UFix) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.6. SFix <= SFix
+ function "<=" (L: SFix; R: SFix) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.7. SFix <= UFix
+ function "<=" (L: SFix; R: UFix) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.8. UFix <= SFix
+ function "<=" (L: UFix; R: SFix) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.9. SFix <= signed
+ function "<=" (L: SFix; R: signed) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.10. signed <= SFix
+ function "<=" (L: signed; R: SFix) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.11. SFix <= integer
+ function "<=" (L: SFix; R: integer) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ -- R.6.12. integer <= SFix
+ function "<=" (L: integer; R: SFix) return boolean is
+ begin
+ return not (R < L);
+ end;
+
+ ------------------------------------------------------------------
+ -- C. Concatenation operators between fixed-point operands, and
+ -- between fixed-point operands and other reasonable types.
+ -- Unlike the implicitly defined "&" operator, they preserve
+ -- place value and return an appropriately aligned subtype.
+ -- Preservation of place value means that some concatenation
+ -- operations are illegal. In particular, operations
+ -- [SFix & SFix] and [UFix & SFix] are illegal, and
+ -- the place values of operands in [SFix & UFix] and
+ -- [UFix & UFix] must match up - the rightmost subscript of
+ -- the left operand must be one higher than the leftmost
+ -- subscript of the right operand.
+ -- Single bits of type std_ulogic may be concatenated with
+ -- fixed-point types where there is no risk of losing
+ -- sign-extension information.
+ -- Because of the way VHDL defines implicit concatenation,
+ -- it is impossible to detect all these errors at compile time.
+ -- Instead they are detected by assertion statements at run time.
+ -- Tool vendors may choose to implement compile-time checks
+ -- so that the run-time checking overhead can be avoided.
+ ------------------------------------------------------------------
+
+ -- C.1.1. UFix := UFix & UFix
+ function "&" (L: UFix; R: UFix) return UFix is
+ begin
+ return UFix(concat(std_logic_vector(L), std_logic_vector(R)));
+ end;
+
+ -- C.1.2. UFix := UFix & std_ulogic
+ function "&" (L: UFix; R: std_ulogic) return UFix is
+ begin
+ return UFix(concat(std_logic_vector(L), R));
+ end;
+
+ -- C.1.3. UFix := std_ulogic & UFix
+ function "&" (L: std_ulogic; R: UFix) return UFix is
+ begin
+ return UFix(concat(L, std_logic_vector(R)));
+ end;
+
+
+ -- C.2.1. SFix := SFix & UFix
+ function "&" (L: SFix; R: UFix) return SFix is
+ begin
+ return SFix(concat(std_logic_vector(L), std_logic_vector(R)));
+ end;
+
+ -- C.2.2. SFix := SFix & SFix -- ILLEGAL
+ function "&" (L: SFix; R: SFix) return SFix is
+ begin
+ report concat_signLS_msg
+ severity concat_severity;
+ return SFix(concat(std_logic_vector(L), std_logic_vector(R)));
+ end;
+
+ -- C.2.3. SFix := SFix & std_ulogic
+ function "&" (L: SFix; R: std_ulogic) return SFix is
+ begin
+ return SFix(concat(std_logic_vector(L), R));
+ end;
+
+ -- C.2.4. SFix := std_ulogic & SFix
+ function "&" (L: std_ulogic; R: SFix) return SFix is
+ begin
+ assert std_match(L, R(R'LEFT))
+ report concat_sxt_msg
+ severity concat_severity;
+ return SFix(concat(L, std_logic_vector(R)));
+ end;
+
+
+end; -- package body fix_std;
diff --git a/lib/fixed/fixed_pkg_c.vhd b/lib/fixed/fixed_pkg_c.vhd
new file mode 100644
index 0000000..68acdd1
--- /dev/null
+++ b/lib/fixed/fixed_pkg_c.vhd
@@ -0,0 +1,7846 @@
+------------------------------------------------------------------------------
+-- "fixed_pkg" package contains functions for fixed point math.
+-- Please see the documentation for the fixed point package.
+-- This package should be compiled into "ieee_proposed" and used as follows:
+-- use ieee.std_logic_1164.all;
+-- use ieee.numeric_std.all;
+-- use ieee_proposed.fixed_pkg.all;
+-- Last Modified: $Date: 2008-08-23 08:20:29 $
+-- RCS ID: $Id: fixed_pkg_c.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+--
+-- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org)
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+-- synthesis translate_off
+use std.textio.all;
+-- synthesis translate_on
+
+package fixed_pkg is
+ --%%% Uncomment the Generics
+-- new work.fixed_generic_pkg
+-- generic map (
+-- fixed_round_style => true; -- fixed_round
+-- fixed_overflow_style => true; -- fixed_saturate
+-- fixed_guard_bits => 3; -- number of guard bits
+-- no_warning => false -- show warnings
+-- );
+ --%%% REMOVE THE REST OF THIS FILE.
+ constant fixed_round_style : BOOLEAN := false; -- round
+ constant fixed_overflow_style : BOOLEAN := false; -- saturate
+ constant fixed_guard_bits : NATURAL := 3; -- number of guard bits
+ constant no_warning : BOOLEAN := false; -- issue warnings
+ -- Author David Bishop (dbishop@vhdl.org)
+ -- These 5 constants are used as defaults.
+ -- There is a mechanism to override them in every function
+ constant fixed_round : BOOLEAN := true; -- Turn on rounding routine
+ constant fixed_truncate : BOOLEAN := false; -- Trun off rounding routine
+ constant fixed_saturate : BOOLEAN := true; -- Saturate large numbers
+ constant fixed_wrap : BOOLEAN := false; -- Wrap large numbers
+ constant fixedsynth_or_real : BOOLEAN := true; -- differed constant
+ -- base Unsigned fixed point type, downto direction assumed
+ type ufixed is array (INTEGER range <>) of STD_LOGIC;
+ -- base Signed fixed point type, downto direction assumed
+ type sfixed is array (INTEGER range <>) of STD_LOGIC;
+ -----------------------------------------------------------------------------
+ -- Fixed point type is defined as follows:
+ -- 0000000000
+ -- 4321012345
+ -- 4 0 -5
+ -- The decimal point is assumed between the "0" and "-1" index
+ -- Thus "0011010000" = 6.5 and would be written as 00110.10000
+ -- All types are assumed to be in the "downto" direction.
+
+ --===========================================================================
+ -- Arithmetic Operators:
+ --===========================================================================
+ -- Modify the sign of the number, 2's complement
+ function "abs" (arg : sfixed) return sfixed;
+ function "-" (arg : sfixed)return sfixed;
+
+ -- Convert a signed fixed to an unsigned fixed
+ function "abs" (arg : sfixed) return ufixed;
+
+ -- Addition
+ -- ufixed(a downto b) + ufixed(c downto d)
+ -- = ufixed(max(a,c)+1 downto min(b,d))
+ function "+" (l, r : ufixed) return ufixed;
+
+ -- sfixed(a downto b) + sfixed(c downto d)
+ -- = sfixed(max(a,c)+1 downto min(b,d))
+ function "+" (l, r : sfixed) return sfixed;
+
+ -- Subtraction
+ -- ufixed(a downto b) - ufixed(c downto d)
+ -- = ufixed(max(a,c)+1 downto min(b,d))
+ function "-" (l, r : ufixed) return ufixed;
+
+ -- sfixed(a downto b) - sfixed(c downto d)
+ -- = sfixed(max(a,c)+1 downto min(b,d))
+ function "-" (l, r : sfixed) return sfixed;
+
+ -- Multiplication
+ -- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
+ function "*" (l, r : ufixed) return ufixed;
+
+ -- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
+ function "*" (l, r : sfixed) return sfixed;
+
+ -- Division
+ -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
+ function "/" (l, r : ufixed) return ufixed;
+
+ -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
+ function "/" (l, r : sfixed) return sfixed;
+
+ -- Remainder
+ -- ufixed (a downto b) rem ufixed (c downto d)
+ -- = ufixed (min(a,c) downto min(b,d))
+ function "rem" (l, r : ufixed) return ufixed;
+
+ -- sfixed (a downto b) rem sfixed (c downto d)
+ -- = sfixed (min(a,c) downto min(b,d))
+ function "rem" (l, r : sfixed) return sfixed;
+
+ -- Modulo
+ -- ufixed (a downto b) mod ufixed (c downto d)
+ -- = ufixed (min(a,c) downto min(b, d))
+ function "mod" (l, r : ufixed) return ufixed;
+
+ -- sfixed (a downto b) mod sfixed (c downto d)
+ -- = sfixed (c downto min(b, d))
+ function "mod" (l, r : sfixed) return sfixed;
+
+ ----------------------------------------------------------------------------
+ -- Overload routines. In these routines the "real" or "natural" (integer)
+ -- are converted into a fixed point number and then the operation is
+ -- performed. It is assumed that the array will be large enough.
+ -- If the input is "real" then the real number is converted into a fixed of
+ -- the same size as the fixed point input. If the number is an "integer"
+ -- then it is converted into fixed with the range (l'high downto 0).
+ ----------------------------------------------------------------------------
+ -- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
+ function "+" (l : ufixed; r : REAL) return ufixed;
+
+ -- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
+ function "+" (l : REAL; r : ufixed) return ufixed;
+
+ -- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
+ function "+" (l : ufixed; r : NATURAL) return ufixed;
+
+ -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
+ function "+" (l : NATURAL; r : ufixed) return ufixed;
+
+ -- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
+ function "-" (l : ufixed; r : REAL) return ufixed;
+
+ -- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
+ function "-" (l : REAL; r : ufixed) return ufixed;
+
+ -- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
+ function "-" (l : ufixed; r : NATURAL) return ufixed;
+
+ -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
+ function "-" (l : NATURAL; r : ufixed) return ufixed;
+
+ -- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
+ function "*" (l : ufixed; r : REAL) return ufixed;
+
+ -- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
+ function "*" (l : REAL; r : ufixed) return ufixed;
+
+ -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
+ function "*" (l : ufixed; r : NATURAL) return ufixed;
+
+ -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
+ function "*" (l : NATURAL; r : ufixed) return ufixed;
+
+ -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
+ function "/" (l : ufixed; r : REAL) return ufixed;
+
+ -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
+ function "/" (l : REAL; r : ufixed) return ufixed;
+
+ -- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
+ function "/" (l : ufixed; r : NATURAL) return ufixed;
+
+ -- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
+ function "/" (l : NATURAL; r : ufixed) return ufixed;
+
+ -- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
+ function "rem" (l : ufixed; r : REAL) return ufixed;
+
+ -- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
+ function "rem" (l : REAL; r : ufixed) return ufixed;
+
+ -- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto min(b,0))
+ function "rem" (l : ufixed; r : NATURAL) return ufixed;
+
+ -- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto min(d,0))
+ function "rem" (l : NATURAL; r : ufixed) return ufixed;
+
+ -- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
+ function "mod" (l : ufixed; r : REAL) return ufixed;
+
+ -- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
+ function "mod" (l : REAL; r : ufixed) return ufixed;
+
+ -- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto min(b,0))
+ function "mod" (l : ufixed; r : NATURAL) return ufixed;
+
+ -- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto min(d,0))
+ function "mod" (l : NATURAL; r : ufixed) return ufixed;
+
+ -- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
+ function "+" (l : sfixed; r : REAL) return sfixed;
+
+ -- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
+ function "+" (l : REAL; r : sfixed) return sfixed;
+
+ -- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
+ function "+" (l : sfixed; r : INTEGER) return sfixed;
+
+ -- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto min(0,d))
+ function "+" (l : INTEGER; r : sfixed) return sfixed;
+
+ -- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
+ function "-" (l : sfixed; r : REAL) return sfixed;
+
+ -- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
+ function "-" (l : REAL; r : sfixed) return sfixed;
+
+ -- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
+ function "-" (l : sfixed; r : INTEGER) return sfixed;
+
+ -- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto min(0,d))
+ function "-" (l : INTEGER; r : sfixed) return sfixed;
+
+ -- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
+ function "*" (l : sfixed; r : REAL) return sfixed;
+
+ -- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
+ function "*" (l : REAL; r : sfixed) return sfixed;
+
+ -- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
+ function "*" (l : sfixed; r : INTEGER) return sfixed;
+
+ -- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
+ function "*" (l : INTEGER; r : sfixed) return sfixed;
+
+ -- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
+ function "/" (l : sfixed; r : REAL) return sfixed;
+
+ -- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
+ function "/" (l : REAL; r : sfixed) return sfixed;
+
+ -- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
+ function "/" (l : sfixed; r : INTEGER) return sfixed;
+
+ -- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
+ function "/" (l : INTEGER; r : sfixed) return sfixed;
+
+ -- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
+ function "rem" (l : sfixed; r : REAL) return sfixed;
+
+ -- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
+ function "rem" (l : REAL; r : sfixed) return sfixed;
+
+ -- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto min(b,0))
+ function "rem" (l : sfixed; r : INTEGER) return sfixed;
+
+ -- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto min(d,0))
+ function "rem" (l : INTEGER; r : sfixed) return sfixed;
+
+ -- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
+ function "mod" (l : sfixed; r : REAL) return sfixed;
+
+ -- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
+ function "mod" (l : REAL; r : sfixed) return sfixed;
+
+ -- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto min(b,0))
+ function "mod" (l : sfixed; r : INTEGER) return sfixed;
+
+ -- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto min(d,0))
+ function "mod" (l : INTEGER; r : sfixed) return sfixed;
+
+ -- This version of divide gives the user more control
+ -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
+ function divide (
+ l, r : ufixed;
+ constant round_style : BOOLEAN := fixed_round_style;
+ constant guard_bits : NATURAL := fixed_guard_bits)
+ return ufixed;
+
+ -- This version of divide gives the user more control
+ -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
+ function divide (
+ l, r : sfixed;
+ constant round_style : BOOLEAN := fixed_round_style;
+ constant guard_bits : NATURAL := fixed_guard_bits)
+ return sfixed;
+
+ -- These functions return 1/X
+ -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
+ function reciprocal (
+ arg : ufixed; -- fixed point input
+ constant round_style : BOOLEAN := fixed_round_style;
+ constant guard_bits : NATURAL := fixed_guard_bits)
+ return ufixed;
+
+ -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
+ function reciprocal (
+ arg : sfixed; -- fixed point input
+ constant round_style : BOOLEAN := fixed_round_style;
+ constant guard_bits : NATURAL := fixed_guard_bits)
+ return sfixed;
+
+ -- REM function
+ -- ufixed (a downto b) rem ufixed (c downto d)
+ -- = ufixed (min(a,c) downto min(b,d))
+ function remainder (
+ l, r : ufixed;
+ constant round_style : BOOLEAN := fixed_round_style)
+ return ufixed;
+
+ -- sfixed (a downto b) rem sfixed (c downto d)
+ -- = sfixed (min(a,c) downto min(b,d))
+ function remainder (
+ l, r : sfixed;
+ constant round_style : BOOLEAN := fixed_round_style)
+ return sfixed;
+
+ -- mod function
+ -- ufixed (a downto b) mod ufixed (c downto d)
+ -- = ufixed (min(a,c) downto min(b, d))
+ function modulo (
+ l, r : ufixed;
+ constant round_style : BOOLEAN := fixed_round_style)
+ return ufixed;
+
+ -- sfixed (a downto b) mod sfixed (c downto d)
+ -- = sfixed (c downto min(b, d))
+ function modulo (
+ l, r : sfixed;
+ constant overflow_style : BOOLEAN := fixed_overflow_style;
+ constant round_style : BOOLEAN := fixed_round_style)
+ return sfixed;
+
+ -- Procedure for those who need an "accumulator" function.
+ -- add_carry (ufixed(a downto b), ufixed (c downto d))
+ -- = ufixed (max(a,c) downto min(b,d))
+ procedure add_carry (
+ L, R : in ufixed;
+ c_in : in STD_ULOGIC;
+ result : out ufixed;
+ c_out : out STD_ULOGIC);
+
+ -- add_carry (sfixed(a downto b), sfixed (c downto d))
+ -- = sfixed (max(a,c) downto min(b,d))
+ procedure add_carry (
+ L, R : in sfixed;
+ c_in : in STD_ULOGIC;
+ result : out sfixed;
+ c_out : out STD_ULOGIC);
+
+ -- Scales the result by a power of 2. Width of input = width of output with
+ -- the decimal point moved.
+ function scalb (y : ufixed; N : integer) return ufixed;
+ function scalb (y : ufixed; N : SIGNED) return ufixed;
+ function scalb (y : sfixed; N : integer) return sfixed;
+ function scalb (y : sfixed; N : SIGNED) return sfixed;
+
+ function Is_Negative (arg : sfixed) return BOOLEAN;
+ --===========================================================================
+ -- Comparison Operators
+ --===========================================================================
+ function ">" (l, r : ufixed) return BOOLEAN;
+ function ">" (l, r : sfixed) return BOOLEAN;
+ function "<" (l, r : ufixed) return BOOLEAN;
+ function "<" (l, r : sfixed) return BOOLEAN;
+ function "<=" (l, r : ufixed) return BOOLEAN;
+ function "<=" (l, r : sfixed) return BOOLEAN;
+ function ">=" (l, r : ufixed) return BOOLEAN;
+ function ">=" (l, r : sfixed) return BOOLEAN;
+ function "=" (l, r : ufixed) return BOOLEAN;
+ function "=" (l, r : sfixed) return BOOLEAN;
+ function "/=" (l, r : ufixed) return BOOLEAN;
+ function "/=" (l, r : sfixed) return BOOLEAN;
+ --%%% Uncomment the following (new syntax)
+-- function "?=" (L, R : ufixed) return BOOLEAN;
+-- function "?=" (L, R : sfixed) return BOOLEAN;
+-- --%%% remove the following (old syntax)
+ function \?=\ (L, R : ufixed) return STD_ULOGIC;
+ function \?=\ (L, R : sfixed) return STD_ULOGIC;
+ -- These need to be overloaded for sfixed and ufixed
+ function \?/=\ (L, R : ufixed) return STD_ULOGIC;
+ function \?>\ (L, R : ufixed) return STD_ULOGIC;
+ function \?>=\ (L, R : ufixed) return STD_ULOGIC;
+ function \?<\ (L, R : ufixed) return STD_ULOGIC;
+ function \?<=\ (L, R : ufixed) return STD_ULOGIC;
+ function \?/=\ (L, R : sfixed) return STD_ULOGIC;
+ function \?>\ (L, R : sfixed) return STD_ULOGIC;
+ function \?>=\ (L, R : sfixed) return STD_ULOGIC;
+ function \?<\ (L, R : sfixed) return STD_ULOGIC;
+ function \?<=\ (L, R : sfixed) return STD_ULOGIC;
+ -- %%% Replace with the following (new syntax)
+-- function "?=" (L, R : ufixed) return STD_ULOGIC;
+-- function "?/=" (L, R : ufixed) return STD_ULOGIC;
+-- function "?>" (L, R : ufixed) return STD_ULOGIC;
+-- function "?>=" (L, R : ufixed) return STD_ULOGIC;
+-- function "?<" (L, R : ufixed) return STD_ULOGIC;
+-- function "?<=" (L, R : ufixed) return STD_ULOGIC;
+-- function "?=" (L, R : sfixed) return STD_ULOGIC;
+-- function "?/=" (L, R : sfixed) return STD_ULOGIC;
+-- function "?>" (L, R : sfixed) return STD_ULOGIC;
+-- function "?>=" (L, R : sfixed) return STD_ULOGIC;
+-- function "?<" (L, R : sfixed) return STD_ULOGIC;
+-- function "?<=" (L, R : sfixed) return STD_ULOGIC;
+
+ function std_match (L, R : ufixed) return BOOLEAN;
+ function std_match (L, R : sfixed) return BOOLEAN;
+
+ -- Overloads the default "maximum" and "minimum" function
+ function maximum (l, r : ufixed) return ufixed;
+ function minimum (l, r : ufixed) return ufixed;
+ function maximum (l, r : sfixed) return sfixed;
+ function minimum (l, r : sfixed) return sfixed;
+
+ ----------------------------------------------------------------------------
+ -- In these compare functions a natural is converted into a
+ -- fixed point number of the bounds "max(l'high,0) downto 0"
+ ----------------------------------------------------------------------------
+ function "=" (l : ufixed; r : NATURAL) return BOOLEAN;
+ function "/=" (l : ufixed; r : NATURAL) return BOOLEAN;
+ function ">=" (l : ufixed; r : NATURAL) return BOOLEAN;
+ function "<=" (l : ufixed; r : NATURAL) return BOOLEAN;
+ function ">" (l : ufixed; r : NATURAL) return BOOLEAN;
+ function "<" (l : ufixed; r : NATURAL) return BOOLEAN;
+
+ function "=" (l : NATURAL; r : ufixed) return BOOLEAN;
+ function "/=" (l : NATURAL; r : ufixed) return BOOLEAN;
+ function ">=" (l : NATURAL; r : ufixed) return BOOLEAN;
+ function "<=" (l : NATURAL; r : ufixed) return BOOLEAN;
+ function ">" (l : NATURAL; r : ufixed) return BOOLEAN;
+ function "<" (l : NATURAL; r : ufixed) return BOOLEAN;
+
+ ----------------------------------------------------------------------------
+ -- In these compare functions a real is converted into a
+ -- fixed point number of the bounds "l'high+1 downto l'low"
+ ----------------------------------------------------------------------------
+ function "=" (l : ufixed; r : REAL) return BOOLEAN;
+ function "/=" (l : ufixed; r : REAL) return BOOLEAN;
+ function ">=" (l : ufixed; r : REAL) return BOOLEAN;
+ function "<=" (l : ufixed; r : REAL) return BOOLEAN;
+ function ">" (l : ufixed; r : REAL) return BOOLEAN;
+ function "<" (l : ufixed; r : REAL) return BOOLEAN;
+
+ function "=" (l : REAL; r : ufixed) return BOOLEAN;
+ function "/=" (l : REAL; r : ufixed) return BOOLEAN;
+ function ">=" (l : REAL; r : ufixed) return BOOLEAN;
+ function "<=" (l : REAL; r : ufixed) return BOOLEAN;
+ function ">" (l : REAL; r : ufixed) return BOOLEAN;
+ function "<" (l : REAL; r : ufixed) return BOOLEAN;
+
+ ----------------------------------------------------------------------------
+ -- In these compare functions an integer is converted into a
+ -- fixed point number of the bounds "max(l'high,1) downto 0"
+ ----------------------------------------------------------------------------
+ function "=" (l : sfixed; r : INTEGER) return BOOLEAN;
+ function "/=" (l : sfixed; r : INTEGER) return BOOLEAN;
+ function ">=" (l : sfixed; r : INTEGER) return BOOLEAN;
+ function "<=" (l : sfixed; r : INTEGER) return BOOLEAN;
+ function ">" (l : sfixed; r : INTEGER) return BOOLEAN;
+ function "<" (l : sfixed; r : INTEGER) return BOOLEAN;
+
+ function "=" (l : INTEGER; r : sfixed) return BOOLEAN;
+ function "/=" (l : INTEGER; r : sfixed) return BOOLEAN;
+ function ">=" (l : INTEGER; r : sfixed) return BOOLEAN;
+ function "<=" (l : INTEGER; r : sfixed) return BOOLEAN;
+ function ">" (l : INTEGER; r : sfixed) return BOOLEAN;
+ function "<" (l : INTEGER; r : sfixed) return BOOLEAN;
+
+ ----------------------------------------------------------------------------
+ -- In these compare functions a real is converted into a
+ -- fixed point number of the bounds "l'high+1 downto l'low"
+ ----------------------------------------------------------------------------
+ function "=" (l : sfixed; r : REAL) return BOOLEAN;
+ function "/=" (l : sfixed; r : REAL) return BOOLEAN;
+ function ">=" (l : sfixed; r : REAL) return BOOLEAN;
+ function "<=" (l : sfixed; r : REAL) return BOOLEAN;
+ function ">" (l : sfixed; r : REAL) return BOOLEAN;
+ function "<" (l : sfixed; r : REAL) return BOOLEAN;
+
+ function "=" (l : REAL; r : sfixed) return BOOLEAN;
+ function "/=" (l : REAL; r : sfixed) return BOOLEAN;
+ function ">=" (l : REAL; r : sfixed) return BOOLEAN;
+ function "<=" (l : REAL; r : sfixed) return BOOLEAN;
+ function ">" (l : REAL; r : sfixed) return BOOLEAN;
+ function "<" (l : REAL; r : sfixed) return BOOLEAN;
+
+ --===========================================================================
+ -- Shift and Rotate Functions.
+ -- Note that sra and sla are not the same as the BIT_VECTOR version
+ --===========================================================================
+ function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed;
+ function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed;
+ function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed;
+ function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed;
+ function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed;
+ function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed;
+ function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed;
+ function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed;
+ function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed;
+ function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed;
+ function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed;
+ function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed;
+ function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed;
+ function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed;
+ function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed;
+ function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed;
+
+ ----------------------------------------------------------------------------
+ -- logical functions
+ ----------------------------------------------------------------------------
+ function "not" (L : ufixed) return ufixed;
+ function "and" (L, R : ufixed) return ufixed;
+ function "or" (L, R : ufixed) return ufixed;
+ function "nand" (L, R : ufixed) return ufixed;
+ function "nor" (L, R : ufixed) return ufixed;
+ function "xor" (L, R : ufixed) return ufixed;
+ function "xnor" (L, R : ufixed) return ufixed;
+ function "not" (L : sfixed) return sfixed;
+ function "and" (L, R : sfixed) return sfixed;
+ function "or" (L, R : sfixed) return sfixed;
+ function "nand" (L, R : sfixed) return sfixed;
+ function "nor" (L, R : sfixed) return sfixed;
+ function "xor" (L, R : sfixed) return sfixed;
+ function "xnor" (L, R : sfixed) return sfixed;
+
+ -- Vector and std_ulogic functions, same as functions in numeric_std
+ function "and" (L : STD_ULOGIC; R : ufixed) return ufixed;
+ function "and" (L : ufixed; R : STD_ULOGIC) return ufixed;
+ function "or" (L : STD_ULOGIC; R : ufixed) return ufixed;
+ function "or" (L : ufixed; R : STD_ULOGIC) return ufixed;
+ function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed;
+ function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed;
+ function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed;
+ function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed;
+ function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed;
+ function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed;
+ function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed;
+ function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed;
+ function "and" (L : STD_ULOGIC; R : sfixed) return sfixed;
+ function "and" (L : sfixed; R : STD_ULOGIC) return sfixed;
+ function "or" (L : STD_ULOGIC; R : sfixed) return sfixed;
+ function "or" (L : sfixed; R : STD_ULOGIC) return sfixed;
+ function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed;
+ function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed;
+ function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed;
+ function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed;
+ function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed;
+ function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed;
+ function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed;
+ function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed;
+
+ -- Reduction operators, same as numeric_std functions
+ -- %%% remove 12 functions (old syntax)
+ function and_reduce(arg : ufixed) return STD_ULOGIC;
+ function nand_reduce(arg : ufixed) return STD_ULOGIC;
+ function or_reduce(arg : ufixed) return STD_ULOGIC;
+ function nor_reduce(arg : ufixed) return STD_ULOGIC;
+ function xor_reduce(arg : ufixed) return STD_ULOGIC;
+ function xnor_reduce(arg : ufixed) return STD_ULOGIC;
+ function and_reduce(arg : sfixed) return STD_ULOGIC;
+ function nand_reduce(arg : sfixed) return STD_ULOGIC;
+ function or_reduce(arg : sfixed) return STD_ULOGIC;
+ function nor_reduce(arg : sfixed) return STD_ULOGIC;
+ function xor_reduce(arg : sfixed) return STD_ULOGIC;
+ function xnor_reduce(arg : sfixed) return STD_ULOGIC;
+ -- %%% Uncomment the following 12 functions (new syntax)
+ -- function "and" ( arg : ufixed ) RETURN std_ulogic;
+ -- function "nand" ( arg : ufixed ) RETURN std_ulogic;
+ -- function "or" ( arg : ufixed ) RETURN std_ulogic;
+ -- function "nor" ( arg : ufixed ) RETURN std_ulogic;
+ -- function "xor" ( arg : ufixed ) RETURN std_ulogic;
+ -- function "xnor" ( arg : ufixed ) RETURN std_ulogic;
+ -- function "and" ( arg : sfixed ) RETURN std_ulogic;
+ -- function "nand" ( arg : sfixed ) RETURN std_ulogic;
+ -- function "or" ( arg : sfixed ) RETURN std_ulogic;
+ -- function "nor" ( arg : sfixed ) RETURN std_ulogic;
+ -- function "xor" ( arg : sfixed ) RETURN std_ulogic;
+ -- function "xnor" ( arg : sfixed ) RETURN std_ulogic;
+
+ -- returns arg'low-1 if not found
+ function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
+ function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
+
+ -- returns arg'high+1 if not found
+ function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
+ function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
+
+ --===========================================================================
+ -- RESIZE Functions
+ --===========================================================================
+ -- resizes the number (larger or smaller)
+ -- The returned result will be ufixed (left_index downto right_index)
+ -- If "round_style" is true, then the result will be rounded. If the MSB
+ -- of the remainder is a "1" AND the LSB of the unround result is a '1' or
+ -- the lower bits of the remainder include a '1' then the result will be
+ -- increased by the smallest representable number for that type.
+ -- The default is "true" for round_style.
+ -- "overflow_style" can be "true" (saturate mode) or "false" (wrap mode).
+ -- In saturate mode, if the number overflows then the largest possible
+ -- representable number is returned. If wrap mode, then the upper bits
+ -- of the number are truncated.
+ function resize (
+ arg : ufixed; -- input
+ constant left_index : INTEGER; -- integer portion
+ constant right_index : INTEGER; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding
+ return ufixed;
+
+ -- "size_res" functions create the size of the output from the length
+ -- of the "size_res" input. The actual value of "size_res" is not used.
+ function resize (
+ arg : ufixed; -- input
+ size_res : ufixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding
+ return ufixed;
+
+ -- Note that in "wrap" mode the sign bit is not replicated. Thus the
+ -- resize of a negative number can have a positive result in wrap mode.
+ function resize (
+ arg : sfixed; -- input
+ constant left_index : INTEGER; -- integer portion
+ constant right_index : INTEGER; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return sfixed;
+
+ function resize (
+ arg : sfixed; -- input
+ size_res : sfixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return sfixed;
+
+ --===========================================================================
+ -- Conversion Functions
+ --===========================================================================
+ -- integer (natural) to unsigned fixed point.
+ -- arguments are the upper and lower bounds of the number, thus
+ -- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
+ function to_ufixed (
+ arg : NATURAL; -- integer
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER := 0; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
+ return ufixed;
+
+ function to_ufixed (
+ arg : NATURAL; -- integer
+ size_res : ufixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
+ return ufixed;
+
+ -- real to unsigned fixed point
+ function to_ufixed (
+ arg : REAL; -- real
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
+ constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
+ return ufixed;
+
+ function to_ufixed (
+ arg : REAL; -- real
+ size_res : ufixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
+ constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
+ return ufixed;
+
+ -- unsigned to unsigned fixed point
+ function to_ufixed (
+ arg : UNSIGNED; -- unsigned
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER := 0; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return ufixed;
+
+ function to_ufixed (
+ arg : UNSIGNED; -- unsigned
+ size_res : ufixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return ufixed;
+
+ -- Performs a casting. ufixed (arg'range) is returned
+ function to_ufixed (
+ arg : UNSIGNED) -- unsigned
+ return ufixed;
+
+ -- unsigned fixed point to unsigned
+ function to_unsigned (
+ arg : ufixed; -- fixed point input
+ constant size : NATURAL; -- length of output
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return UNSIGNED;
+
+ -- unsigned fixed point to unsigned
+ function to_unsigned (
+ arg : ufixed; -- fixed point input
+ size_res : UNSIGNED; -- used for length of output
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return UNSIGNED;
+
+ -- unsigned fixed point to real
+ function to_real (
+ arg : ufixed) -- fixed point input
+ return REAL;
+
+ -- unsigned fixed point to integer
+ function to_integer (
+ arg : ufixed; -- fixed point input
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return NATURAL;
+
+ -- Integer to sfixed
+ function to_sfixed (
+ arg : INTEGER; -- integer
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER := 0; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return sfixed;
+
+ function to_sfixed (
+ arg : INTEGER; -- integer
+ size_res : sfixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return sfixed;
+
+ -- Real to sfixed
+ function to_sfixed (
+ arg : REAL; -- real
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
+ constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
+ return sfixed;
+
+ function to_sfixed (
+ arg : REAL; -- real
+ size_res : sfixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
+ constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
+ return sfixed;
+
+ -- signed to sfixed
+ function to_sfixed (
+ arg : SIGNED; -- signed
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER := 0; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return sfixed;
+
+ function to_sfixed (
+ arg : SIGNED; -- signed
+ size_res : sfixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return sfixed;
+
+ -- signed to sfixed (output assumed to be size of signed input)
+ function to_sfixed (
+ arg : SIGNED) -- signed
+ return sfixed;
+
+ -- unsigned fixed point to signed fixed point (adds a "0" sign bit)
+ function add_sign (
+ arg : ufixed) -- unsigned fixed point
+ return sfixed;
+
+ -- signed fixed point to signed
+ function to_signed (
+ arg : sfixed; -- fixed point input
+ constant size : NATURAL; -- length of output
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return SIGNED;
+
+ -- signed fixed point to signed
+ function to_signed (
+ arg : sfixed; -- fixed point input
+ size_res : SIGNED; -- used for length of output
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return SIGNED;
+
+ -- signed fixed point to real
+ function to_real (
+ arg : sfixed) -- fixed point input
+ return REAL;
+
+ -- signed fixed point to integer
+ function to_integer (
+ arg : sfixed; -- fixed point input
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return INTEGER;
+
+ -- Because of the farily complicated sizing rules in the fixed point
+ -- packages these functions are provided to compute the result ranges
+ -- Example:
+ -- signal uf1 : ufixed (3 downto -3);
+ -- signal uf2 : ufixed (4 downto -2);
+ -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
+ -- ufixed_low (3, -3, '*', 4, -2));
+ -- uf1multuf2 <= uf1 * uf2;
+ -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod)
+ function ufixed_high (left_index, right_index : INTEGER;
+ operation : CHARACTER := 'X';
+ left_index2, right_index2 : INTEGER := 0)
+ return INTEGER;
+ function ufixed_low (left_index, right_index : INTEGER;
+ operation : CHARACTER := 'X';
+ left_index2, right_index2 : INTEGER := 0)
+ return INTEGER;
+ function sfixed_high (left_index, right_index : INTEGER;
+ operation : CHARACTER := 'X';
+ left_index2, right_index2 : INTEGER := 0)
+ return INTEGER;
+ function sfixed_low (left_index, right_index : INTEGER;
+ operation : CHARACTER := 'X';
+ left_index2, right_index2 : INTEGER := 0)
+ return INTEGER;
+ -- Same as above, but using the "size_res" input only for their ranges:
+ -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
+ -- ufixed_low (uf1, '*', uf2));
+ -- uf1multuf2 <= uf1 * uf2;
+ function ufixed_high (size_res : ufixed;
+ operation : CHARACTER := 'X';
+ size_res2 : ufixed)
+ return INTEGER;
+ function ufixed_low (size_res : ufixed;
+ operation : CHARACTER := 'X';
+ size_res2 : ufixed)
+ return INTEGER;
+ function sfixed_high (size_res : sfixed;
+ operation : CHARACTER := 'X';
+ size_res2 : sfixed)
+ return INTEGER;
+ function sfixed_low (size_res : sfixed;
+ operation : CHARACTER := 'X';
+ size_res2 : sfixed)
+ return INTEGER;
+
+ -- purpose: returns a saturated number
+ function saturate (
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed;
+
+ -- purpose: returns a saturated number
+ function saturate (
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed;
+
+ function saturate (
+ size_res : ufixed) -- only the size of this is used
+ return ufixed;
+
+ function saturate (
+ size_res : sfixed) -- only the size of this is used
+ return sfixed;
+
+ --===========================================================================
+ -- Translation Functions
+ --===========================================================================
+ -- Maps meta-logical values
+ function to_01 (
+ s : ufixed; -- fixed point input
+ constant XMAP : STD_LOGIC := '0') -- Map x to
+ return ufixed;
+
+ -- maps meta-logical values
+ function to_01 (
+ s : sfixed; -- fixed point input
+ constant XMAP : STD_LOGIC := '0') -- Map x to
+ return sfixed;
+
+ function Is_X (arg : ufixed) return BOOLEAN;
+ function Is_X (arg : sfixed) return BOOLEAN;
+ function to_X01 (arg : ufixed) return ufixed;
+ function to_X01 (arg : sfixed) return sfixed;
+ function to_X01Z (arg : ufixed) return ufixed;
+ function to_X01Z (arg : sfixed) return sfixed;
+ function to_UX01 (arg : ufixed) return ufixed;
+ function to_UX01 (arg : sfixed) return sfixed;
+
+ -- straight vector conversion routines, needed for synthesis.
+ -- These functions are here so that a std_logic_vector can be
+ -- converted to and from sfixed and ufixed. Note that you can
+ -- not cast these vectors because of their negative index.
+ function to_slv (
+ arg : ufixed) -- fp vector
+ return STD_LOGIC_VECTOR;
+-- alias to_StdLogicVector is to_slv [ufixed return STD_LOGIC_VECTOR];
+-- alias to_Std_Logic_Vector is to_slv [ufixed return STD_LOGIC_VECTOR];
+
+ function to_slv (
+ arg : sfixed) -- fp vector
+ return STD_LOGIC_VECTOR;
+-- alias to_StdLogicVector is to_slv [sfixed return STD_LOGIC_VECTOR];
+-- alias to_Std_Logic_Vector is to_slv [sfixed return STD_LOGIC_VECTOR];
+
+ function to_sulv (
+ arg : ufixed) -- fp vector
+ return STD_ULOGIC_VECTOR;
+-- alias to_StdULogicVector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
+-- alias to_Std_ULogic_Vector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
+
+ function to_sulv (
+ arg : sfixed) -- fp vector
+ return STD_ULOGIC_VECTOR;
+-- alias to_StdULogicVector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
+-- alias to_Std_ULogic_Vector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
+
+ function to_ufixed (
+ arg : STD_LOGIC_VECTOR; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed;
+
+ function to_ufixed (
+ arg : STD_LOGIC_VECTOR; -- shifted vector
+ size_res : ufixed) -- for size only
+ return ufixed;
+
+ function to_sfixed (
+ arg : STD_LOGIC_VECTOR; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed;
+
+ function to_sfixed (
+ arg : STD_LOGIC_VECTOR; -- shifted vector
+ size_res : sfixed) -- for size only
+ return sfixed;
+
+ function to_ufixed (
+ arg : STD_ULOGIC_VECTOR; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed;
+
+ function to_ufixed (
+ arg : STD_ULOGIC_VECTOR; -- shifted vector
+ size_res : ufixed) -- for size only
+ return ufixed;
+
+ function to_sfixed (
+ arg : STD_ULOGIC_VECTOR; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed;
+
+ function to_sfixed (
+ arg : STD_ULOGIC_VECTOR; -- shifted vector
+ size_res : sfixed) -- for size only
+ return sfixed;
+
+ -- As a concession to those who use a graphical DSP environment,
+ -- these functions take parameters in those tools format and create
+ -- fixed point numbers. These functions are designed to convert from
+ -- a std_logic_vector to the VHDL fixed point format using the conventions
+ -- of these packages. In a pure VHDL environment you should use the
+ -- "to_ufixed" and "to_sfixed" routines.
+ -- Unsigned fixed point
+ function to_UFix (
+ arg : STD_LOGIC_VECTOR;
+ width : NATURAL; -- width of vector
+ fraction : NATURAL) -- width of fraction
+ return ufixed;
+ -- signed fixed point
+ function to_SFix (
+ arg : STD_LOGIC_VECTOR;
+ width : NATURAL; -- width of vector
+ fraction : NATURAL) -- width of fraction
+ return sfixed;
+ -- finding the bounds of a number. These functions can be used like this:
+ -- signal xxx : ufixed (7 downto -3);
+ -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
+ -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
+ -- downto UFix_low(11, 3, "+", 11, 3));
+ -- Where "11" is the width of xxx (xxx'length),
+ -- and 3 is the lower bound (abs (xxx'low))
+ -- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
+ function UFix_high (width, fraction : NATURAL;
+ operation : CHARACTER := 'X';
+ width2, fraction2 : NATURAL := 0)
+ return INTEGER;
+ function UFix_low (width, fraction : NATURAL;
+ operation : CHARACTER := 'X';
+ width2, fraction2 : NATURAL := 0)
+ return INTEGER;
+ -- Same as above but for signed fixed point. Note that the width
+ -- of a signed fixed point number ignores the sign bit, thus
+ -- width = sxxx'length-1
+ function SFix_high (width, fraction : NATURAL;
+ operation : CHARACTER := 'X';
+ width2, fraction2 : NATURAL := 0)
+ return INTEGER;
+ function SFix_low (width, fraction : NATURAL;
+ operation : CHARACTER := 'X';
+ width2, fraction2 : NATURAL := 0)
+ return INTEGER;
+ --===========================================================================
+ -- string and textio Functions
+ --===========================================================================
+-- rtl_synthesis off
+-- synthesis translate_off
+ -- purpose: writes fixed point into a line
+ procedure WRITE (
+ L : inout LINE; -- input line
+ VALUE : in ufixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0);
+
+ -- purpose: writes fixed point into a line
+ procedure WRITE (
+ L : inout LINE; -- input line
+ VALUE : in sfixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0);
+
+ procedure READ(L : inout LINE;
+ VALUE : out ufixed);
+
+ procedure READ(L : inout LINE;
+ VALUE : out ufixed;
+ GOOD : out BOOLEAN);
+
+ procedure READ(L : inout LINE;
+ VALUE : out sfixed);
+
+ procedure READ(L : inout LINE;
+ VALUE : out sfixed;
+ GOOD : out BOOLEAN);
+
+ alias bwrite is WRITE [LINE, ufixed, SIDE, width];
+ alias bwrite is WRITE [LINE, sfixed, SIDE, width];
+ alias bread is READ [LINE, ufixed];
+ alias bread is READ [LINE, ufixed, BOOLEAN];
+ alias bread is READ [LINE, sfixed];
+ alias bread is READ [LINE, sfixed, BOOLEAN];
+
+ -- octal read and write
+ procedure OWRITE (
+ L : inout LINE; -- input line
+ VALUE : in ufixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0);
+
+ procedure OWRITE (
+ L : inout LINE; -- input line
+ VALUE : in sfixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0);
+
+ procedure OREAD(L : inout LINE;
+ VALUE : out ufixed);
+
+ procedure OREAD(L : inout LINE;
+ VALUE : out ufixed;
+ GOOD : out BOOLEAN);
+
+ procedure OREAD(L : inout LINE;
+ VALUE : out sfixed);
+
+ procedure OREAD(L : inout LINE;
+ VALUE : out sfixed;
+ GOOD : out BOOLEAN);
+
+ -- hex read and write
+ procedure HWRITE (
+ L : inout LINE; -- input line
+ VALUE : in ufixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0);
+
+ -- purpose: writes fixed point into a line
+ procedure HWRITE (
+ L : inout LINE; -- input line
+ VALUE : in sfixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0);
+
+ procedure HREAD(L : inout LINE;
+ VALUE : out ufixed);
+
+ procedure HREAD(L : inout LINE;
+ VALUE : out ufixed;
+ GOOD : out BOOLEAN);
+
+ procedure HREAD(L : inout LINE;
+ VALUE : out sfixed);
+
+ procedure HREAD(L : inout LINE;
+ VALUE : out sfixed;
+ GOOD : out BOOLEAN);
+
+ -- returns a string, useful for:
+ -- assert (x = y) report "error found " & to_string(x) severity error;
+ function to_string (
+ value : ufixed;
+ justified : SIDE := right;
+ field : WIDTH := 0
+ ) return STRING;
+
+ alias to_bstring is to_string [ufixed, SIDE, width return STRING];
+
+ function to_ostring (
+ value : ufixed;
+ justified : SIDE := right;
+ field : WIDTH := 0
+ ) return STRING;
+
+ function to_hstring (
+ value : ufixed;
+ justified : SIDE := right;
+ field : WIDTH := 0
+ ) return STRING;
+
+ function to_string (
+ value : sfixed;
+ justified : SIDE := right;
+ field : WIDTH := 0
+ ) return STRING;
+
+ alias to_bstring is to_string [sfixed, SIDE, width return STRING];
+
+ function to_ostring (
+ value : sfixed;
+ justified : SIDE := right;
+ field : WIDTH := 0
+ ) return STRING;
+
+ function to_hstring (
+ value : sfixed;
+ justified : SIDE := right;
+ field : WIDTH := 0
+ ) return STRING;
+
+ -- From string functions allow you to convert a string into a fixed
+ -- point number. Example:
+ -- signal uf1 : ufixed (3 downto -3);
+ -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
+ -- The "." is optional in this syntax, however it exist and is
+ -- in the wrong location an error is produced. Overflow will
+ -- result in saturation.
+ function from_string (
+ bstring : STRING; -- binary string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed;
+ alias from_bstring is from_string [STRING, INTEGER, INTEGER return ufixed];
+
+ -- Octal and hex conversions work as follows:
+ -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
+ -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
+ function from_ostring (
+ ostring : STRING; -- Octal string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed;
+
+ function from_hstring (
+ hstring : STRING; -- hex string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed;
+
+ function from_string (
+ bstring : STRING; -- binary string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed;
+ alias from_bstring is from_string [STRING, INTEGER, INTEGER return sfixed];
+
+ function from_ostring (
+ ostring : STRING; -- Octal string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed;
+
+ function from_hstring (
+ hstring : STRING; -- hex string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed;
+
+ -- Same as above, "size_res" is used for it's range only.
+ function from_string (
+ bstring : STRING; -- binary string
+ size_res : ufixed)
+ return ufixed;
+ alias from_bstring is from_string [STRING, ufixed return ufixed];
+
+ function from_ostring (
+ ostring : STRING; -- Octal string
+ size_res : ufixed)
+ return ufixed;
+
+ function from_hstring (
+ hstring : STRING; -- hex string
+ size_res : ufixed)
+ return ufixed;
+
+ function from_string (
+ bstring : STRING; -- binary string
+ size_res : sfixed)
+ return sfixed;
+ alias from_bstring is from_string [STRING, sfixed return sfixed];
+
+ function from_ostring (
+ ostring : STRING; -- Octal string
+ size_res : sfixed)
+ return sfixed;
+
+ function from_hstring (
+ hstring : STRING; -- hex string
+ size_res : sfixed)
+ return sfixed;
+
+ -- Direct converstion functions. Example:
+ -- signal uf1 : ufixed (3 downto -3);
+ -- uf1 <= from_string ("0110.100"); -- 6.5
+ -- In this case the "." is not optional, and the size of
+ -- the output must match exactly.
+ function from_string (
+ bstring : STRING) -- binary string
+ return ufixed;
+ alias from_bstring is from_string [STRING return ufixed];
+
+ -- Direct octal and hex converstion functions. In this case
+ -- the string lengths must match. Example:
+ -- signal sf1 := sfixed (5 downto -3);
+ -- sf1 <= from_ostring ("71.4") -- -6.5
+ function from_ostring (
+ ostring : STRING) -- Octal string
+ return ufixed;
+
+ function from_hstring (
+ hstring : STRING) -- hex string
+ return ufixed;
+
+ function from_string (
+ bstring : STRING) -- binary string
+ return sfixed;
+ alias from_bstring is from_string [STRING return sfixed];
+
+ function from_ostring (
+ ostring : STRING) -- Octal string
+ return sfixed;
+
+ function from_hstring (
+ hstring : STRING) -- hex string
+ return sfixed;
+
+-- synthesis translate_on
+-- rtl_synthesis on
+ -- This type is here for the floating point package.
+ type round_type is (round_nearest, -- Default, nearest LSB '0'
+ round_inf, -- Round to positive
+ round_neginf, -- Round to negate
+ round_zero); -- Round towards zero
+ -- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
+ -- and FE_TOWARDZERO floating point rounding macros.
+ function to_StdLogicVector (
+ arg : ufixed) -- fp vector
+ return STD_LOGIC_VECTOR;
+ function to_Std_Logic_Vector (
+ arg : ufixed) -- fp vector
+ return STD_LOGIC_VECTOR;
+ function to_StdLogicVector (
+ arg : sfixed) -- fp vector
+ return STD_LOGIC_VECTOR;
+ function to_Std_Logic_Vector (
+ arg : sfixed) -- fp vector
+ return STD_LOGIC_VECTOR;
+end package fixed_pkg;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use std.textio.all;
+use ieee.std_logic_textio.all; -- %%% for testing only
+package body fixed_pkg is
+ -- Author David Bishop (dbishop@vhdl.org)
+ -- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
+ -- null array constants
+ constant NAUF : ufixed (0 downto 1) := (others => '0');
+ constant NASF : sfixed (0 downto 1) := (others => '0');
+ constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
+
+ -- This differed constant will tell you if the package body is synthesizable
+ -- or implemented as real numbers, set to "true" if synthesizable.
+-- constant fixedsynth_or_real : BOOLEAN := true;
+
+ --%%% Can be removed in vhdl-200x, will be implicit.
+ -- purpose: To find the largest of 2 numbers
+ function maximum (l, r : INTEGER)
+ return INTEGER is
+ begin -- function maximum
+ if L > R then return L;
+ else return R;
+ end if;
+ end function maximum;
+
+ function minimum (l, r : INTEGER)
+ return INTEGER is
+ begin -- function minimum
+ if L > R then return R;
+ else return L;
+ end if;
+ end function minimum;
+
+ -- %%% Remove the following function (duplicates of new numeric_std)
+ function "sra" (arg : SIGNED; count : INTEGER)
+ return SIGNED is
+ begin
+ if (COUNT >= 0) then
+ return SHIFT_RIGHT(arg, count);
+ else
+ return SHIFT_LEFT(arg, -count);
+ end if;
+ end function "sra";
+
+ -- %%% Replace or_reducex with "or", and_reducex with "and", and
+ -- %%% xor_reducex with "xor", then remove the following 3 functions
+ -- purpose: OR all of the bits in a vector together
+ -- This is a copy of the proposed "or_reduce" from 1076.3
+ function or_reducex (arg : STD_LOGIC_VECTOR)
+ return STD_LOGIC is
+ variable Upper, Lower : STD_LOGIC;
+ variable Half : INTEGER;
+ variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
+ variable Result : STD_LOGIC;
+ begin
+ if (arg'length < 1) then -- In the case of a NULL range
+ Result := '0';
+ else
+ BUS_int := to_ux01 (arg);
+ if (BUS_int'length = 1) then
+ Result := BUS_int (BUS_int'left);
+ elsif (BUS_int'length = 2) then
+ Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
+ else
+ Half := (BUS_int'length + 1) / 2 + BUS_int'right;
+ Upper := or_reducex (BUS_int (BUS_int'left downto Half));
+ Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right));
+ Result := Upper or Lower;
+ end if;
+ end if;
+ return Result;
+ end function or_reducex;
+
+ -- purpose: AND all of the bits in a vector together
+ -- This is a copy of the proposed "and_reduce" from 1076.3
+ function and_reducex (arg : STD_LOGIC_VECTOR)
+ return STD_LOGIC is
+ variable Upper, Lower : STD_LOGIC;
+ variable Half : INTEGER;
+ variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
+ variable Result : STD_LOGIC;
+ begin
+ if (arg'length < 1) then -- In the case of a NULL range
+ Result := '1';
+ else
+ BUS_int := to_ux01 (arg);
+ if (BUS_int'length = 1) then
+ Result := BUS_int (BUS_int'left);
+ elsif (BUS_int'length = 2) then
+ Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
+ else
+ Half := (BUS_int'length + 1) / 2 + BUS_int'right;
+ Upper := and_reducex (BUS_int (BUS_int'left downto Half));
+ Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right));
+ Result := Upper and Lower;
+ end if;
+ end if;
+ return Result;
+ end function and_reducex;
+
+ function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ variable Upper, Lower : STD_ULOGIC;
+ variable Half : INTEGER;
+ variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
+ variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
+ begin
+ if (arg'length >= 1) then
+ BUS_int := to_ux01 (arg);
+ if (BUS_int'length = 1) then
+ Result := BUS_int (BUS_int'left);
+ elsif (BUS_int'length = 2) then
+ Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
+ else
+ Half := (BUS_int'length + 1) / 2 + BUS_int'right;
+ Upper := xor_reducex (BUS_int (BUS_int'left downto Half));
+ Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right));
+ Result := Upper xor Lower;
+ end if;
+ end if;
+ return Result;
+ end function xor_reducex;
+
+ --%%% remove the following function and table
+ -- Match table, copied form new std_logic_1164
+ type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
+ constant match_logic_table : stdlogic_table := (
+ -----------------------------------------------------
+ -- U X 0 1 Z W L H - | |
+ -----------------------------------------------------
+ ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
+ ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
+ ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
+ ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
+ ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
+ ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
+ );
+
+ constant no_match_logic_table : stdlogic_table := (
+ -----------------------------------------------------
+ -- U X 0 1 Z W L H - | |
+ -----------------------------------------------------
+ ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
+ ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
+ ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
+ ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
+ ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
+ ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
+ ('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
+ );
+
+ -------------------------------------------------------------------
+ -- ?= functions, Similar to "std_match", but returns "std_ulogic".
+ -------------------------------------------------------------------
+ -- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
+ function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
+ begin
+ return match_logic_table (l, r);
+ end function \?=\;
+ -- %%% END FUNCTION "?=";
+ -- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
+ function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
+ begin
+ return no_match_logic_table (l, r);
+ end function \?/=\;
+ -- %%% END FUNCTION "?/=";
+ -- %%% end remove
+
+ -- Special version of "minimum" to do some boundary checking without errors
+ function mins (l, r : INTEGER)
+ return INTEGER is
+ begin -- function mins
+ if (L = INTEGER'low or R = INTEGER'low) then
+ return 0; -- error condition
+ end if;
+ return minimum (L, R);
+ end function mins;
+
+ -- Special version of "minimum" to do some boundary checking with errors
+ function mine (l, r : INTEGER)
+ return INTEGER is
+ begin -- function mine
+ if (L = INTEGER'low or R = INTEGER'low) then
+ report "FIXED_GENERIC_PKG: Unbounded number passed, was a literal used?"
+ severity error;
+ return 0;
+ end if;
+ return minimum (L, R);
+ end function mine;
+
+ -- The following functions are used only internally. Every function
+ -- calls "cleanvec" either directly or indirectly.
+ -- purpose: Fixes "downto" problem and resolves meta states
+ function cleanvec (
+ arg : sfixed) -- input
+ return sfixed is
+ constant left_index : INTEGER := maximum(arg'left, arg'right);
+ constant right_index : INTEGER := mins(arg'left, arg'right);
+ variable result : sfixed (arg'range);
+ begin -- function cleanvec
+ assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
+ report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
+ severity error;
+ return arg;
+ end function cleanvec;
+
+ -- purpose: Fixes "downto" problem and resolves meta states
+ function cleanvec (
+ arg : ufixed) -- input
+ return ufixed is
+ constant left_index : INTEGER := maximum(arg'left, arg'right);
+ constant right_index : INTEGER := mins(arg'left, arg'right);
+ variable result : ufixed (arg'range);
+ begin -- function cleanvec
+ assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
+ report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
+ severity error;
+ return arg;
+ end function cleanvec;
+
+ -- Type cast a "unsigned" into a "ufixed", used internally
+ function to_fixed (
+ arg : UNSIGNED; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed is
+ variable result : ufixed (left_index downto right_index);
+-- variable j : INTEGER := arg'high; -- index for arg
+ begin -- function to_fixed
+ result := ufixed(arg);
+-- floop : for i in result'range loop
+-- result(i) := arg(j); -- res(4) := arg (4 + 3)
+-- j := j - 1;
+-- end loop floop;
+ return result;
+ end function to_fixed;
+
+ -- Type cast a "signed" into an "sfixed", used internally
+ function to_fixed (
+ arg : SIGNED; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed is
+ variable result : sfixed (left_index downto right_index);
+-- variable j : INTEGER := arg'high; -- index for arg
+ begin -- function to_fixed
+ result := sfixed(arg);
+-- floop : for i in result'range loop
+-- result(i) := arg(j); -- res(4) := arg (4 + 3)
+-- j := j - 1;
+-- end loop floop;
+ return result;
+ end function to_fixed;
+
+ -- Type cast a "ufixed" into an "unsigned", used internally
+ function to_uns (
+ arg : ufixed) -- fp vector
+ return UNSIGNED is
+ subtype t is UNSIGNED(arg'high - arg'low downto 0);
+ variable slv : t;
+ begin -- function to_uns
+ slv := t(arg);
+-- floop : for i in slv'range loop
+-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
+-- end loop floop;
+ return UNSIGNED(to_X01(std_logic_vector(slv)));
+ end function to_uns;
+
+ -- Type cast an "sfixed" into a "signed", used internally
+ function to_s (
+ arg : sfixed) -- fp vector
+ return SIGNED is
+ subtype t is SIGNED(arg'high - arg'low downto 0);
+ variable slv : t;
+ begin -- function to_s
+ slv := t(arg);
+-- floop : for i in slv'range loop
+-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
+-- end loop floop;
+ return SIGNED(to_X01(std_logic_vector(slv)));
+ end function to_s;
+
+ -- adds 1 to the LSB of the number
+ procedure round_up (arg : in ufixed;
+ result : out ufixed;
+ overflowx : out BOOLEAN) is
+ variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0) :=
+ (others => '0');
+ begin -- round_up
+ arguns (arguns'high-1 downto 0) := to_uns (arg);
+ resuns := arguns + 1;
+ result := to_fixed(resuns(arg'high-arg'low
+ downto 0), arg'high, arg'low);
+ overflowx := (resuns(resuns'high) = '1');
+ end procedure round_up;
+
+ -- adds 1 to the LSB of the number
+ procedure round_up (arg : in sfixed;
+ result : out sfixed;
+ overflowx : out BOOLEAN) is
+ variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
+ begin -- round_up
+ args (args'high-1 downto 0) := to_s (arg);
+ args(args'high) := arg(arg'high); -- sign extend
+ ress := args + 1;
+ result := to_fixed(ress (ress'high-1
+ downto 0), arg'high, arg'low);
+ overflowx := ((arg(arg'high) /= ress(ress'high-1))
+ and (or_reducex (STD_LOGIC_VECTOR(ress)) /= '0'));
+ end procedure round_up;
+
+ -- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
+ -- when the remainder is > 0.5. If the remainder IS 0.5 then if the
+ -- bottom bit is a "1" it is rounded, otherwise it remains the same.
+ function round_fixed (arg : ufixed;
+ remainder : ufixed;
+ overflow_style : BOOLEAN := fixed_overflow_style)
+ return ufixed is
+ variable rounds : BOOLEAN;
+ variable round_overflow : BOOLEAN;
+ variable result : ufixed (arg'range);
+ begin
+ rounds := false;
+ if (remainder'length > 1) then
+ if (remainder (remainder'high) = '1') then
+ rounds := (arg(arg'low) = '1')
+ or (or_reducex (to_slv(remainder(remainder'high-1 downto
+ remainder'low))) = '1');
+ end if;
+ else
+ rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
+ end if;
+ if rounds then
+ round_up(arg => arg,
+ result => result,
+ overflowx => round_overflow);
+ else
+ result := arg;
+ end if;
+ if (overflow_style = fixed_saturate) and round_overflow then
+ result := saturate (result'high, result'low);
+ end if;
+ return result;
+ end function round_fixed;
+
+ -- Rounding case statement
+ function round_fixed (arg : sfixed;
+ remainder : sfixed;
+ overflow_style : BOOLEAN := fixed_overflow_style)
+ return sfixed is
+ variable rounds : BOOLEAN;
+ variable round_overflow : BOOLEAN;
+ variable result : sfixed (arg'range);
+ begin
+ rounds := false;
+ if (remainder'length > 1) then
+ if (remainder (remainder'high) = '1') then
+ rounds := (arg(arg'low) = '1')
+ or (or_reducex (to_slv(remainder(remainder'high-1 downto
+ remainder'low))) = '1');
+ end if;
+ else
+ rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
+ end if;
+ if rounds then
+ round_up(arg => arg,
+ result => result,
+ overflowx => round_overflow);
+ else
+ result := arg;
+ end if;
+ if round_overflow then
+ if (overflow_style = fixed_saturate) then
+ if arg(arg'high) = '0' then
+ result := saturate (result'high, result'low);
+ else
+ result := not saturate (result'high, result'low);
+ end if;
+-- else
+-- result(result'high) := arg(arg'high); -- fix sign bit in wrap
+ end if;
+ end if;
+ return result;
+ end function round_fixed;
+
+-----------------------------------------------------------------------------
+-- Visible functions
+-----------------------------------------------------------------------------
+
+ -- casting functions. These are needed for synthesis where typically
+ -- the only input and output type is a std_logic_vector.
+ function to_slv (
+ arg : ufixed) -- fixed point vector
+ return STD_LOGIC_VECTOR is
+ subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
+ variable slv : t;
+ begin
+ if arg'length < 1 then
+ return NSLV;
+ end if;
+ slv := t (arg);
+ return slv;
+ end function to_slv;
+
+ function to_slv (
+ arg : sfixed) -- fixed point vector
+ return STD_LOGIC_VECTOR is
+ subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
+ variable slv : t;
+ begin
+ if arg'length < 1 then
+ return NSLV;
+ end if;
+ slv := t (arg);
+ return slv;
+ end function to_slv;
+
+ function to_sulv (
+ arg : ufixed) -- fixed point vector
+ return STD_ULOGIC_VECTOR is
+ begin
+ return to_stdulogicvector (to_slv(arg));
+ end function to_sulv;
+
+ function to_sulv (
+ arg : sfixed) -- fixed point vector
+ return STD_ULOGIC_VECTOR is
+ begin
+ return to_stdulogicvector (to_slv(arg));
+ end function to_sulv;
+
+ function to_ufixed (
+ arg : STD_LOGIC_VECTOR; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed is
+ variable result : ufixed (left_index downto right_index);
+ begin
+ if (arg'length < 1 or right_index > left_index) then
+ return NAUF;
+ end if;
+ if (arg'length /= result'length) then
+ report "FIXED_GENERIC_PKG.TO_UFIXED (STD_LOGIC_VECTOR) "
+ & "Vector lengths do not match. Input length is "
+ & INTEGER'image(arg'length) & " and output will be "
+ & INTEGER'image(result'length) & " wide."
+ severity error;
+ return NAUF;
+ else
+ result := to_fixed (arg => UNSIGNED(arg),
+ left_index => left_index,
+ right_index => right_index);
+ return result;
+ end if;
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : STD_LOGIC_VECTOR; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed is
+ variable result : sfixed (left_index downto right_index);
+ begin
+ if (arg'length < 1 or right_index > left_index) then
+ return NASF;
+ end if;
+ if (arg'length /= result'length) then
+ report "FIXED_GENERIC_PKG.TO_SFIXED (STD_LOGIC_VECTOR) "
+ & "Vector lengths do not match. Input length is "
+ & INTEGER'image(arg'length) & " and output will be "
+ & INTEGER'image(result'length) & " wide."
+ severity error;
+ return NASF;
+ else
+ result := to_fixed (arg => SIGNED(arg),
+ left_index => left_index,
+ right_index => right_index);
+ return result;
+ end if;
+ end function to_sfixed;
+
+ function to_ufixed (
+ arg : STD_ULOGIC_VECTOR; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed is
+ begin
+ return to_ufixed (arg => to_stdlogicvector(arg),
+ left_index => left_index,
+ right_index => right_index);
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : STD_ULOGIC_VECTOR; -- shifted vector
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed is
+ begin
+ return to_sfixed (arg => to_stdlogicvector(arg),
+ left_index => left_index,
+ right_index => right_index);
+ end function to_sfixed;
+
+ -- Two's complement number, Grows the vector by 1 bit.
+ -- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
+ function "abs" (
+ arg : sfixed) -- fixed point input
+ return sfixed is
+ constant left_index : INTEGER := arg'high;
+ constant right_index : INTEGER := mine(arg'low, arg'low);
+ variable ressns : SIGNED (arg'length downto 0);
+ variable result : sfixed (left_index+1 downto right_index);
+ begin
+ if (arg'length < 1 or result'length < 1) then
+ return NASF;
+ end if;
+ ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
+ ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
+ result := to_fixed (abs(ressns), left_index+1, right_index);
+ return result;
+ end function "abs";
+
+ -- also grows the vector by 1 bit.
+ function "-" (
+ arg : sfixed) -- fixed point input
+ return sfixed is
+ constant left_index : INTEGER := arg'high+1;
+ constant right_index : INTEGER := mine(arg'low, arg'low);
+ variable ressns : SIGNED (arg'length downto 0);
+ variable result : sfixed (left_index downto right_index);
+ begin
+ if (arg'length < 1 or result'length < 1) then
+ return NASF;
+ end if;
+ ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
+ ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
+ result := to_fixed (-ressns, left_index, right_index);
+ return result;
+ end function "-";
+
+ function "abs" (arg : sfixed) return ufixed is
+ constant left_index : INTEGER := arg'high;
+ constant right_index : INTEGER := mine(arg'low, arg'low);
+ variable xarg : sfixed(left_index+1 downto right_index);
+ variable result : ufixed(left_index downto right_index);
+ begin
+ if arg'length < 1 then
+ return NAUF;
+ end if;
+ xarg := abs(arg);
+ result := ufixed (xarg (left_index downto right_index));
+ return result;
+ end function "abs";
+
+ -- Addition
+ function "+" (
+ l, r : ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
+ return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
+ constant left_index : INTEGER := maximum(l'high, r'high)+1;
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable result : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (left_index-right_index
+ downto 0);
+ variable result_slv : UNSIGNED (left_index-right_index
+ downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ return NAUF;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ result_slv := lslv + rslv;
+ result := to_fixed(result_slv, left_index, right_index);
+ return result;
+ end function "+";
+
+ function "+" (
+ l, r : sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
+ return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
+ constant left_index : INTEGER := maximum(l'high, r'high)+1;
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable result : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (left_index-right_index downto 0);
+ variable result_slv : SIGNED (left_index-right_index downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ return NASF;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ result_slv := lslv + rslv;
+ result := to_fixed(result_slv, left_index, right_index);
+ return result;
+ end function "+";
+
+ -- Subtraction
+ function "-" (
+ l, r : ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
+ return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
+ constant left_index : INTEGER := maximum(l'high, r'high)+1;
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable result : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (left_index-right_index
+ downto 0);
+ variable result_slv : UNSIGNED (left_index-right_index
+ downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ return NAUF;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ result_slv := lslv - rslv;
+ result := to_fixed(result_slv, left_index, right_index);
+ return result;
+ end function "-";
+
+ function "-" (
+ l, r : sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
+ return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
+ constant left_index : INTEGER := maximum(l'high, r'high)+1;
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable result : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (left_index-right_index downto 0);
+ variable result_slv : SIGNED (left_index-right_index downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ return NASF;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ result_slv := lslv - rslv;
+ result := to_fixed(result_slv, left_index, right_index);
+ return result;
+ end function "-";
+
+ function "*" (
+ l, r : ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
+ return ufixed is -- ufixed(a+c+1 downto b+d)
+ variable lslv : UNSIGNED (l'length-1 downto 0);
+ variable rslv : UNSIGNED (r'length-1 downto 0);
+ variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
+ variable result : ufixed (l'high + r'high+1 downto
+ mine(l'low, l'low) + mine(r'low, r'low));
+ begin
+ if (l'length < 1 or r'length < 1 or
+ result'length /= result_slv'length) then
+ return NAUF;
+ end if;
+ lslv := to_uns (cleanvec(l));
+ rslv := to_uns (cleanvec(r));
+ result_slv := lslv * rslv;
+ result := to_fixed (result_slv, result'high, result'low);
+ return result;
+ end function "*";
+
+ function "*" (
+ l, r : sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
+ return sfixed is -- sfixed(a+c+1 downto b+d)
+ variable lslv : SIGNED (l'length-1 downto 0);
+ variable rslv : SIGNED (r'length-1 downto 0);
+ variable result_slv : SIGNED (r'length+l'length-1 downto 0);
+ variable result : sfixed (l'high + r'high+1 downto
+ mine(l'low, l'low) + mine(r'low, r'low));
+ begin
+ if (l'length < 1 or r'length < 1 or
+ result'length /= result_slv'length) then
+ return NASF;
+ end if;
+ lslv := to_s (cleanvec(l));
+ rslv := to_s (cleanvec(r));
+ result_slv := lslv * rslv;
+ result := to_fixed (result_slv, result'high, result'low);
+ return result;
+ end function "*";
+
+ function "/" (
+ l, r : ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
+ return ufixed is -- ufixed(a-d downto b-c-1)
+ begin
+ return divide (l, r);
+ end function "/";
+
+ function "/" (
+ l, r : sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
+ return sfixed is -- sfixed(a-d+1 downto b-c)
+ begin
+ return divide (l, r);
+ end function "/";
+
+ -- This version of divide gives the user more control
+ -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
+ function divide (
+ l, r : ufixed;
+ constant round_style : BOOLEAN := fixed_round_style;
+ constant guard_bits : NATURAL := fixed_guard_bits)
+ return ufixed is
+ variable result : ufixed (l'high - mine(r'low, r'low)
+ downto mine (l'low, l'low) - r'high -1);
+ variable dresult : ufixed (result'high downto result'low -guard_bits);
+ variable lresize : ufixed (l'high downto l'high - dresult'length+1);
+ variable lslv : UNSIGNED (lresize'length-1 downto 0);
+ variable rslv : UNSIGNED (r'length-1 downto 0);
+ variable result_slv : UNSIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1 or
+ mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+ return NAUF;
+ end if;
+ lresize := resize (l, lresize'high, lresize'low);
+ lslv := to_uns (cleanvec (lresize));
+ rslv := to_uns (cleanvec (r));
+ if (rslv = 0) then
+ report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
+ result := saturate (result'high, result'low); -- saturate
+ else
+ result_slv := lslv / rslv;
+ dresult := to_fixed (result_slv, dresult'high, dresult'low);
+ result := resize (arg => dresult,
+ left_index => result'high,
+ right_index => result'low,
+ round_style => round_style,
+ overflow_style => fixed_wrap); -- overflow impossible
+ end if;
+ return result;
+ end function divide;
+
+ -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
+ function divide (
+ l, r : sfixed;
+ constant round_style : BOOLEAN := fixed_round_style;
+ constant guard_bits : NATURAL := fixed_guard_bits)
+ return sfixed is
+ variable result : sfixed (l'high - mine(r'low, r'low)+1
+ downto mine (l'low, l'low) - r'high);
+ variable dresult : sfixed (result'high downto result'low-guard_bits);
+ variable lresize : sfixed (l'high+1 downto l'high+1 -dresult'length+1);
+ variable lslv : SIGNED (lresize'length-1 downto 0);
+ variable rslv : SIGNED (r'length-1 downto 0);
+ variable result_slv : SIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1 or
+ mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+ return NASF;
+ end if;
+ lresize := resize (l, lresize'high, lresize'low);
+ lslv := to_s (cleanvec (lresize));
+ rslv := to_s (cleanvec (r));
+ if (rslv = 0) then
+ report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
+ result := saturate (result'high, result'low);
+ else
+ result_slv := lslv / rslv;
+ dresult := to_fixed (result_slv, dresult'high, dresult'low);
+ result := resize (arg => dresult,
+ left_index => result'high,
+ right_index => result'low,
+ round_style => round_style,
+ overflow_style => fixed_wrap); -- overflow impossible
+ end if;
+ return result;
+ end function divide;
+
+ -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
+ function reciprocal (
+ arg : ufixed; -- fixed point input
+ constant round_style : BOOLEAN := fixed_round_style;
+ constant guard_bits : NATURAL := fixed_guard_bits)
+ return ufixed is
+ constant one : ufixed (0 downto 0) := "1";
+ begin
+ return divide(l => one,
+ r => arg,
+ round_style => round_style,
+ guard_bits => guard_bits);
+ end function reciprocal;
+
+ -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
+ function reciprocal (
+ arg : sfixed; -- fixed point input
+ constant round_style : BOOLEAN := fixed_round_style;
+ constant guard_bits : NATURAL := fixed_guard_bits)
+ return sfixed is
+ constant one : sfixed (1 downto 0) := "01"; -- extra bit.
+ variable resultx : sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
+ begin
+ if (arg'length < 1 or resultx'length < 1) then
+ return NASF;
+ else
+ resultx := divide(l => one,
+ r => arg,
+ round_style => round_style,
+ guard_bits => guard_bits);
+ return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
+ end if;
+ end function reciprocal;
+
+ -- ufixed (a downto b) rem ufixed (c downto d)
+ -- = ufixed (min(a,c) downto min(b,d))
+ function "rem" (
+ l, r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return remainder (l => l,
+ r => r,
+ round_style => fixed_round_style);
+ end function "rem";
+
+ -- remainder
+ -- sfixed (a downto b) rem sfixed (c downto d)
+ -- = sfixed (min(a,c) downto min(b,d))
+ function "rem" (
+ l, r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return remainder (l => l,
+ r => r,
+ round_style => fixed_round_style);
+ end function "rem";
+
+ -- ufixed (a downto b) rem ufixed (c downto d)
+ -- = ufixed (min(a,c) downto min(b,d))
+ function remainder (
+ l, r : ufixed; -- fixed point input
+ constant round_style : BOOLEAN := fixed_round_style)
+ return ufixed is
+ variable result : ufixed (minimum(l'high, r'high) downto mine(l'low, r'low));
+ variable dresult : ufixed (r'high downto r'low);
+ variable lresize : ufixed (maximum(l'high, r'low) downto mins(r'low, r'low));
+ variable lslv : UNSIGNED (lresize'length-1 downto 0);
+ variable rslv : UNSIGNED (r'length-1 downto 0);
+ variable result_slv : UNSIGNED (rslv'range);
+ begin
+ if (l'length < 1 or r'length < 1 or
+ mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+ return NAUF;
+ end if;
+ lresize := resize (arg => l,
+ left_index => lresize'high,
+ right_index => lresize'low,
+ overflow_style => fixed_wrap, -- vector only grows
+ round_style => fixed_truncate);
+ lslv := to_uns (lresize);
+ rslv := to_uns (cleanvec(r));
+ if (rslv = 0) then
+ report "FIXED_GENERIC_PKG.rem uFixed point Division by zero" severity error;
+ result := saturate (result'high, result'low); -- saturate
+ else
+ if (r'low <= l'high) then
+ result_slv := lslv rem rslv;
+ dresult := to_fixed (result_slv, dresult'high, dresult'low);
+ result := resize (arg => dresult,
+ left_index => result'high,
+ right_index => result'low,
+ overflow_style => fixed_wrap,
+ round_style => round_style);
+-- result(result'high downto r'low) := dresult(result'high downto r'low);
+ end if;
+ if l'low < r'low then
+ result(mins(r'low-1, l'high) downto l'low) :=
+ cleanvec(l(mins(r'low-1, l'high) downto l'low));
+ end if;
+ end if;
+ return result;
+ end function remainder;
+
+ -- remainder
+ -- sfixed (a downto b) rem sfixed (c downto d)
+ -- = sfixed (min(a,c) downto min(b,d))
+ function remainder (
+ l, r : sfixed; -- fixed point input
+ constant round_style : BOOLEAN := fixed_round_style)
+ return sfixed is
+ variable l_abs : ufixed (l'range);
+ variable r_abs : ufixed (r'range);
+ variable result : sfixed (minimum(r'high, l'high) downto mine(r'low, l'low));
+ variable neg_result : sfixed (minimum(r'high, l'high)+1 downto mins(r'low, l'low));
+ begin
+ if (l'length < 1 or r'length < 1 or
+ mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+ return NASF;
+ end if;
+ l_abs := abs(l);
+ r_abs := abs(r);
+ result := sfixed(remainder (l => l_abs,
+ r => r_abs,
+ round_style => round_style));
+ neg_result := -result;
+ if l(l'high) = '1' then
+ result := neg_result(result'range);
+ end if;
+ return result;
+ end function remainder;
+
+ -- modulo
+ -- ufixed (a downto b) mod ufixed (c downto d)
+ -- = ufixed (min(a,c) downto min(b, d))
+ function "mod" (
+ l, r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return modulo (l => l,
+ r => r,
+ round_style => fixed_round_style);
+ end function "mod";
+
+ -- sfixed (a downto b) mod sfixed (c downto d)
+ -- = sfixed (c downto min(b, d))
+ function "mod" (
+ l, r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return modulo(l => l,
+ r => r,
+ round_style => fixed_round_style);
+ end function "mod";
+
+ -- modulo
+ -- ufixed (a downto b) mod ufixed (c downto d)
+ -- = ufixed (min(a,c) downto min(b, d))
+ function modulo (
+ l, r : ufixed; -- fixed point input
+ constant round_style : BOOLEAN := fixed_round_style)
+ return ufixed is
+ begin
+ return remainder(l => l,
+ r => r,
+ round_style => round_style);
+ end function modulo;
+
+ -- sfixed (a downto b) mod sfixed (c downto d)
+ -- = sfixed (c downto min(b, d))
+ function modulo (
+ l, r : sfixed; -- fixed point input
+ constant overflow_style : BOOLEAN := fixed_overflow_style;
+ constant round_style : BOOLEAN := fixed_round_style)
+ return sfixed is
+ variable l_abs : ufixed (l'range);
+ variable r_abs : ufixed (r'range);
+ variable result : sfixed (r'high downto
+ mine(r'low, l'low));
+ variable dresult : sfixed (minimum(r'high, l'high)+1 downto
+ mins(r'low, l'low));
+ variable dresult_not_zero : BOOLEAN;
+ begin
+ if (l'length < 1 or r'length < 1 or
+ mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
+ return NASF;
+ end if;
+ l_abs := abs(l);
+ r_abs := abs(r);
+ dresult := "0" & sfixed(remainder (l => l_abs,
+ r => r_abs,
+ round_style => round_style));
+ if (to_s(dresult) = 0) then
+ dresult_not_zero := false;
+ else
+ dresult_not_zero := true;
+ end if;
+ if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
+ and dresult_not_zero then
+ result := resize (arg => r - dresult,
+ left_index => result'high,
+ right_index => result'low,
+ overflow_style => overflow_style,
+ round_style => round_style);
+ elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
+ result := resize (arg => -dresult,
+ left_index => result'high,
+ right_index => result'low,
+ overflow_style => overflow_style,
+ round_style => round_style);
+ elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
+ and dresult_not_zero then
+ result := resize (arg => dresult + r,
+ left_index => result'high,
+ right_index => result'low,
+ overflow_style => overflow_style,
+ round_style => round_style);
+ else
+ result := resize (arg => dresult,
+ left_index => result'high,
+ right_index => result'low,
+ overflow_style => overflow_style,
+ round_style => round_style);
+ end if;
+ return result;
+ end function modulo;
+
+ -- Procedure for those who need an "accumulator" function
+ procedure add_carry (
+ L, R : in ufixed;
+ c_in : in STD_ULOGIC;
+ result : out ufixed;
+ c_out : out STD_ULOGIC) is
+ constant left_index : INTEGER := maximum(l'high, r'high)+1;
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (left_index-right_index
+ downto 0);
+ variable result_slv : UNSIGNED (left_index-right_index
+ downto 0);
+ variable cx : UNSIGNED (0 downto 0); -- Carry in
+ begin
+ if (l'length < 1 or r'length < 1) then
+ result := NAUF;
+ c_out := '0';
+ else
+ cx (0) := c_in;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ result_slv := lslv + rslv + cx;
+ c_out := result_slv(left_index);
+ result := to_fixed(result_slv (left_index-right_index-1 downto 0),
+ left_index-1, right_index);
+ end if;
+ end procedure add_carry;
+
+ procedure add_carry (
+ L, R : in sfixed;
+ c_in : in STD_ULOGIC;
+ result : out sfixed;
+ c_out : out STD_ULOGIC) is
+ constant left_index : INTEGER := maximum(l'high, r'high)+1;
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (left_index-right_index
+ downto 0);
+ variable result_slv : SIGNED (left_index-right_index
+ downto 0);
+ variable cx : SIGNED (1 downto 0); -- Carry in
+ begin
+ if (l'length < 1 or r'length < 1) then
+ result := NASF;
+ c_out := '0';
+ else
+ cx (1) := '0';
+ cx (0) := c_in;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ result_slv := lslv + rslv + cx;
+ c_out := result_slv(left_index);
+ result := to_fixed(result_slv (left_index-right_index-1 downto 0),
+ left_index-1, right_index);
+ end if;
+ end procedure add_carry;
+
+ -- Scales the result by a power of 2. Width of input = width of output with
+ -- the decimal point moved.
+ function scalb (y : ufixed; N : integer) return ufixed is
+ variable result : ufixed (y'high+N downto y'low+N);
+ begin
+ if y'length < 1 then
+ return NAUF;
+ else
+ result := y;
+ return result;
+ end if;
+ end function scalb;
+
+ function scalb (y : ufixed; N : SIGNED) return ufixed is
+ begin
+ return scalb (y => y,
+ N => to_integer(N));
+ end function scalb;
+
+ function scalb (y : sfixed; N : integer) return sfixed is
+ variable result : sfixed (y'high+N downto y'low+N);
+ begin
+ if y'length < 1 then
+ return NASF;
+ else
+ result := y;
+ return result;
+ end if;
+ end function scalb;
+
+ function scalb (y : sfixed; N : SIGNED) return sfixed is
+ begin
+ return scalb (y => y,
+ N => to_integer(N));
+ end function scalb;
+
+ function Is_Negative (arg : sfixed) return BOOLEAN is
+ begin
+ if to_X01(arg(arg'high)) = '1' then
+ return true;
+ else
+ return false;
+ end if;
+ end function Is_Negative;
+
+ function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
+ begin
+ for_loop : for i in arg'low to arg'high loop
+ if arg(i) = y then
+ return i;
+ end if;
+ end loop;
+ return arg'high+1; -- return out of bounds 'high
+ end function find_lsb;
+
+ function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
+ begin
+ for_loop : for i in arg'high downto arg'low loop
+ if arg(i) = y then
+ return i;
+ end if;
+ end loop;
+ return arg'low-1; -- return out of bounds 'low
+ end function find_msb;
+
+ function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
+ begin
+ for_loop : for i in arg'low to arg'high loop
+ if arg(i) = y then
+ return i;
+ end if;
+ end loop;
+ return arg'high+1; -- return out of bounds 'high
+ end function find_lsb;
+
+ function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
+ begin
+ for_loop : for i in arg'high downto arg'low loop
+ if arg(i) = y then
+ return i;
+ end if;
+ end loop;
+ return arg'low-1; -- return out of bounds 'low
+ end function find_msb;
+
+ function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed is
+ variable argslv : UNSIGNED (arg'length-1 downto 0);
+ variable result : ufixed (arg'range);
+ begin
+ argslv := to_uns (arg);
+ argslv := argslv sll COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "sll";
+
+ function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed is
+ variable argslv : UNSIGNED (arg'length-1 downto 0);
+ variable result : ufixed (arg'range);
+ begin
+ argslv := to_uns (arg);
+ argslv := argslv srl COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "srl";
+
+ function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed is
+ variable argslv : UNSIGNED (arg'length-1 downto 0);
+ variable result : ufixed (arg'range);
+ begin
+ argslv := to_uns (arg);
+ argslv := argslv rol COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "rol";
+
+ function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed is
+ variable argslv : UNSIGNED (arg'length-1 downto 0);
+ variable result : ufixed (arg'range);
+ begin
+ argslv := to_uns (arg);
+ argslv := argslv ror COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "ror";
+
+ function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed is
+ variable argslv : UNSIGNED (arg'length-1 downto 0);
+ variable result : ufixed (arg'range);
+ begin
+ argslv := to_uns (arg);
+ -- Arithmetic shift on an unsigned is a logical shift
+ argslv := argslv sll COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "sla";
+
+ function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed is
+ variable argslv : UNSIGNED (arg'length-1 downto 0);
+ variable result : ufixed (arg'range);
+ begin
+ argslv := to_uns (arg);
+ -- Arithmetic shift on an unsigned is a logical shift
+ argslv := argslv srl COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "sra";
+
+ function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed is
+ variable argslv : SIGNED (arg'length-1 downto 0);
+ variable result : sfixed (arg'range);
+ begin
+ argslv := to_s (arg);
+ argslv := argslv sll COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "sll";
+
+ function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed is
+ variable argslv : SIGNED (arg'length-1 downto 0);
+ variable result : sfixed (arg'range);
+ begin
+ argslv := to_s (arg);
+ argslv := argslv srl COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "srl";
+
+ function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed is
+ variable argslv : SIGNED (arg'length-1 downto 0);
+ variable result : sfixed (arg'range);
+ begin
+ argslv := to_s (arg);
+ argslv := argslv rol COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "rol";
+
+ function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed is
+ variable argslv : SIGNED (arg'length-1 downto 0);
+ variable result : sfixed (arg'range);
+ begin
+ argslv := to_s (arg);
+ argslv := argslv ror COUNT;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "ror";
+
+ function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed is
+ variable argslv : SIGNED (arg'length-1 downto 0);
+ variable result : sfixed (arg'range);
+ begin
+ argslv := to_s (arg);
+ if COUNT > 0 then
+ -- Arithmetic shift left on a 2's complement number is a logic shift
+ argslv := argslv sll COUNT;
+ else
+ argslv := argslv sra -COUNT;
+ end if;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "sla";
+
+ function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed is
+ variable argslv : SIGNED (arg'length-1 downto 0);
+ variable result : sfixed (arg'range);
+ begin
+ argslv := to_s (arg);
+ if COUNT > 0 then
+ argslv := argslv sra COUNT;
+ else
+ -- Arithmetic shift left on a 2's complement number is a logic shift
+ argslv := argslv sll -COUNT;
+ end if;
+ result := to_fixed (argslv, result'high, result'low);
+ return result;
+ end function "sra";
+
+ -- Because some people want the older functions.
+ function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed is
+ begin
+ if (ARG'length < 1) then
+ return NAUF;
+ end if;
+ return ARG sla COUNT;
+ end function SHIFT_LEFT;
+ function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed is
+ begin
+ if (ARG'length < 1) then
+ return NAUF;
+ end if;
+ return ARG sra COUNT;
+ end function SHIFT_RIGHT;
+ function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed is
+ begin
+ if (ARG'length < 1) then
+ return NASF;
+ end if;
+ return ARG sla COUNT;
+ end function SHIFT_LEFT;
+ function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed is
+ begin
+ if (ARG'length < 1) then
+ return NASF;
+ end if;
+ return ARG sra COUNT;
+ end function SHIFT_RIGHT;
+
+ ----------------------------------------------------------------------------
+ -- logical functions
+ ----------------------------------------------------------------------------
+ function "not" (L : ufixed) return ufixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ RESULT := not to_slv(L);
+ return to_ufixed(RESULT, L'high, L'low);
+ end function "not";
+
+ function "and" (L, R : ufixed) return ufixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) and to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_ufixed(RESULT, L'high, L'low);
+ end function "and";
+
+ function "or" (L, R : ufixed) return ufixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) or to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_ufixed(RESULT, L'high, L'low);
+ end function "or";
+
+ function "nand" (L, R : ufixed) return ufixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) nand to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_ufixed(RESULT, L'high, L'low);
+ end function "nand";
+
+ function "nor" (L, R : ufixed) return ufixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) nor to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_ufixed(RESULT, L'high, L'low);
+ end function "nor";
+
+ function "xor" (L, R : ufixed) return ufixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) xor to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_ufixed(RESULT, L'high, L'low);
+ end function "xor";
+
+ function "xnor" (L, R : ufixed) return ufixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) xnor to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_ufixed(RESULT, L'high, L'low);
+ end function "xnor";
+
+ function "not" (L : sfixed) return sfixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ RESULT := not to_slv(L);
+ return to_sfixed(RESULT, L'high, L'low);
+ end function "not";
+
+ function "and" (L, R : sfixed) return sfixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) and to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_sfixed(RESULT, L'high, L'low);
+ end function "and";
+
+ function "or" (L, R : sfixed) return sfixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) or to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_sfixed(RESULT, L'high, L'low);
+ end function "or";
+
+ function "nand" (L, R : sfixed) return sfixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) nand to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_sfixed(RESULT, L'high, L'low);
+ end function "nand";
+
+ function "nor" (L, R : sfixed) return sfixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) nor to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_sfixed(RESULT, L'high, L'low);
+ end function "nor";
+
+ function "xor" (L, R : sfixed) return sfixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) xor to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_sfixed(RESULT, L'high, L'low);
+ end function "xor";
+
+ function "xnor" (L, R : sfixed) return sfixed is
+ variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ RESULT := to_slv(L) xnor to_slv(R);
+ else
+ report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
+ severity warning;
+ RESULT := (others => 'U');
+ end if;
+ return to_sfixed(RESULT, L'high, L'low);
+ end function "xnor";
+
+ -- Vector and std_ulogic functions, same as functions in numeric_std
+ function "and" (L : STD_ULOGIC; R : ufixed) return ufixed is
+ variable result : ufixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L and R(i);
+ end loop;
+ return result;
+ end function "and";
+
+ function "and" (L : ufixed; R : STD_ULOGIC) return ufixed is
+ variable result : ufixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) and R;
+ end loop;
+ return result;
+ end function "and";
+
+ function "or" (L : STD_ULOGIC; R : ufixed) return ufixed is
+ variable result : ufixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L or R(i);
+ end loop;
+ return result;
+ end function "or";
+
+ function "or" (L : ufixed; R : STD_ULOGIC) return ufixed is
+ variable result : ufixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) or R;
+ end loop;
+ return result;
+ end function "or";
+
+ function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed is
+ variable result : ufixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L nand R(i);
+ end loop;
+ return result;
+ end function "nand";
+
+ function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed is
+ variable result : ufixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) nand R;
+ end loop;
+ return result;
+ end function "nand";
+
+ function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed is
+ variable result : ufixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L nor R(i);
+ end loop;
+ return result;
+ end function "nor";
+
+ function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed is
+ variable result : ufixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) nor R;
+ end loop;
+ return result;
+ end function "nor";
+
+ function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed is
+ variable result : ufixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L xor R(i);
+ end loop;
+ return result;
+ end function "xor";
+
+ function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed is
+ variable result : ufixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) xor R;
+ end loop;
+ return result;
+ end function "xor";
+
+ function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed is
+ variable result : ufixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L xnor R(i);
+ end loop;
+ return result;
+ end function "xnor";
+
+ function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed is
+ variable result : ufixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) xnor R;
+ end loop;
+ return result;
+ end function "xnor";
+
+ function "and" (L : STD_ULOGIC; R : sfixed) return sfixed is
+ variable result : sfixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L and R(i);
+ end loop;
+ return result;
+ end function "and";
+
+ function "and" (L : sfixed; R : STD_ULOGIC) return sfixed is
+ variable result : sfixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) and R;
+ end loop;
+ return result;
+ end function "and";
+
+ function "or" (L : STD_ULOGIC; R : sfixed) return sfixed is
+ variable result : sfixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L or R(i);
+ end loop;
+ return result;
+ end function "or";
+
+ function "or" (L : sfixed; R : STD_ULOGIC) return sfixed is
+ variable result : sfixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) or R;
+ end loop;
+ return result;
+ end function "or";
+
+ function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed is
+ variable result : sfixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L nand R(i);
+ end loop;
+ return result;
+ end function "nand";
+
+ function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed is
+ variable result : sfixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) nand R;
+ end loop;
+ return result;
+ end function "nand";
+
+ function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed is
+ variable result : sfixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L nor R(i);
+ end loop;
+ return result;
+ end function "nor";
+
+ function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed is
+ variable result : sfixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) nor R;
+ end loop;
+ return result;
+ end function "nor";
+
+ function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed is
+ variable result : sfixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L xor R(i);
+ end loop;
+ return result;
+ end function "xor";
+
+ function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed is
+ variable result : sfixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) xor R;
+ end loop;
+ return result;
+ end function "xor";
+
+ function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed is
+ variable result : sfixed (R'range);
+ begin
+ for i in result'range loop
+ result(i) := L xnor R(i);
+ end loop;
+ return result;
+ end function "xnor";
+
+ function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed is
+ variable result : sfixed (L'range);
+ begin
+ for i in result'range loop
+ result(i) := L(i) xnor R;
+ end loop;
+ return result;
+ end function "xnor";
+
+ -- Reduction operators, same as numeric_std functions
+ -- %%% remove 12 functions (old syntax)
+ function and_reduce(arg : ufixed) return STD_ULOGIC is
+ begin
+ return and_reducex (to_slv(arg));
+ end function and_reduce;
+
+ function nand_reduce(arg : ufixed) return STD_ULOGIC is
+ begin
+ return not and_reducex (to_slv(arg));
+ end function nand_reduce;
+
+ function or_reduce(arg : ufixed) return STD_ULOGIC is
+ begin
+ return or_reducex (to_slv(arg));
+ end function or_reduce;
+
+ function nor_reduce(arg : ufixed) return STD_ULOGIC is
+ begin
+ return not or_reducex (to_slv(arg));
+ end function nor_reduce;
+
+ function xor_reduce(arg : ufixed) return STD_ULOGIC is
+ begin
+ return xor_reducex (to_slv(arg));
+ end function xor_reduce;
+
+ function xnor_reduce(arg : ufixed) return STD_ULOGIC is
+ begin
+ return not xor_reducex (to_slv(arg));
+ end function xnor_reduce;
+
+ function and_reduce(arg : sfixed) return STD_ULOGIC is
+ begin
+ return and_reducex (to_slv(arg));
+ end function and_reduce;
+
+ function nand_reduce(arg : sfixed) return STD_ULOGIC is
+ begin
+ return not and_reducex (to_slv(arg));
+ end function nand_reduce;
+
+ function or_reduce(arg : sfixed) return STD_ULOGIC is
+ begin
+ return or_reducex (to_slv(arg));
+ end function or_reduce;
+
+ function nor_reduce(arg : sfixed) return STD_ULOGIC is
+ begin
+ return not or_reducex (to_slv(arg));
+ end function nor_reduce;
+
+ function xor_reduce(arg : sfixed) return STD_ULOGIC is
+ begin
+ return xor_reducex (to_slv(arg));
+ end function xor_reduce;
+
+ function xnor_reduce(arg : sfixed) return STD_ULOGIC is
+ begin
+ return not xor_reducex (to_slv(arg));
+ end function xnor_reduce;
+ -- %%% Uncomment the following 12 functions (new syntax)
+ -- function "and" ( arg : ufixed ) RETURN std_ulogic is
+ -- begin
+ -- return and to_slv(arg);
+ -- end function "and";
+ -- function "nand" ( arg : ufixed ) RETURN std_ulogic is
+ -- begin
+ -- return nand to_slv(arg);
+ -- end function "nand";;
+ -- function "or" ( arg : ufixed ) RETURN std_ulogic is
+ -- begin
+ -- return or to_slv(arg);
+ -- end function "or";
+ -- function "nor" ( arg : ufixed ) RETURN std_ulogic is
+ -- begin
+ -- return nor to_slv(arg);
+ -- end function "nor";
+ -- function "xor" ( arg : ufixed ) RETURN std_ulogic is
+ -- begin
+ -- return xor to_slv(arg);
+ -- end function "xor";
+ -- function "xnor" ( arg : ufixed ) RETURN std_ulogic is
+ -- begin
+ -- return xnor to_slv(arg);
+ -- end function "xnor";
+ -- function "and" ( arg : sfixed ) RETURN std_ulogic is
+ -- begin
+ -- return and to_slv(arg);
+ -- end function "and";;
+ -- function "nand" ( arg : sfixed ) RETURN std_ulogic is
+ -- begin
+ -- return nand to_slv(arg);
+ -- end function "nand";;
+ -- function "or" ( arg : sfixed ) RETURN std_ulogic is
+ -- begin
+ -- return or to_slv(arg);
+ -- end function "or";
+ -- function "nor" ( arg : sfixed ) RETURN std_ulogic is
+ -- begin
+ -- return nor to_slv(arg);
+ -- end function "nor";
+ -- function "xor" ( arg : sfixed ) RETURN std_ulogic is
+ -- begin
+ -- return xor to_slv(arg);
+ -- end function "xor";
+ -- function "xnor" ( arg : sfixed ) RETURN std_ulogic is
+ -- begin
+ -- return xnor to_slv(arg);
+ -- end function "xnor";
+
+ -- %%% Replace with the following (new syntax)
+-- function "?=" (L, R : ufixed) return STD_ULOGIC is
+ function \?=\ (L, R : ufixed) return STD_ULOGIC is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable result, result1 : STD_ULOGIC; -- result
+ begin -- ?=
+ if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
+ severity warning;
+ return 'X';
+ else
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ result := '1';
+ for i in lresize'reverse_range loop
+ result1 := \?=\(lresize(i), rresize(i));
+ if result1 = 'U' then
+ return 'U';
+ elsif result1 = 'X' or result = 'X' then
+ result := 'X';
+ else
+ result := result and result1;
+ end if;
+ end loop;
+ return result;
+ end if;
+ end function \?=\;
+-- end function "?=";
+
+-- function "?/=" (L, R : ufixed) return STD_ULOGIC is
+ function \?/=\ (L, R : ufixed) return STD_ULOGIC is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable result, result1 : STD_ULOGIC; -- result
+ begin -- ?/=
+ if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
+ severity warning;
+ return 'X';
+ else
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ result := '0';
+ for i in lresize'reverse_range loop
+ result1 := \?/=\ (lresize(i), rresize(i));
+ if result1 = 'U' then
+ return 'U';
+ elsif result1 = 'X' or result = 'X' then
+ result := 'X';
+ else
+ result := result or result1;
+ end if;
+ end loop;
+ return result;
+ end if;
+ end function \?/=\;
+-- end function "?/=";
+
+-- function "?>" (L, R : ufixed) return STD_ULOGIC is
+ function \?>\ (L, R : ufixed) return STD_ULOGIC is
+ begin -- ?>
+ if ((l'length < 1) or (r'length < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
+ severity warning;
+ return 'X';
+ elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
+ report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
+ severity error;
+ return 'X';
+ else
+ if is_x(l) or is_x(r) then
+ return 'X';
+ elsif l > r then
+ return '1';
+ else
+ return '0';
+ end if;
+ end if;
+ end function \?>\;
+-- end function "?>";
+
+-- function "?>=" (L, R : ufixed) return STD_ULOGIC is
+ function \?>=\ (L, R : ufixed) return STD_ULOGIC is
+ begin -- ?>=
+ if ((l'length < 1) or (r'length < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
+ severity warning;
+ return 'X';
+ elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
+ report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
+ severity error;
+ return 'X';
+ else
+ if is_x(l) or is_x(r) then
+ return 'X';
+ elsif l >= r then
+ return '1';
+ else
+ return '0';
+ end if;
+ end if;
+ end function \?>=\;
+-- end function "?>=";
+
+-- function "?<" (L, R : ufixed) return STD_ULOGIC is
+ function \?<\ (L, R : ufixed) return STD_ULOGIC is
+ begin -- ?<
+ if ((l'length < 1) or (r'length < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
+ severity warning;
+ return 'X';
+ elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
+ report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
+ severity error;
+ return 'X';
+ else
+ if is_x(l) or is_x(r) then
+ return 'X';
+ elsif l < r then
+ return '1';
+ else
+ return '0';
+ end if;
+ end if;
+ end function \?<\;
+-- end function "?<";
+
+-- function "?<=" (L, R : ufixed) return STD_ULOGIC is
+ function \?<=\ (L, R : ufixed) return STD_ULOGIC is
+ begin -- ?<=
+ if ((l'length < 1) or (r'length < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
+ severity warning;
+ return 'X';
+ elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
+ report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
+ severity error;
+ return 'X';
+ else
+ if is_x(l) or is_x(r) then
+ return 'X';
+ elsif l <= r then
+ return '1';
+ else
+ return '0';
+ end if;
+ end if;
+ end function \?<=\;
+-- end function "?<=";
+
+ -- function "?=" (L, R : sfixed) return STD_ULOGIC is
+ function \?=\ (L, R : sfixed) return STD_ULOGIC is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable result, result1 : STD_ULOGIC; -- result
+ begin -- ?=
+ if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
+ severity warning;
+ return 'X';
+ else
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ result := '1';
+ for i in lresize'reverse_range loop
+ result1 := \?=\ (lresize(i), rresize(i));
+ if result1 = 'U' then
+ return 'U';
+ elsif result1 = 'X' or result = 'X' then
+ result := 'X';
+ else
+ result := result and result1;
+ end if;
+ end loop;
+ return result;
+ end if;
+ end function \?=\;
+-- end function "?=";
+
+-- function "?/=" (L, R : sfixed) return STD_ULOGIC is
+ function \?/=\ (L, R : sfixed) return STD_ULOGIC is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable result, result1 : STD_ULOGIC; -- result
+ begin -- ?/=
+ if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
+ severity warning;
+ return 'X';
+ else
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ result := '0';
+ for i in lresize'reverse_range loop
+ result1 := \?/=\ (lresize(i), rresize(i));
+ if result1 = 'U' then
+ return 'U';
+ elsif result1 = 'X' or result = 'X' then
+ result := 'X';
+ else
+ result := result or result1;
+ end if;
+ end loop;
+ return result;
+ end if;
+ end function \?/=\;
+-- end function "?/=";
+
+-- function "?>" (L, R : sfixed) return STD_ULOGIC is
+ function \?>\ (L, R : sfixed) return STD_ULOGIC is
+ begin -- ?>
+ if ((l'length < 1) or (r'length < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
+ severity warning;
+ return 'X';
+ elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
+ report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
+ severity error;
+ return 'X';
+ else
+ if is_x(l) or is_x(r) then
+ return 'X';
+ elsif l > r then
+ return '1';
+ else
+ return '0';
+ end if;
+ end if;
+ end function \?>\;
+-- end function "?>";
+
+-- function "?>=" (L, R : sfixed) return STD_ULOGIC is
+ function \?>=\ (L, R : sfixed) return STD_ULOGIC is
+ begin -- ?>=
+ if ((l'length < 1) or (r'length < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
+ severity warning;
+ return 'X';
+ elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
+ report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
+ severity error;
+ return 'X';
+ else
+ if is_x(l) or is_x(r) then
+ return 'X';
+ elsif l >= r then
+ return '1';
+ else
+ return '0';
+ end if;
+ end if;
+ end function \?>=\;
+-- end function "?>=";
+
+-- function "?<" (L, R : sfixed) return STD_ULOGIC is
+ function \?<\ (L, R : sfixed) return STD_ULOGIC is
+ begin -- ?<
+ if ((l'length < 1) or (r'length < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
+ severity warning;
+ return 'X';
+ elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
+ report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
+ severity error;
+ return 'X';
+ else
+ if is_x(l) or is_x(r) then
+ return 'X';
+ elsif l < r then
+ return '1';
+ else
+ return '0';
+ end if;
+ end if;
+ end function \?<\;
+-- end function "?<";
+
+-- function "?<=" (L, R : sfixed) return STD_ULOGIC is
+ function \?<=\ (L, R : sfixed) return STD_ULOGIC is
+ begin -- ?<=
+ if ((l'length < 1) or (r'length < 1)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
+ severity warning;
+ return 'X';
+ elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
+ report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
+ severity error;
+ return 'X';
+ else
+ if is_x(l) or is_x(r) then
+ return 'X';
+ elsif l <= r then
+ return '1';
+ else
+ return '0';
+ end if;
+ end if;
+ end function \?<=\;
+-- end function "?<=";
+
+ -- %%% end replace
+ -- Match function, similar to "std_match" from numeric_std
+ function std_match (L, R : ufixed) return BOOLEAN is
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ return std_match(to_slv(L), to_slv(R));
+ else
+ report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ end function std_match;
+
+ function std_match (L, R : sfixed) return BOOLEAN is
+ begin
+ if (L'high = R'high and L'low = R'low) then
+ return std_match(to_slv(L), to_slv(R));
+ else
+ report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ end function std_match;
+ --%%% end remove
+
+ -- compare functions
+ function "=" (
+ l, r : ufixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ return lslv = rslv;
+ end function "=";
+
+ function "=" (
+ l, r : sfixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ return lslv = rslv;
+ end function "=";
+
+ function "/=" (
+ l, r : ufixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
+ severity warning;
+ return true;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
+ severity warning;
+ return true;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ return lslv /= rslv;
+ end function "/=";
+
+ function "/=" (
+ l, r : sfixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
+ severity warning;
+ return true;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
+ severity warning;
+ return true;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ return lslv /= rslv;
+ end function "/=";
+
+ function ">" (
+ l, r : ufixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ return lslv > rslv;
+ end function ">";
+
+ function ">" (
+ l, r : sfixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ return lslv > rslv;
+ end function ">";
+
+ function "<" (
+ l, r : ufixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ return lslv < rslv;
+ end function "<";
+
+ function "<" (
+ l, r : sfixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ return lslv < rslv;
+ end function "<";
+
+ function ">=" (
+ l, r : ufixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ return lslv >= rslv;
+ end function ">=";
+
+ function ">=" (
+ l, r : sfixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ return lslv >= rslv;
+ end function ">=";
+
+ function "<=" (
+ l, r : ufixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : ufixed (left_index downto right_index);
+ variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_uns (lresize);
+ rslv := to_uns (rresize);
+ return lslv <= rslv;
+ end function "<=";
+
+ function "<=" (
+ l, r : sfixed) -- fixed point input
+ return BOOLEAN is
+ constant left_index : INTEGER := maximum(l'high, r'high);
+ constant right_index : INTEGER := mins(l'low, r'low);
+ variable lresize, rresize : sfixed (left_index downto right_index);
+ variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
+ begin
+ if (l'length < 1 or r'length < 1) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
+ severity warning;
+ return false;
+ elsif (Is_X(l) or Is_X(r)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
+ severity warning;
+ return false;
+ end if;
+ lresize := resize (l, left_index, right_index);
+ rresize := resize (r, left_index, right_index);
+ lslv := to_s (lresize);
+ rslv := to_s (rresize);
+ return lslv <= rslv;
+ end function "<=";
+
+ -- overloads of the default maximum and minimum functions
+ function maximum (l, r : ufixed) return ufixed is
+ begin
+ if l > r then return l;
+ else return r;
+ end if;
+ end function maximum;
+
+ function maximum (l, r : sfixed) return sfixed is
+ begin
+ if l > r then return l;
+ else return r;
+ end if;
+ end function maximum;
+
+ function minimum (l, r : ufixed) return ufixed is
+ begin
+ if l > r then return r;
+ else return l;
+ end if;
+ end function minimum;
+
+ function minimum (l, r : sfixed) return sfixed is
+ begin
+ if l > r then return r;
+ else return l;
+ end if;
+ end function minimum;
+
+ function to_ufixed (
+ arg : NATURAL; -- integer
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER := 0; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
+ return ufixed is
+ variable argx : INTEGER;
+ constant fw : INTEGER := mine (right_index, right_index); -- catch literals
+ variable result : ufixed (left_index downto fw) := (others => '0');
+ variable sresult : UNSIGNED (left_index downto 0); -- integer portion
+ variable bound : NATURAL; -- find the numerical bounds
+ begin
+ if (left_index < fw) then
+ return NAUF;
+ end if;
+ if left_index >= 0 then
+ if (left_index < 30) then
+ bound := 2**(left_index+1);
+ else
+ bound := INTEGER'high;
+ end if;
+ end if;
+ if (arg /= 0) then
+ if arg >= bound or left_index < 0 then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.TO_UFIXED(NATURAL): vector truncated"
+ severity warning;
+ if (overflow_style = fixed_wrap) then -- wrap
+ if bound = 0 then
+ argx := 0;
+ else
+ argx := arg mod bound;
+ end if;
+ else -- saturate
+ return saturate (result'high, result'low);
+ end if;
+ else
+ argx := arg;
+ end if;
+ else
+ return result; -- return zero
+ end if;
+ sresult := to_unsigned (argx, sresult'high+1);
+ result := resize (arg => ufixed (sresult),
+ left_index => left_index,
+ right_index => right_index,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : INTEGER; -- integer
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER := 0; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
+ return sfixed is
+ variable argx : INTEGER;
+ constant fw : INTEGER := mine (right_index, right_index); -- catch literals
+ variable result : sfixed (left_index downto fw) := (others => '0');
+ variable sresult : SIGNED (left_index+1 downto 0); -- integer portion
+ variable bound : NATURAL := 0;
+ begin
+ if (left_index < fw) then -- null range
+ return NASF;
+ end if;
+ if left_index >= 0 then
+ if (left_index < 30) then
+ bound := 2**(left_index);
+ else
+ bound := INTEGER'high;
+ end if;
+ end if;
+ if (arg /= 0) then
+ if (arg >= bound or arg < -bound or left_index < 0) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.TO_SFIXED(INTEGER): vector truncated"
+ severity warning;
+ if overflow_style = fixed_wrap then -- wrap
+ if bound = 0 then -- negative integer_range trap
+ argx := 0;
+ else -- shift off the top bits
+ argx := arg rem (bound*2);
+ end if;
+ else -- saturate
+ if arg < 0 then
+ result := not saturate (result'high, result'low); -- underflow
+ else
+ result := saturate (result'high, result'low); -- overflow
+ end if;
+ return result;
+ end if;
+ else
+ argx := arg;
+ end if;
+ else
+ return result; -- return zero
+ end if;
+ sresult := to_signed (argx, sresult'length);
+ result := resize (arg => sfixed (sresult),
+ left_index => left_index,
+ right_index => right_index,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end function to_sfixed;
+
+ function to_ufixed (
+ arg : REAL; -- real
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
+ constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
+ return ufixed is
+ constant fw : INTEGER := mine (right_index, right_index); -- catch literals
+ variable result : ufixed (left_index downto fw) := (others => '0');
+ variable Xresult : ufixed (left_index downto fw-guard_bits) := (others => '0');
+ variable presult : REAL;
+ variable overflow_needed : BOOLEAN;
+ begin
+ -- If negative or null range, return.
+ if (left_index < fw) then
+ return NAUF;
+ end if;
+ if (arg < 0.0) then
+ report "FIXED_GENERIC_PKG.TO_UFIXED: Negative argument passed "
+ & REAL'image(arg) severity error;
+ return result;
+ end if;
+ presult := arg;
+ if presult >= (2.0**(left_index+1)) then
+ assert NO_WARNING report "FIXED_GENERIC_PKG.TO_UFIXED(REAL): vector truncated"
+ severity warning;
+ overflow_needed := (overflow_style = fixed_saturate);
+ if overflow_style = fixed_wrap then
+ presult := presult mod (2.0**(left_index+1)); -- wrap
+ else
+ return saturate (result'high, result'low);
+ end if;
+ end if;
+ for i in Xresult'range loop
+ if presult >= 2.0**i then
+ Xresult(i) := '1';
+ presult := presult - 2.0**i;
+ else
+ Xresult(i) := '0';
+ end if;
+ end loop;
+ if guard_bits > 0 and round_style = fixed_round then
+ result := round_fixed (arg => Xresult (left_index
+ downto right_index),
+ remainder => Xresult (right_index-1 downto
+ right_index-guard_bits),
+ overflow_style => overflow_style);
+ else
+ result := Xresult (result'range);
+ end if;
+ return result;
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : REAL; -- real
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
+ constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
+ return sfixed is
+ constant fw : INTEGER := mine (right_index, right_index); -- catch literals
+ variable result : sfixed (left_index downto fw) := (others => '0');
+ variable Xresult : sfixed (left_index+1 downto fw-guard_bits) := (others => '0');
+ variable presult : REAL;
+ begin
+ if (left_index < fw) then -- null range
+ return NASF;
+ end if;
+ if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
+ assert NO_WARNING report "FIXED_GENERIC_PKG.TO_SFIXED(REAL): vector truncated"
+ severity warning;
+ if overflow_style = fixed_saturate then
+ if arg < 0.0 then -- saturate
+ result := not saturate (result'high, result'low); -- underflow
+ else
+ result := saturate (result'high, result'low); -- overflow
+ end if;
+ return result;
+ else
+ presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
+ end if;
+ else
+ presult := abs(arg);
+ end if;
+ for i in Xresult'range loop
+ if presult >= 2.0**i then
+ Xresult(i) := '1';
+ presult := presult - 2.0**i;
+ else
+ Xresult(i) := '0';
+ end if;
+ end loop;
+ if arg < 0.0 then
+ Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
+ end if;
+ if guard_bits > 0 and round_style then
+ result := round_fixed (arg => Xresult (left_index
+ downto right_index),
+ remainder => Xresult (right_index-1 downto
+ right_index-guard_bits),
+ overflow_style => overflow_style);
+ else
+ result := Xresult (result'range);
+ end if;
+ return result;
+ end function to_sfixed;
+
+ function to_ufixed (
+ arg : UNSIGNED; -- unsigned
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER := 0; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
+ return ufixed is
+ constant ARG_LEFT : INTEGER := ARG'length-1;
+ alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
+ constant fw : INTEGER := mine (right_index, right_index); -- catch literals
+ variable result : ufixed (left_index downto fw);
+ begin
+ if arg'length < 1 or (left_index < fw) then
+ return NAUF;
+ end if;
+ result := resize (arg => ufixed (XARG),
+ left_index => left_index,
+ right_index => right_index,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end function to_ufixed;
+
+ -- casted version
+ function to_ufixed (
+ arg : UNSIGNED) -- unsigned
+ return ufixed is
+ constant ARG_LEFT : INTEGER := ARG'length-1;
+ alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
+ begin
+ if arg'length < 1 then
+ return NAUF;
+ end if;
+ return ufixed(xarg);
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : SIGNED; -- signed
+ constant left_index : INTEGER; -- size of integer portion
+ constant right_index : INTEGER := 0; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
+ return sfixed is
+ constant ARG_LEFT : INTEGER := ARG'length-1;
+ alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
+ constant fw : INTEGER := mine (right_index, right_index); -- catch literals
+ variable result : sfixed (left_index downto fw);
+ begin
+ if arg'length < 1 or (left_index < fw) then
+ return NASF;
+ end if;
+ result := resize (arg => sfixed (XARG),
+ left_index => left_index,
+ right_index => right_index,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end function to_sfixed;
+
+ -- casted version
+ function to_sfixed (
+ arg : SIGNED) -- signed
+ return sfixed is
+ constant ARG_LEFT : INTEGER := ARG'length-1;
+ alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
+ begin
+ if arg'length < 1 then
+ return NASF;
+ end if;
+ return sfixed(xarg);
+ end function to_sfixed;
+
+ function add_sign (arg : ufixed) return sfixed is
+ variable result : sfixed (arg'high+1 downto arg'low);
+ begin
+ if arg'length < 1 then
+ return NASF;
+ end if;
+ result (arg'high downto arg'low) := sfixed(cleanvec(arg));
+ result (arg'high+1) := '0';
+ return result;
+ end function add_sign;
+
+ -- Because of the farily complicated sizing rules in the fixed point
+ -- packages these functions are provided to compute the result ranges
+ -- Example:
+ -- signal uf1 : ufixed (3 downto -3);
+ -- signal uf2 : ufixed (4 downto -2);
+ -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
+ -- ufixed_low (3, -3, '*', 4, -2));
+ -- uf1multuf2 <= uf1 * uf2;
+ -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
+ -- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
+ function ufixed_high (left_index, right_index : INTEGER;
+ operation : CHARACTER := 'X';
+ left_index2, right_index2 : INTEGER := 0)
+ return INTEGER is
+ begin
+ case operation is
+ when '+'| '-' => return maximum (left_index, left_index2) + 1;
+ when '*' => return left_index + left_index2 + 1;
+ when '/' => return left_index - right_index2;
+ when '1' => return -right_index; -- reciprocal
+ when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
+ when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
+ when others => return left_index; -- For abs and default
+ end case;
+ end function ufixed_high;
+
+ function ufixed_low (left_index, right_index : INTEGER;
+ operation : CHARACTER := 'X';
+ left_index2, right_index2 : INTEGER := 0)
+ return INTEGER is
+ begin
+ case operation is
+ when '+'| '-' => return mins (right_index, right_index2);
+ when '*' => return right_index + right_index2;
+ when '/' => return right_index - left_index2 - 1;
+ when '1' => return -left_index - 1; -- reciprocal
+ when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
+ when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
+ when others => return right_index; -- for abs and default
+ end case;
+ end function ufixed_low;
+
+ function sfixed_high (left_index, right_index : INTEGER;
+ operation : CHARACTER := 'X';
+ left_index2, right_index2 : INTEGER := 0)
+ return INTEGER is
+ begin
+ case operation is
+ when '+'| '-' => return maximum (left_index, left_index2) + 1;
+ when '*' => return left_index + left_index2 + 1;
+ when '/' => return left_index - right_index2 + 1;
+ when '1' => return -right_index + 1; -- reciprocal
+ when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
+ when 'M'|'m' => return left_index2; -- "mod"
+ when 'A'|'a' => return left_index + 1; -- "abs"
+ when 'N'|'n' => return left_index + 1; -- -sfixed
+ when others => return left_index;
+ end case;
+ end function sfixed_high;
+
+ function sfixed_low (left_index, right_index : INTEGER;
+ operation : CHARACTER := 'X';
+ left_index2, right_index2 : INTEGER := 0)
+ return INTEGER is
+ begin
+ case operation is
+ when '+'| '-' => return mins (right_index, right_index2);
+ when '*' => return right_index + right_index2;
+ when '/' => return right_index - left_index2;
+ when '1' => return -left_index; -- reciprocal
+ when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
+ when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
+ when others => return right_index; -- default for abs, neg and default
+ end case;
+ end function sfixed_low;
+ -- Same as above, but using the "size_res" input only for their ranges:
+ -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
+ -- ufixed_low (uf1, '*', uf2));
+ -- uf1multuf2 <= uf1 * uf2;
+ function ufixed_high (size_res : ufixed;
+ operation : CHARACTER := 'X';
+ size_res2 : ufixed)
+ return INTEGER is
+ begin
+ return ufixed_high (left_index => size_res'high,
+ right_index => size_res'low,
+ operation => operation,
+ left_index2 => size_res2'high,
+ right_index2 => size_res2'low);
+ end function ufixed_high;
+ function ufixed_low (size_res : ufixed;
+ operation : CHARACTER := 'X';
+ size_res2 : ufixed)
+ return INTEGER is
+ begin
+ return ufixed_low (left_index => size_res'high,
+ right_index => size_res'low,
+ operation => operation,
+ left_index2 => size_res2'high,
+ right_index2 => size_res2'low);
+ end function ufixed_low;
+ function sfixed_high (size_res : sfixed;
+ operation : CHARACTER := 'X';
+ size_res2 : sfixed)
+ return INTEGER is
+ begin
+ return sfixed_high (left_index => size_res'high,
+ right_index => size_res'low,
+ operation => operation,
+ left_index2 => size_res2'high,
+ right_index2 => size_res2'low);
+ end function sfixed_high;
+ function sfixed_low (size_res : sfixed;
+ operation : CHARACTER := 'X';
+ size_res2 : sfixed)
+ return INTEGER is
+ begin
+ return sfixed_low (left_index => size_res'high,
+ right_index => size_res'low,
+ operation => operation,
+ left_index2 => size_res2'high,
+ right_index2 => size_res2'low);
+ end function sfixed_low;
+
+ -- purpose: returns a saturated number
+ function saturate (
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed is
+ constant sat : ufixed (left_index downto right_index) := (others => '1');
+ begin
+ return sat;
+ end function saturate;
+
+ -- purpose: returns a saturated number
+ function saturate (
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed is
+ variable sat : sfixed (left_index downto right_index) := (others => '1');
+ begin
+ -- saturate positive, to saturate negative, just do "not saturate()"
+ sat (left_index) := '0';
+ return sat;
+ end function saturate;
+
+ function saturate (
+ size_res : ufixed) -- only the size of this is used
+ return ufixed is
+ begin
+ return saturate (size_res'high, size_res'low);
+ end function saturate;
+
+ function saturate (
+ size_res : sfixed) -- only the size of this is used
+ return sfixed is
+ begin
+ return saturate (size_res'high, size_res'low);
+ end function saturate;
+
+ -- As a concession to those who use a graphical DSP environment,
+ -- these functions take parameters in those tools format and create
+ -- fixed point numbers. These functions are designed to convert from
+ -- a std_logic_vector to the VHDL fixed point format using the conventions
+ -- of these packages. In a pure VHDL environment you should use the
+ -- "to_ufixed" and "to_sfixed" routines.
+ -- Unsigned fixed point
+ function to_UFix (
+ arg : STD_LOGIC_VECTOR;
+ width : NATURAL; -- width of vector
+ fraction : NATURAL) -- width of fraction
+ return ufixed is
+ variable result : ufixed (width-fraction-1 downto -fraction);
+ begin
+ if (arg'length /= result'length) then
+ report "FIXED_GENERIC_PKG.TO_UFIX (STD_LOGIC_VECTOR) "
+ & "Vector lengths do not match. Input length is "
+ & INTEGER'image(arg'length) & " and output will be "
+ & INTEGER'image(result'length) & " wide."
+ severity error;
+ return NAUF;
+ else
+ result := to_ufixed (arg, result'high, result'low);
+ return result;
+ end if;
+ end function to_UFix;
+
+ -- signed fixed point
+ function to_SFix (
+ arg : STD_LOGIC_VECTOR;
+ width : NATURAL; -- width of vector
+ fraction : NATURAL) -- width of fraction
+ return sfixed is
+ variable result : sfixed (width-fraction-1 downto -fraction);
+ begin
+ if (arg'length /= result'length) then
+ report "FIXED_GENERIC_PKG.TO_SFIX (STD_LOGIC_VECTOR) "
+ & "Vector lengths do not match. Input length is "
+ & INTEGER'image(arg'length) & " and output will be "
+ & INTEGER'image(result'length) & " wide."
+ severity error;
+ return NASF;
+ else
+ result := to_sfixed (arg, result'high, result'low);
+ return result;
+ end if;
+ end function to_SFix;
+
+ -- finding the bounds of a number. These functions can be used like this:
+ -- signal xxx : ufixed (7 downto -3);
+ -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
+ -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
+ -- downto UFix_low(11, 3, "+", 11, 3));
+ -- Where "11" is the width of xxx (xxx'length),
+ -- and 3 is the lower bound (abs (xxx'low))
+ -- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
+ function ufix_high (
+ width, fraction : NATURAL;
+ operation : CHARACTER := 'X';
+ width2, fraction2 : NATURAL := 0)
+ return INTEGER is
+ begin
+ return ufixed_high (left_index => width - 1 - fraction,
+ right_index => -fraction,
+ operation => operation,
+ left_index2 => width2 - 1 - fraction2,
+ right_index2 => -fraction2);
+ end function ufix_high;
+ function ufix_low (
+ width, fraction : NATURAL;
+ operation : CHARACTER := 'X';
+ width2, fraction2 : NATURAL := 0)
+ return INTEGER is
+ begin
+ return ufixed_low (left_index => width - 1 - fraction,
+ right_index => -fraction,
+ operation => operation,
+ left_index2 => width2 - 1 - fraction2,
+ right_index2 => -fraction2);
+ end function ufix_low;
+ function sfix_high (
+ width, fraction : NATURAL;
+ operation : CHARACTER := 'X';
+ width2, fraction2 : NATURAL := 0)
+ return INTEGER is
+ begin
+ return sfixed_high (left_index => width - fraction,
+ right_index => -fraction,
+ operation => operation,
+ left_index2 => width2 - fraction2,
+ right_index2 => -fraction2);
+ end function sfix_high;
+ function sfix_low (
+ width, fraction : NATURAL;
+ operation : CHARACTER := 'X';
+ width2, fraction2 : NATURAL := 0)
+ return INTEGER is
+ begin
+ return sfixed_low (left_index => width - fraction,
+ right_index => -fraction,
+ operation => operation,
+ left_index2 => width2 - fraction2,
+ right_index2 => -fraction2);
+ end function sfix_low;
+
+ function to_unsigned (
+ arg : ufixed; -- ufixed point input
+ constant size : NATURAL; -- length of output
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return UNSIGNED is
+ begin
+ return to_uns(resize (arg => arg,
+ left_index => size-1,
+ right_index => 0,
+ round_style => round_style,
+ overflow_style => overflow_style));
+ end function to_unsigned;
+
+ function to_unsigned (
+ arg : ufixed; -- ufixed point input
+ size_res : UNSIGNED; -- length of output
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return UNSIGNED is
+ begin
+ return to_unsigned (arg => arg,
+ size => size_res'length,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ end function to_unsigned;
+
+ function to_signed (
+ arg : sfixed; -- ufixed point input
+ constant size : NATURAL; -- length of output
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return SIGNED is
+ begin
+ return to_s(resize (arg => arg,
+ left_index => size-1,
+ right_index => 0,
+ round_style => round_style,
+ overflow_style => overflow_style));
+ end function to_signed;
+
+ function to_signed (
+ arg : sfixed; -- ufixed point input
+ size_res : SIGNED; -- used for length of output
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return SIGNED is
+ begin
+ return to_signed (arg => arg,
+ size => size_res'length,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ end function to_signed;
+
+ function to_real (
+ arg : ufixed) -- ufixed point input
+ return REAL is
+ constant left_index : INTEGER := arg'high;
+ constant right_index : INTEGER := arg'low;
+ variable result : REAL; -- result
+ variable arg_int : ufixed (left_index downto right_index);
+ begin
+ if (arg'length < 1) then
+ return 0.0;
+ end if;
+ arg_int := cleanvec(arg);
+ if (Is_X(arg_int)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
+ severity warning;
+ return 0.0;
+ end if;
+ result := 0.0;
+ for i in arg_int'range loop
+ if (arg_int(i) = '1') then
+ result := result + (2.0**i);
+ end if;
+ end loop;
+ return result;
+ end function to_real;
+
+ function to_real (
+ arg : sfixed) -- ufixed point input
+ return REAL is
+ constant left_index : INTEGER := arg'high;
+ constant right_index : INTEGER := arg'low;
+ variable result : REAL; -- result
+ variable arg_int : sfixed (left_index downto right_index);
+ -- unsigned version of argument
+ variable arg_uns : ufixed (left_index downto right_index);
+ -- absolute of argument
+ begin
+ if (arg'length < 1) then
+ return 0.0;
+ end if;
+ arg_int := cleanvec(arg);
+ if (Is_X(arg_int)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
+ severity warning;
+ return 0.0;
+ end if;
+ arg_uns := abs(arg_int);
+ result := to_real (arg_uns);
+ if (arg_int(arg_int'high) = '1') then
+ result := -result;
+ end if;
+ return result;
+ end function to_real;
+
+ function to_integer (
+ arg : ufixed; -- fixed point input
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return NATURAL is
+ constant left_index : INTEGER := arg'high;
+ variable arg_uns : UNSIGNED (minimum(31, left_index+1) downto 0)
+ := (others => '0');
+ begin
+ if (arg'length < 1) then
+ return 0;
+ end if;
+ if (Is_X (arg)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
+ severity warning;
+ return 0;
+ end if;
+ if (left_index < -1) then
+ return 0;
+ end if;
+ arg_uns := to_uns(resize (arg => arg,
+ left_index => arg_uns'high,
+ right_index => 0,
+ round_style => round_style,
+ overflow_style => overflow_style));
+ return to_integer (arg_uns);
+ end function to_integer;
+
+ function to_integer (
+ arg : sfixed; -- fixed point input
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
+ return INTEGER is
+ constant left_index : INTEGER := arg'high;
+ constant right_index : INTEGER := arg'low;
+ variable arg_s : SIGNED (minimum(31, left_index+1) downto 0);
+ begin
+ if (arg'length < 1) then
+ return 0;
+ end if;
+ if (Is_X (arg)) then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
+ severity warning;
+ return 0;
+ end if;
+ if (left_index < -1) then
+ return 0;
+ end if;
+ arg_s := to_s(resize (arg => arg,
+ left_index => arg_s'high,
+ right_index => 0,
+ round_style => round_style,
+ overflow_style => overflow_style));
+ return to_integer (arg_s);
+ end function to_integer;
+
+ function to_01 (
+ s : ufixed; -- ufixed point input
+ constant XMAP : STD_LOGIC := '0') -- Map x to
+ return ufixed is
+ variable result : ufixed (s'range); -- result
+ begin
+ for i in s'range loop
+ case s(i) is
+ when '0' | 'L' => result(i) := '0';
+ when '1' | 'H' => result(i) := '1';
+ when others => result(i) := XMAP;
+ end case;
+ end loop;
+ return result;
+ end function to_01;
+
+ function to_01 (
+ s : sfixed; -- ufixed point input
+ constant XMAP : STD_LOGIC := '0') -- Map x to
+ return sfixed is
+ variable result : sfixed (s'range);
+ begin
+ for i in s'range loop
+ case s(i) is
+ when '0' | 'L' => result(i) := '0';
+ when '1' | 'H' => result(i) := '1';
+ when others => result(i) := XMAP;
+ end case;
+ end loop;
+ return result;
+ end function to_01;
+
+ function Is_X (
+ arg : ufixed)
+ return BOOLEAN is
+ variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
+ begin
+ argslv := to_slv(arg);
+ return Is_X(argslv);
+ end function Is_X;
+
+ function Is_X (
+ arg : sfixed)
+ return BOOLEAN is
+ variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
+ begin
+ argslv := to_slv(arg);
+ return Is_X(argslv);
+ end function Is_X;
+
+ function To_X01 (
+ arg : ufixed)
+ return ufixed is
+ begin
+ return to_ufixed (To_X01(to_slv(arg)), arg'high, arg'low);
+ end function To_X01;
+
+ function to_X01 (
+ arg : sfixed)
+ return sfixed is
+ begin
+ return to_sfixed (To_X01(to_slv(arg)), arg'high, arg'low);
+ end function To_X01;
+
+ function To_X01Z (
+ arg : ufixed)
+ return ufixed is
+ begin
+ return to_ufixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
+ end function To_X01Z;
+
+ function to_X01Z (
+ arg : sfixed)
+ return sfixed is
+ begin
+ return to_sfixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
+ end function To_X01Z;
+
+ function To_UX01 (
+ arg : ufixed)
+ return ufixed is
+ begin
+ return to_ufixed (To_UX01(to_slv(arg)), arg'high, arg'low);
+ end function To_UX01;
+
+ function to_UX01 (
+ arg : sfixed)
+ return sfixed is
+ begin
+ return to_sfixed (To_UX01(to_slv(arg)), arg'high, arg'low);
+ end function To_UX01;
+
+
+ function resize (
+ arg : ufixed; -- input
+ constant left_index : INTEGER; -- integer portion
+ constant right_index : INTEGER; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding
+ return ufixed is
+ constant arghigh : INTEGER := maximum (arg'high, arg'low);
+ constant arglow : INTEGER := mine (arg'high, arg'low);
+ variable invec : ufixed (arghigh downto arglow);
+ variable result : ufixed(left_index downto right_index) :=
+ (others => '0');
+ variable needs_rounding : BOOLEAN := false;
+ begin -- resize
+ if (arg'length < 1) or (result'length < 1) then
+ return NAUF;
+ elsif (invec'length < 1) then
+ return result; -- string literal value
+ else
+ invec := cleanvec(arg);
+ if (right_index > arghigh) then -- return top zeros
+ needs_rounding := (round_style = fixed_round) and
+ (right_index = arghigh+1);
+ elsif (left_index < arglow) then -- return overflow
+ if (overflow_style = fixed_saturate) and
+ (or_reducex(to_slv(invec)) = '1') then
+ result := saturate (result'high, result'low); -- saturate
+ end if;
+ elsif (arghigh > left_index) then
+ -- wrap or saturate?
+ if (overflow_style and
+ or_reducex(to_slv(invec(arghigh downto left_index+1))) = '1')
+ then
+ result := saturate (result'high, result'low); -- saturate
+ else
+ if (arglow >= right_index) then
+ result (left_index downto arglow) :=
+ invec(left_index downto arglow);
+ else
+ result (left_index downto right_index) :=
+ invec (left_index downto right_index);
+ needs_rounding := (round_style = fixed_round); -- round
+ end if;
+ end if;
+ else -- arghigh <= integer width
+ if (arglow >= right_index) then
+ result (arghigh downto arglow) := invec;
+ else
+ result (arghigh downto right_index) :=
+ invec (arghigh downto right_index);
+ needs_rounding := (round_style = fixed_round); -- round
+ end if;
+ end if;
+ -- Round result
+ if needs_rounding then
+ result := round_fixed (arg => result,
+ remainder => invec (right_index-1
+ downto arglow),
+ overflow_style => overflow_style);
+ end if;
+ return result;
+ end if;
+ end function resize;
+
+ function resize (
+ arg : sfixed; -- input
+ constant left_index : INTEGER; -- integer portion
+ constant right_index : INTEGER; -- size of fraction
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding
+ return sfixed is
+ constant arghigh : INTEGER := maximum (arg'high, arg'low);
+ constant arglow : INTEGER := mine (arg'high, arg'low);
+ variable invec : sfixed (arghigh downto arglow);
+ variable result : sfixed(left_index downto right_index) :=
+ (others => '0');
+ variable reduced : STD_ULOGIC;
+ variable needs_rounding : BOOLEAN := false; -- rounding
+ begin -- resize
+ if (arg'length < 1) or (result'length < 1) then
+ return NASF;
+ elsif (invec'length < 1) then
+ return result; -- string literal value
+ else
+ invec := cleanvec(arg);
+ if (right_index > arghigh) then -- return top zeros
+ if (arg'low /= INTEGER'low) then -- check for a literal
+ result := (others => arg(arghigh)); -- sign extend
+ end if;
+ needs_rounding := (round_style = fixed_round) and
+ (right_index = arghigh+1);
+ elsif (left_index < arglow) then -- return overflow
+ if (overflow_style) then
+ reduced := or_reducex(to_slv(invec));
+ if (reduced = '1') then
+ if (invec(arghigh) = '0') then
+ -- saturate POSITIVE
+ result := saturate (result'high, result'low);
+ else
+ -- saturate negative
+ result := not saturate (result'high, result'low);
+ end if;
+ -- else return 0 (input was 0)
+ end if;
+ -- else return 0 (wrap)
+ end if;
+ elsif (arghigh > left_index) then
+ if (invec(arghigh) = '0') then
+ reduced := or_reducex(to_slv(invec(arghigh-1 downto
+ left_index)));
+ if overflow_style and reduced = '1' then
+ -- saturate positive
+ result := saturate (result'high, result'low);
+ else
+ if (right_index > arglow) then
+ result := invec (left_index downto right_index);
+ needs_rounding := (round_style = fixed_round);
+ else
+ result (left_index downto arglow) :=
+ invec (left_index downto arglow);
+ end if;
+ end if;
+ else
+ reduced := and_reducex(to_slv(invec(arghigh-1 downto
+ left_index)));
+ if overflow_style and reduced = '0' then
+ result := not saturate (result'high, result'low);
+ else
+ if (right_index > arglow) then
+ result := invec (left_index downto right_index);
+ needs_rounding := (round_style = fixed_round);
+ else
+ result (left_index downto arglow) :=
+ invec (left_index downto arglow);
+ end if;
+ end if;
+ end if;
+ else -- arghigh <= integer width
+ if (arglow >= right_index) then
+ result (arghigh downto arglow) := invec;
+ else
+ result (arghigh downto right_index) :=
+ invec (arghigh downto right_index);
+ needs_rounding := (round_style = fixed_round); -- round
+ end if;
+ if (left_index > arghigh) then -- sign extend
+ result(left_index downto arghigh+1) := (others => invec(arghigh));
+ end if;
+ end if;
+ -- Round result
+ if (needs_rounding) then
+ result := round_fixed (arg => result,
+ remainder => invec (right_index-1
+ downto arglow),
+ overflow_style => overflow_style);
+ end if;
+ return result;
+ end if;
+ end function resize;
+
+ -- size_res functions
+ -- These functions compute the size from a passed variable named "size_res"
+ -- The only part of this variable used it it's size, it is never passed
+ -- to a lower level routine.
+ function to_ufixed (
+ arg : STD_LOGIC_VECTOR; -- shifted vector
+ size_res : ufixed) -- for size only
+ return ufixed is
+ variable result : ufixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_ufixed (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low);
+ return result;
+ end if;
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : STD_LOGIC_VECTOR; -- shifted vector
+ size_res : sfixed) -- for size only
+ return sfixed is
+ variable result : sfixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_sfixed (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low);
+ return result;
+ end if;
+ end function to_sfixed;
+
+ function to_ufixed (
+ arg : STD_ULOGIC_VECTOR; -- shifted vector
+ size_res : ufixed) -- for size only
+ return ufixed is
+ variable result : ufixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_ufixed (arg => to_stdlogicvector(arg),
+ left_index => size_res'high,
+ right_index => size_res'low);
+ return result;
+ end if;
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : STD_ULOGIC_VECTOR; -- shifted vector
+ size_res : sfixed) -- for size only
+ return sfixed is
+ variable result : sfixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_sfixed (arg => to_stdlogicvector(arg),
+ left_index => size_res'high,
+ right_index => size_res'low);
+ return result;
+ end if;
+ end function to_sfixed;
+
+ function to_ufixed (
+ arg : NATURAL; -- integer
+ size_res : ufixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
+ return ufixed is
+ variable result : ufixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_ufixed (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end if;
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : INTEGER; -- integer
+ size_res : sfixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
+ return sfixed is
+ variable result : sfixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_sfixed (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end if;
+ end function to_sfixed;
+
+ function to_ufixed (
+ arg : REAL; -- real
+ size_res : ufixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
+ constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
+ return ufixed is
+ variable result : ufixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_ufixed (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low,
+ guard_bits => guard_bits,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end if;
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : REAL; -- real
+ size_res : sfixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
+ constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
+ return sfixed is
+ variable result : sfixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_sfixed (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low,
+ guard_bits => guard_bits,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end if;
+ end function to_sfixed;
+
+ function to_ufixed (
+ arg : UNSIGNED; -- unsigned
+ size_res : ufixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding
+ return ufixed is
+ variable result : ufixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_ufixed (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end if;
+ end function to_ufixed;
+
+ function to_sfixed (
+ arg : SIGNED; -- signed
+ size_res : sfixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
+ constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
+ return sfixed is
+ variable result : sfixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_sfixed (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end if;
+ end function to_sfixed;
+
+ function resize (
+ arg : ufixed; -- input
+ size_res : ufixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding
+ return ufixed is
+ variable result : ufixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := resize (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end if;
+ end function resize;
+
+ function resize (
+ arg : sfixed; -- input
+ size_res : sfixed; -- for size only
+ constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
+ constant round_style : BOOLEAN := fixed_round_style) -- rounding
+ return sfixed is
+ variable result : sfixed (size_res'left downto size_res'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := resize (arg => arg,
+ left_index => size_res'high,
+ right_index => size_res'low,
+ round_style => round_style,
+ overflow_style => overflow_style);
+ return result;
+ end if;
+ end function resize;
+
+ -- Overloaded functions
+ function "+" (
+ l : ufixed; -- fixed point input
+ r : REAL)
+ return ufixed is
+ begin
+ return (l +
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "+";
+
+ function "+" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ + r);
+ end function "+";
+
+ function "+" (
+ l : sfixed; -- fixed point input
+ r : REAL)
+ return sfixed is
+ begin
+ return (l +
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "+";
+
+ function "+" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ + r);
+ end function "+";
+
+ -- Overloaded functions
+ function "-" (
+ l : ufixed; -- fixed point input
+ r : REAL)
+ return ufixed is
+ begin
+ return (l -
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "-";
+
+ function "-" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ - r);
+ end function "-";
+
+ function "-" (
+ l : sfixed; -- fixed point input
+ r : REAL)
+ return sfixed is
+ begin
+ return (l -
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "-";
+
+ function "-" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ - r);
+ end function "-";
+
+ -- Overloaded functions
+ function "*" (
+ l : ufixed; -- fixed point input
+ r : REAL)
+ return ufixed is
+ begin
+ return (l *
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "*";
+
+ function "*" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ * r);
+ end function "*";
+
+ function "*" (
+ l : sfixed; -- fixed point input
+ r : REAL)
+ return sfixed is
+ begin
+ return (l *
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "*";
+
+ function "*" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ * r);
+ end function "*";
+
+ -- Overloaded functions
+ function "/" (
+ l : ufixed; -- fixed point input
+ r : REAL)
+ return ufixed is
+ begin
+ return (l /
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "/";
+
+ function "/" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ / r);
+ end function "/";
+
+ function "/" (
+ l : sfixed; -- fixed point input
+ r : REAL)
+ return sfixed is
+ begin
+ return (l /
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "/";
+
+ function "/" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ / r);
+ end function "/";
+
+ -- Overloaded functions
+ function "rem" (
+ l : ufixed; -- fixed point input
+ r : REAL)
+ return ufixed is
+ begin
+ return (l rem
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "rem";
+
+ function "rem" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ rem r);
+ end function "rem";
+
+ function "rem" (
+ l : sfixed; -- fixed point input
+ r : REAL)
+ return sfixed is
+ begin
+ return (l rem
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "rem";
+
+ function "rem" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ rem r);
+ end function "rem";
+
+ function "mod" (
+ l : ufixed; -- fixed point input
+ r : REAL)
+ return ufixed is
+ begin
+ return (l mod
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "mod";
+
+ function "mod" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ mod r);
+ end function "mod";
+
+ function "mod" (
+ l : sfixed; -- fixed point input
+ r : REAL)
+ return sfixed is
+ begin
+ return (l mod
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "mod";
+
+ function "mod" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ mod r);
+ end function "mod";
+
+ -- Overloaded functions for integers
+ function "+" (
+ l : ufixed; -- fixed point input
+ r : NATURAL)
+ return ufixed is
+ begin
+ return (l + to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)); -- rounding not needed
+ end function "+";
+
+ function "+" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ + r);
+ end function "+";
+
+ function "+" (
+ l : sfixed; -- fixed point input
+ r : INTEGER)
+ return sfixed is
+ begin
+ return (l + to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "+";
+
+ function "+" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ + r);
+ end function "+";
+
+ -- Overloaded functions
+ function "-" (
+ l : ufixed; -- fixed point input
+ r : NATURAL)
+ return ufixed is
+ begin
+ return (l - to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "-";
+
+ function "-" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ - r);
+ end function "-";
+
+ function "-" (
+ l : sfixed; -- fixed point input
+ r : INTEGER)
+ return sfixed is
+ begin
+ return (l - to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "-";
+
+ function "-" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ - r);
+ end function "-";
+
+ -- Overloaded functions
+ function "*" (
+ l : ufixed; -- fixed point input
+ r : NATURAL)
+ return ufixed is
+ begin
+ return (l * to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "*";
+
+ function "*" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ * r);
+ end function "*";
+
+ function "*" (
+ l : sfixed; -- fixed point input
+ r : INTEGER)
+ return sfixed is
+ begin
+ return (l * to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "*";
+
+ function "*" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ * r);
+ end function "*";
+
+ -- Overloaded functions
+ function "/" (
+ l : ufixed; -- fixed point input
+ r : NATURAL)
+ return ufixed is
+ begin
+ return (l / to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "/";
+
+ function "/" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ / r);
+ end function "/";
+
+ function "/" (
+ l : sfixed; -- fixed point input
+ r : INTEGER)
+ return sfixed is
+ begin
+ return (l / to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "/";
+
+ function "/" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ / r);
+ end function "/";
+
+ -- Overloaded functions
+ function "rem" (
+ l : ufixed; -- fixed point input
+ r : NATURAL)
+ return ufixed is
+ begin
+ return (l rem to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "rem";
+
+ function "rem" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ rem r);
+ end function "rem";
+
+ function "rem" (
+ l : sfixed; -- fixed point input
+ r : INTEGER)
+ return sfixed is
+ begin
+ return (l rem to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "rem";
+
+ function "rem" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ rem r);
+ end function "rem";
+
+ function "mod" (
+ l : ufixed; -- fixed point input
+ r : NATURAL)
+ return ufixed is
+ begin
+ return (l mod to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "mod";
+
+ function "mod" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return ufixed is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ mod r);
+ end function "mod";
+
+ function "mod" (
+ l : sfixed; -- fixed point input
+ r : INTEGER)
+ return sfixed is
+ begin
+ return (l mod to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "mod";
+
+ function "mod" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return sfixed is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ mod r);
+ end function "mod";
+
+ -- overloaded compare functions
+ function "=" (
+ l : ufixed;
+ r : NATURAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l = to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "=";
+
+ function "/=" (
+ l : ufixed;
+ r : NATURAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l /= to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "/=";
+
+ function ">=" (
+ l : ufixed;
+ r : NATURAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l >= to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function ">=";
+
+ function "<=" (
+ l : ufixed;
+ r : NATURAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l <= to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "<=";
+
+ function ">" (
+ l : ufixed;
+ r : NATURAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l > to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function ">";
+
+ function "<" (
+ l : ufixed;
+ r : NATURAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l < to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "<";
+
+ function "=" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ = r);
+ end function "=";
+
+ function "/=" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ /= r);
+ end function "/=";
+
+ function ">=" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ >= r);
+ end function ">=";
+
+ function "<=" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ <= r);
+ end function "<=";
+
+ function ">" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ > r);
+ end function ">";
+
+ function "<" (
+ l : NATURAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ < r);
+ end function "<";
+
+ function "=" (
+ l : ufixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l =
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "=";
+
+ function "/=" (
+ l : ufixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l /=
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "/=";
+
+ function ">=" (
+ l : ufixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l >=
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function ">=";
+
+ function "<=" (
+ l : ufixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l <=
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "<=";
+
+ function ">" (
+ l : ufixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l >
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function ">";
+
+ function "<" (
+ l : ufixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l <
+ to_ufixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "<";
+
+ function "=" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ = r);
+ end function "=";
+
+ function "/=" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ /= r);
+ end function "/=";
+
+ function ">=" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ >= r);
+ end function ">=";
+
+ function "<=" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ <= r);
+ end function "<=";
+
+ function ">" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ > r);
+ end function ">";
+
+ function "<" (
+ l : REAL;
+ r : ufixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_ufixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ < r);
+ end function "<";
+
+ function "=" (
+ l : sfixed;
+ r : INTEGER) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l = to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "=";
+
+ function "/=" (
+ l : sfixed;
+ r : INTEGER) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l /= to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "/=";
+
+ function ">=" (
+ l : sfixed;
+ r : INTEGER) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l >= to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function ">=";
+
+ function "<=" (
+ l : sfixed;
+ r : INTEGER) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l <= to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "<=";
+
+ function ">" (
+ l : sfixed;
+ r : INTEGER) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l > to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function ">";
+
+ function "<" (
+ l : sfixed;
+ r : INTEGER) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l < to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style));
+ end function "<";
+
+ function "=" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ = r);
+ end function "=";
+
+ function "/=" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ /= r);
+ end function "/=";
+
+ function ">=" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ >= r);
+ end function ">=";
+
+ function "<=" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ <= r);
+ end function "<=";
+
+ function ">" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ > r);
+ end function ">";
+
+ function "<" (
+ l : INTEGER;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style)
+ < r);
+ end function "<";
+
+ function "=" (
+ l : sfixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l =
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "=";
+
+ function "/=" (
+ l : sfixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l /=
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "/=";
+
+ function ">=" (
+ l : sfixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l >=
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function ">=";
+
+ function "<=" (
+ l : sfixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l <=
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "<=";
+
+ function ">" (
+ l : sfixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l >
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function ">";
+
+ function "<" (
+ l : sfixed;
+ r : REAL) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (l <
+ to_sfixed (arg => r,
+ left_index => l'high,
+ right_index => l'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits));
+ end function "<";
+
+ function "=" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ = r);
+ end function "=";
+
+ function "/=" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ /= r);
+ end function "/=";
+
+ function ">=" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ >= r);
+ end function ">=";
+
+ function "<=" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ <= r);
+ end function "<=";
+
+ function ">" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ > r);
+ end function ">";
+
+ function "<" (
+ l : REAL;
+ r : sfixed) -- fixed point input
+ return BOOLEAN is
+ begin
+ return (to_sfixed (arg => l,
+ left_index => r'high,
+ right_index => r'low,
+ overflow_style => fixed_overflow_style,
+ round_style => fixed_round_style,
+ guard_bits => fixed_guard_bits)
+ < r);
+ end function "<";
+
+ -- rtl_synthesis off
+ -- synthesis translate_off
+ -- copied from std_logic_textio
+ type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
+ type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
+ type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
+ type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
+
+ constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
+ constant char_to_MVL9 : MVL9_indexed_by_char :=
+ ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
+ 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
+ constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
+ ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
+ 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
+ constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
+ constant NUS : STRING(2 to 1) := (others => ' ');
+
+ -- purpose: writes fixed point into a line
+ procedure write (
+ L : inout LINE; -- input line
+ VALUE : in ufixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0) is
+ variable s : STRING(1 to value'length +1) := (others => ' ');
+ variable sindx : INTEGER;
+ begin -- function write Example: 0011.1100
+ sindx := 1;
+ for i in value'high downto value'low loop
+ if i = -1 then
+ s(sindx) := '.';
+ sindx := sindx +1;
+ end if;
+ s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
+ sindx := sindx +1;
+ end loop;
+ write(l, s, justified, field);
+ end procedure write;
+
+ -- purpose: writes fixed point into a line
+ procedure write (
+ L : inout LINE; -- input line
+ VALUE : in sfixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0) is
+ variable s : STRING(1 to value'length +1);
+ variable sindx : INTEGER;
+ begin -- function write Example: 0011.1100
+ sindx := 1;
+ for i in value'high downto value'low loop
+ if i = -1 then
+ s(sindx) := '.';
+ sindx := sindx +1;
+ end if;
+ s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
+ sindx := sindx +1;
+ end loop;
+ write(l, s, justified, field);
+ end procedure write;
+
+ procedure READ(L : inout LINE;
+ VALUE : out ufixed) is
+ -- Possible data: 00000.0000000
+ -- 000000000000
+ variable c : CHARACTER;
+ variable s : STRING(1 to value'length-1);
+ variable readOk : BOOLEAN;
+ variable i : INTEGER; -- index variable
+ begin -- READ
+ VALUE (VALUE'range) := (others => 'U');
+ loop -- skip white space
+ read(l, c, readOk);
+ exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ i := value'high;
+ readloop : loop
+ if readOk = false then -- Bail out if there was a bad read
+ report "FIXED_GENERIC_PKG.READ(ufixed) "
+ & "Error: end of string encountered"
+ severity error;
+ return;
+ elsif c = ' ' or c = NBSP or c = HT then -- reading done.
+ assert i = value'low
+ report "FIXED_GENERIC_PKG.READ(ufixed) "
+ & "Warning: Value truncated " severity warning;
+ return;
+ elsif c = '.' then -- separator, ignore
+ assert (i = -1)
+ report "FIXED_GENERIC_PKG.READ(ufixed) "
+ & "Warning: Decimal point does not match number format "
+ severity warning;
+ elsif (char_to_MVL9plus(c) = error) then
+ report "FIXED_GENERIC_PKG.READ(ufixed) "
+ & "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
+ severity error;
+ return;
+ else
+ value (i) := char_to_MVL9(c);
+ i := i - 1;
+ if i < value'low then
+ return;
+ end if;
+ end if;
+ read(l, c, readOk);
+ end loop readloop;
+ end procedure READ;
+
+ procedure READ(L : inout LINE;
+ VALUE : out ufixed;
+ GOOD : out BOOLEAN) is
+ -- Possible data: 00000.0000000
+ -- 000000000000
+ variable c : CHARACTER;
+ variable i : INTEGER; -- index variable
+ variable readOk : BOOLEAN;
+ begin -- READ
+ VALUE (VALUE'range) := (others => 'U');
+ loop -- skip white space
+ read(l, c, readOk);
+ exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ i := value'high;
+ good := true;
+ readloop : loop
+ if readOk = false then -- Bail out if there was a bad read
+ good := false;
+ return;
+ elsif c = ' ' or c = NBSP or c = HT then -- reading done
+ good := false;
+ return;
+ elsif c = '.' then -- separator, ignore
+ good := (i = -1);
+ elsif (char_to_MVL9plus(c) = error) then
+ good := false;
+ return;
+ else
+ value (i) := char_to_MVL9(c);
+ i := i - 1;
+ if i < value'low then
+ return;
+ end if;
+ end if;
+ read(l, c, readOk);
+ end loop readloop;
+ end procedure READ;
+
+ procedure READ(L : inout LINE;
+ VALUE : out sfixed) is
+ -- Possible data: 00000.0000000
+ -- 000000000000
+ variable c : CHARACTER;
+ variable readOk : BOOLEAN;
+ variable i : INTEGER; -- index variable
+ begin -- READ
+ VALUE (VALUE'range) := (others => 'U');
+ loop -- skip white space
+ read(l, c, readOk);
+ exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ i := value'high;
+ readloop : loop
+ if readOk = false then -- Bail out if there was a bad read
+ report "FIXED_GENERIC_PKG.READ(sfixed) "
+ & "Error end of string encountered"
+ severity error;
+ return;
+ elsif c = ' ' or c = NBSP or c = HT then -- reading done.
+ assert i = value'low
+ report "FIXED_GENERIC_PKG.READ(sfixed) "
+ & "Warning: Value truncated " severity warning;
+ return;
+ elsif c = '.' then -- separator, ignore
+ assert (i = -1)
+ report "FIXED_GENERIC_PKG.READ(sfixed) "
+ & "Warning: Decimal point does not match number format "
+ severity warning;
+ elsif (char_to_MVL9plus(c) = error) then
+ report "FIXED_GENERIC_PKG.READ(sfixed) "
+ & "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
+ severity error;
+ return;
+ else
+ value (i) := char_to_MVL9(c);
+ i := i - 1;
+ if i < value'low then
+ return;
+ end if;
+ end if;
+ read(l, c, readOk);
+ end loop readloop;
+ end procedure READ;
+
+ procedure READ(L : inout LINE;
+ VALUE : out sfixed;
+ GOOD : out BOOLEAN) is
+ -- Possible data: 00000.0000000
+ -- 000000000000
+ variable c : CHARACTER;
+ variable i : INTEGER; -- index variable
+ variable readOk : BOOLEAN;
+ begin -- READ
+ VALUE (VALUE'range) := (others => 'U');
+ loop -- skip white space
+ read(l, c, readOk);
+ exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ i := value'high;
+ good := true;
+ readloop : loop
+ if readOk = false then -- Bail out if there was a bad read
+ good := false;
+ return;
+ elsif c = ' ' or c = NBSP or c = HT then -- reading done
+ good := false;
+ return;
+ elsif c = '.' then -- separator, ignore
+ good := (i = -1);
+ elsif (char_to_MVL9plus(c) = error) then
+ good := false;
+ return;
+ else
+ value (i) := char_to_MVL9(c);
+ i := i - 1;
+ if i < value'low then
+ return;
+ end if;
+ end if;
+ read(l, c, readOk);
+ end loop readloop;
+ end procedure READ;
+
+ -- octal read and write
+ procedure owrite (
+ L : inout LINE; -- input line
+ VALUE : in ufixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0) is
+ begin -- Example 03.30
+ write (L => L,
+ VALUE => to_ostring (VALUE),
+ JUSTIFIED => JUSTIFIED,
+ FIELD => FIELD);
+ end procedure owrite;
+
+ procedure owrite (
+ L : inout LINE; -- input line
+ VALUE : in sfixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0) is
+ begin -- Example 03.30
+ write (L => L,
+ VALUE => to_ostring (VALUE),
+ JUSTIFIED => JUSTIFIED,
+ FIELD => FIELD);
+ end procedure owrite;
+
+ procedure Char2TriBits (C : CHARACTER;
+ RESULT : out STD_LOGIC_VECTOR(2 downto 0);
+ GOOD : out BOOLEAN;
+ ISSUE_ERROR : in BOOLEAN) is
+ begin
+ case c is
+ when '0' => result := o"0"; good := true;
+ when '1' => result := o"1"; good := true;
+ when '2' => result := o"2"; good := true;
+ when '3' => result := o"3"; good := true;
+ when '4' => result := o"4"; good := true;
+ when '5' => result := o"5"; good := true;
+ when '6' => result := o"6"; good := true;
+ when '7' => result := o"7"; good := true;
+ when 'Z' => result := "ZZZ"; good := true;
+ when 'X' => result := "XXX"; good := true;
+ when others =>
+ assert not ISSUE_ERROR
+ report
+ "FIXED_GENERIC_PKG.OREAD Error: Read a '" & c &
+ "', expected an Octal character (0-7)."
+ severity error;
+ result := "UUU";
+ good := false;
+ end case;
+ end procedure Char2TriBits;
+
+ -- Note that for Octal and Hex read, you can not start with a ".",
+ -- the read is for numbers formatted "A.BC". These routines go to
+ -- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
+ procedure OREAD(L : inout LINE;
+ VALUE : out ufixed) is
+ constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
+ constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
+ variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
+ variable c : CHARACTER; -- to read the "."
+ variable valuex : ufixed (hbv downto lbv);
+ variable igood : BOOLEAN;
+ variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
+ variable i : INTEGER;
+ begin
+ VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
+ loop -- skip white space
+ read(L, c, igood);
+ exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ if igood = false then
+ report "FIXED_GENERIC_PKG.OREAD(ufixed): "
+ & "Error end of string encountered"
+ severity error;
+ return;
+ else
+ Char2triBits(c, nybble, igood, true);
+ i := hbv-lbv - 3; -- Top - 3
+ slv (hbv-lbv downto i+1) := nybble;
+ end if;
+ while (i /= -1) and igood and L.all'length /= 0 loop
+ read (L, c, igood);
+ if igood = false then
+ report "FIXED_GENERIC_PKG.OREAD(ufixed): "
+ & "Error end of string encountered"
+ severity error;
+ elsif (c = '.') then
+ if (i + 1 /= -lbv) then
+ igood := false;
+ report "FIXED_GENERIC_PKG.OREAD(ufixed): "
+ & "encountered ""."" at wrong index"
+ severity error;
+ end if;
+ else
+ Char2TriBits(c, nybble, igood, true);
+ slv (i downto i-2) := nybble;
+ i := i - 3;
+ end if;
+ end loop;
+ if igood then -- We did not get another error
+ assert (i = -1) and -- We read everything, and high bits 0
+ (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
+ report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated."
+ severity error;
+ if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated"
+ severity warning;
+ end if;
+ end if;
+ valuex := to_ufixed (slv, hbv, lbv);
+ VALUE := valuex (VALUE'range);
+ end procedure OREAD;
+
+ procedure OREAD(L : inout LINE;
+ VALUE : out ufixed;
+ GOOD : out BOOLEAN) is
+ constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
+ constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
+ variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
+ variable c : CHARACTER; -- to read the "."
+ variable valuex : ufixed (hbv downto lbv);
+ variable igood : BOOLEAN;
+ variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
+ variable i : INTEGER;
+ begin
+ VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
+ loop -- skip white space
+ read(L, c, igood);
+ exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ if igood = false then
+ return;
+ else
+ Char2triBits(c, nybble, igood, false);
+ i := hbv-lbv - 3; -- Top - 3
+ slv (hbv-lbv downto i+1) := nybble;
+ end if;
+ while (i /= -1) and igood and L.all'length /= 0 loop
+ read (L, c, igood);
+ if igood then
+ if (c = '.') then
+ igood := igood and (i + 1 = -lbv);
+ else
+ Char2TriBits(c, nybble, igood, false);
+ slv (i downto i-2) := nybble;
+ i := i - 3;
+ end if;
+ end if;
+ end loop;
+ good := igood and -- We did not get another error
+ (i = -1) and -- We read everything, and high bits 0
+ (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
+ valuex := to_ufixed (slv, hbv, lbv);
+ VALUE := valuex (VALUE'range);
+ end procedure OREAD;
+
+ procedure OREAD(L : inout LINE;
+ VALUE : out sfixed) is
+ constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
+ constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
+ variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
+ variable c : CHARACTER; -- to read the "."
+ variable valuex : sfixed (hbv downto lbv);
+ variable igood : BOOLEAN;
+ variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
+ variable i : INTEGER;
+ begin
+ VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
+ loop -- skip white space
+ read(L, c, igood);
+ exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ if igood = false then
+ report "FIXED_GENERIC_PKG.OREAD(sfixed): "
+ & "Error end of string encountered"
+ severity error;
+ return;
+ else
+ Char2triBits(c, nybble, igood, true);
+ i := hbv-lbv - 3; -- Top - 3
+ slv (hbv-lbv downto i+1) := nybble;
+ end if;
+ while (i /= -1) and igood and L.all'length /= 0 loop
+ read (L, c, igood);
+ if igood = false then
+ report "FIXED_GENERIC_PKG.OREAD(sfixed): "
+ & "Error end of string encountered"
+ severity error;
+ elsif (c = '.') then
+ if (i + 1 /= -lbv) then
+ igood := false;
+ report "FIXED_GENERIC_PKG.OREAD(sfixed): "
+ & "encountered ""."" at wrong index"
+ severity error;
+ end if;
+ else
+ Char2TriBits(c, nybble, igood, true);
+ slv (i downto i-2) := nybble;
+ i := i - 3;
+ end if;
+ end loop;
+ if igood then -- We did not get another error
+ assert (i = -1) and -- We read everything
+ ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
+ or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
+ (slv(VALUE'high-lbv) = '1' and
+ and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
+ report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated."
+ severity error;
+ if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated"
+ severity warning;
+ end if;
+ end if;
+ valuex := to_sfixed (slv, hbv, lbv);
+ VALUE := valuex (VALUE'range);
+ end procedure OREAD;
+
+ procedure OREAD(L : inout LINE;
+ VALUE : out sfixed;
+ GOOD : out BOOLEAN) is
+ constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
+ constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
+ variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
+ variable c : CHARACTER; -- to read the "."
+ variable valuex : sfixed (hbv downto lbv);
+ variable igood : BOOLEAN;
+ variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
+ variable i : INTEGER;
+ begin
+ VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
+ loop -- skip white space
+ read(L, c, igood);
+ exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ if igood = false then
+ return;
+ else
+ Char2triBits(c, nybble, igood, false);
+ i := hbv-lbv - 3; -- Top - 3
+ slv (hbv-lbv downto i+1) := nybble;
+ end if;
+ while (i /= -1) and igood and L.all'length /= 0 loop
+ read (L, c, igood);
+ if igood then
+ if (c = '.') then
+ igood := igood and (i + 1 = -lbv);
+ else
+ Char2TriBits(c, nybble, igood, false);
+ slv (i downto i-2) := nybble;
+ i := i - 3;
+ end if;
+ end if;
+ end loop;
+ good := igood -- We did not get another error
+ and (i = -1) -- We read everything
+ and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
+ or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
+ (slv(VALUE'high-lbv) = '1' and
+ and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
+ valuex := to_sfixed (slv, hbv, lbv);
+ VALUE := valuex (VALUE'range);
+ end procedure OREAD;
+
+ -- hex read and write
+ procedure hwrite (
+ L : inout LINE; -- input line
+ VALUE : in ufixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0) is
+ begin -- Example 03.30
+ write (L => L,
+ VALUE => to_hstring (VALUE),
+ JUSTIFIED => JUSTIFIED,
+ FIELD => FIELD);
+ end procedure hwrite;
+
+ -- purpose: writes fixed point into a line
+ procedure hwrite (
+ L : inout LINE; -- input line
+ VALUE : in sfixed; -- fixed point input
+ JUSTIFIED : in SIDE := right;
+ FIELD : in WIDTH := 0) is
+ begin -- Example 03.30
+ write (L => L,
+ VALUE => to_hstring (VALUE),
+ JUSTIFIED => JUSTIFIED,
+ FIELD => FIELD);
+ end procedure hwrite;
+
+ -- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
+ -- Modified from the original to be more forgiving.
+
+ procedure Char2QuadBits (C : CHARACTER;
+ RESULT : out STD_LOGIC_VECTOR(3 downto 0);
+ GOOD : out BOOLEAN;
+ ISSUE_ERROR : in BOOLEAN) is
+ begin
+ case c is
+ when '0' => result := x"0"; good := true;
+ when '1' => result := x"1"; good := true;
+ when '2' => result := x"2"; good := true;
+ when '3' => result := x"3"; good := true;
+ when '4' => result := x"4"; good := true;
+ when '5' => result := x"5"; good := true;
+ when '6' => result := x"6"; good := true;
+ when '7' => result := x"7"; good := true;
+ when '8' => result := x"8"; good := true;
+ when '9' => result := x"9"; good := true;
+ when 'A' | 'a' => result := x"A"; good := true;
+ when 'B' | 'b' => result := x"B"; good := true;
+ when 'C' | 'c' => result := x"C"; good := true;
+ when 'D' | 'd' => result := x"D"; good := true;
+ when 'E' | 'e' => result := x"E"; good := true;
+ when 'F' | 'f' => result := x"F"; good := true;
+ when 'Z' => result := "ZZZZ"; good := true;
+ when 'X' => result := "XXXX"; good := true;
+ when others =>
+ assert not ISSUE_ERROR
+ report
+ "FIXED_GENERIC_PKG.HREAD Error: Read a '" & c &
+ "', expected a Hex character (0-F)."
+ severity error;
+ result := "UUUU";
+ good := false;
+ end case;
+ end procedure Char2QuadBits;
+
+ procedure HREAD(L : inout LINE;
+ VALUE : out ufixed) is
+ constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
+ constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
+ variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
+ variable c : CHARACTER; -- to read the "."
+ variable valuex : ufixed (hbv downto lbv);
+ variable igood : BOOLEAN;
+ variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
+ variable i : INTEGER;
+ begin
+ VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
+ loop -- skip white space
+ read(L, c, igood);
+ exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ if igood = false then
+ report "FIXED_GENERIC_PKG.HREAD(ufixed): "
+ & "Error end of string encountered"
+ severity error;
+ return;
+ else
+ Char2QuadBits(c, nybble, igood, true);
+ i := hbv-lbv - 4; -- Top - 4
+ slv (hbv-lbv downto i+1) := nybble;
+ end if;
+ while (i /= -1) and igood and L.all'length /= 0 loop
+ read (L, c, igood);
+ if igood = false then
+ report "FIXED_GENERIC_PKG.HREAD(ufixed): "
+ & "Error end of string encountered"
+ severity error;
+ elsif (c = '.') then
+ if (i + 1 /= -lbv) then
+ igood := false;
+ report "FIXED_GENERIC_PKG.HREAD(ufixed): "
+ & "encountered ""."" at wrong index"
+ severity error;
+ end if;
+ else
+ Char2QuadBits(c, nybble, igood, true);
+ slv (i downto i-3) := nybble;
+ i := i - 4;
+ end if;
+ end loop;
+ if igood then -- We did not get another error
+ assert (i = -1) and -- We read everything, and high bits 0
+ (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
+ report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated."
+ severity error;
+ if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated"
+ severity warning;
+ end if;
+ end if;
+ valuex := to_ufixed (slv, hbv, lbv);
+ VALUE := valuex (VALUE'range);
+ end procedure HREAD;
+
+ procedure HREAD(L : inout LINE;
+ VALUE : out ufixed;
+ GOOD : out BOOLEAN) is
+ constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
+ constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
+ variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
+ variable c : CHARACTER; -- to read the "."
+ variable valuex : ufixed (hbv downto lbv);
+ variable igood : BOOLEAN;
+ variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
+ variable i : INTEGER;
+ begin
+ VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
+ loop -- skip white space
+ read(L, c, igood);
+ exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ if igood = false then
+ return;
+ else
+ Char2QuadBits(c, nybble, igood, false);
+ i := hbv-lbv - 4; -- Top - 4
+ slv (hbv-lbv downto i+1) := nybble;
+ end if;
+ while (i /= -1) and igood and L.all'length /= 0 loop
+ read (L, c, igood);
+ if igood then
+ if (c = '.') then
+ igood := igood and (i + 1 = -lbv);
+ else
+ Char2QuadBits(c, nybble, igood, false);
+ slv (i downto i-3) := nybble;
+ i := i - 4;
+ end if;
+ end if;
+ end loop;
+ good := igood and -- We did not get another error
+ (i = -1) and -- We read everything, and high bits 0
+ (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
+ valuex := to_ufixed (slv, hbv, lbv);
+ VALUE := valuex (VALUE'range);
+ end procedure HREAD;
+
+ procedure HREAD(L : inout LINE;
+ VALUE : out sfixed) is
+ constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
+ constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
+ variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
+ variable c : CHARACTER; -- to read the "."
+ variable valuex : sfixed (hbv downto lbv);
+ variable igood : BOOLEAN;
+ variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
+ variable i : INTEGER;
+ begin
+ VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
+ loop -- skip white space
+ read(L, c, igood);
+ exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ if igood = false then
+ report "FIXED_GENERIC_PKG.HREAD(sfixed): "
+ & "Error end of string encountered"
+ severity error;
+ return;
+ else
+ Char2QuadBits(c, nybble, igood, true);
+ i := hbv-lbv - 4; -- Top - 4
+ slv (hbv-lbv downto i+1) := nybble;
+ end if;
+ while (i /= -1) and igood and L.all'length /= 0 loop
+ read (L, c, igood);
+ if igood = false then
+ report "FIXED_GENERIC_PKG.HREAD(sfixed): "
+ & "Error end of string encountered"
+ severity error;
+ elsif (c = '.') then
+ if (i + 1 /= -lbv) then
+ igood := false;
+ report "FIXED_GENERIC_PKG.HREAD(sfixed): "
+ & "encountered ""."" at wrong index"
+ severity error;
+ end if;
+ else
+ Char2QuadBits(c, nybble, igood, true);
+ slv (i downto i-3) := nybble;
+ i := i - 4;
+ end if;
+ end loop;
+ if igood then -- We did not get another error
+ assert (i = -1) -- We read everything
+ and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
+ or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
+ (slv(VALUE'high-lbv) = '1' and
+ and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
+ report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated."
+ severity error;
+ if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
+ assert NO_WARNING
+ report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated"
+ severity warning;
+ end if;
+ end if;
+ valuex := to_sfixed (slv, hbv, lbv);
+ VALUE := valuex (VALUE'range);
+ end procedure HREAD;
+
+ procedure HREAD(L : inout LINE;
+ VALUE : out sfixed;
+ GOOD : out BOOLEAN) is
+ constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
+ constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
+ variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
+ variable c : CHARACTER; -- to read the "."
+ variable valuex : sfixed (hbv downto lbv);
+ variable igood : BOOLEAN;
+ variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
+ variable i : INTEGER;
+ begin
+ VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
+ loop -- skip white space
+ read(L, c, igood);
+ exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
+ end loop;
+ if igood = false then
+ return;
+ else
+ Char2QuadBits(c, nybble, igood, false);
+ i := hbv-lbv - 4; -- Top - 4
+ slv (hbv-lbv downto i+1) := nybble;
+ end if;
+ while (i /= -1) and igood and L.all'length /= 0 loop
+ read (L, c, igood);
+ if igood then
+ if (c = '.') then
+ igood := igood and (i + 1 = -lbv);
+ else
+ Char2QuadBits(c, nybble, igood, false);
+ slv (i downto i-3) := nybble;
+ i := i - 4;
+ end if;
+ end if;
+ end loop;
+ good := igood and -- We did not get another error
+ (i = -1) and -- We read everything
+ ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
+ or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
+ (slv(VALUE'high-lbv) = '1' and
+ and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
+ valuex := to_sfixed (slv, hbv, lbv);
+ VALUE := valuex (VALUE'range);
+ end procedure HREAD;
+
+ -----------------------------------------------------------------------------
+ -- %%% Remove the following 3 functions. They are a duplicate needed for
+ -- testing
+ -----------------------------------------------------------------------------
+ -- purpose: Justify a string to the right
+ function justify (
+ value : STRING;
+ justified : SIDE := right;
+ field : width := 0)
+ return STRING is
+ constant VAL_LEN : INTEGER := value'length;
+ variable result : STRING (1 to field) := (others => ' ');
+ begin -- function justify
+ -- return value if field is too small
+ if VAL_LEN >= field then
+ return value;
+ end if;
+ if justified = left then
+ result(1 to VAL_LEN) := value;
+ elsif justified = right then
+ result(field - VAL_LEN + 1 to field) := value;
+ end if;
+ return result;
+ end function justify;
+
+ function to_ostring (
+ value : STD_LOGIC_VECTOR;
+ justified : SIDE := right;
+ field : width := 0
+ ) return STRING is
+ constant ne : INTEGER := (value'length+2)/3;
+ variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
+ variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
+ variable result : STRING(1 to ne);
+ variable tri : STD_LOGIC_VECTOR(0 to 2);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ if value (value'left) = 'Z' then
+ pad := (others => 'Z');
+ else
+ pad := (others => '0');
+ end if;
+ ivalue := pad & value;
+ for i in 0 to ne-1 loop
+ tri := To_X01Z(ivalue(3*i to 3*i+2));
+ case tri is
+ when o"0" => result(i+1) := '0';
+ when o"1" => result(i+1) := '1';
+ when o"2" => result(i+1) := '2';
+ when o"3" => result(i+1) := '3';
+ when o"4" => result(i+1) := '4';
+ when o"5" => result(i+1) := '5';
+ when o"6" => result(i+1) := '6';
+ when o"7" => result(i+1) := '7';
+ when "ZZZ" => result(i+1) := 'Z';
+ when others => result(i+1) := 'X';
+ end case;
+ end loop;
+ return justify(result, justified, field);
+ end if;
+ end function to_ostring;
+ -------------------------------------------------------------------
+ function to_hstring (
+ value : STD_LOGIC_VECTOR;
+ justified : SIDE := right;
+ field : width := 0
+ ) return STRING is
+ constant ne : INTEGER := (value'length+3)/4;
+ variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
+ variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
+ variable result : STRING(1 to ne);
+ variable quad : STD_LOGIC_VECTOR(0 to 3);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ if value (value'left) = 'Z' then
+ pad := (others => 'Z');
+ else
+ pad := (others => '0');
+ end if;
+ ivalue := pad & value;
+ for i in 0 to ne-1 loop
+ quad := To_X01Z(ivalue(4*i to 4*i+3));
+ case quad is
+ when x"0" => result(i+1) := '0';
+ when x"1" => result(i+1) := '1';
+ when x"2" => result(i+1) := '2';
+ when x"3" => result(i+1) := '3';
+ when x"4" => result(i+1) := '4';
+ when x"5" => result(i+1) := '5';
+ when x"6" => result(i+1) := '6';
+ when x"7" => result(i+1) := '7';
+ when x"8" => result(i+1) := '8';
+ when x"9" => result(i+1) := '9';
+ when x"A" => result(i+1) := 'A';
+ when x"B" => result(i+1) := 'B';
+ when x"C" => result(i+1) := 'C';
+ when x"D" => result(i+1) := 'D';
+ when x"E" => result(i+1) := 'E';
+ when x"F" => result(i+1) := 'F';
+ when "ZZZZ" => result(i+1) := 'Z';
+ when others => result(i+1) := 'X';
+ end case;
+ end loop;
+ return justify(result, justified, field);
+ end if;
+ end function to_hstring;
+ -- %%% End remove here
+
+ function to_string (
+ value : ufixed;
+ justified : SIDE := right;
+ field : width := 0
+ ) return STRING is
+ variable s : STRING(1 to value'length +1) := (others => ' ');
+ variable sindx : INTEGER;
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ if value'high < 0 then
+ return to_string (resize (value, 0, value'low), justified, field);
+ elsif value'low > 0 then
+ return to_string (resize (value, value'high, -1), justified, field);
+ else
+ sindx := 1;
+ for i in value'high downto value'low loop
+ if i = -1 then
+ s(sindx) := '.';
+ sindx := sindx +1;
+ end if;
+ s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
+ sindx := sindx +1;
+ end loop;
+ return justify(s, justified, field);
+ end if;
+ end if;
+ end function to_string;
+
+ function to_string (
+ value : sfixed;
+ justified : SIDE := right;
+ field : width := 0
+ ) return STRING is
+ variable s : STRING(1 to value'length +1) := (others => ' ');
+ variable sindx : INTEGER;
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ if value'high < 0 then
+ return to_string (resize (value, 0, value'low), justified, field);
+ elsif value'low > 0 then
+ return to_string (resize (value, value'high, -1), justified, field);
+ else
+ sindx := 1;
+ for i in value'high downto value'low loop
+ if i = -1 then
+ s(sindx) := '.';
+ sindx := sindx +1;
+ end if;
+ s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
+ sindx := sindx +1;
+ end loop;
+ return justify(s, justified, field);
+ end if;
+ end if;
+ end function to_string;
+
+ function to_ostring (
+ value : ufixed;
+ justified : SIDE := right;
+ field : width := 0
+ ) return STRING is
+ constant lne : INTEGER := (-VALUE'low+2)/3;
+ constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
+ (others => '0');
+ variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ if value'high < 0 then
+ return to_ostring (resize (value, 2, value'low), justified, field);
+ elsif value'low > 0 then
+ return to_ostring (resize (value, value'high, -3), justified, field);
+ else
+ slv := to_slv (value);
+ return justify(to_ostring(slv(slv'high downto slv'high-VALUE'high))
+ & "."
+ & to_ostring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
+ justified, field);
+ end if;
+ end if;
+ end function to_ostring;
+
+ function to_hstring (
+ value : ufixed;
+ justified : SIDE := right;
+ field : width := 0
+ ) return STRING is
+ constant lne : INTEGER := (-VALUE'low+3)/4;
+ constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
+ (others => '0');
+ variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ if value'high < 0 then
+ return to_hstring (resize (value, 3, value'low), justified, field);
+ elsif value'low > 0 then
+ return to_hstring (resize (value, value'high, -4), justified, field);
+ else
+ slv := to_slv (value);
+ return justify(to_hstring(slv(slv'high downto slv'high-VALUE'high))
+ & "."
+ & to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
+ justified, field);
+ end if;
+ end if;
+ end function to_hstring;
+
+ function to_ostring (
+ value : sfixed;
+ justified : SIDE := right;
+ field : width := 0
+ ) return STRING is
+ constant ne : INTEGER := ((value'high+1)+2)/3;
+ variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
+ constant lne : INTEGER := (-VALUE'low+2)/3;
+ constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
+ (others => '0');
+ variable slv : STD_LOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ pad := (others => value(value'high));
+ if value'high < 0 then
+ return to_ostring (resize (value, 2, value'low), justified, field);
+ elsif value'low > 0 then
+ return to_ostring (resize (value, value'high, -3), justified, field);
+ else
+ slv := to_slv (value);
+ return justify(to_ostring(pad
+ & slv(slv'high downto slv'high-VALUE'high))
+ & "."
+ & to_ostring(slv(slv'high-VALUE'high-1 downto 0)
+ & lpad),
+ justified, field);
+ end if;
+ end if;
+ end function to_ostring;
+
+ function to_hstring (
+ value : sfixed;
+ justified : SIDE := right;
+ field : width := 0
+ ) return STRING is
+ constant ne : INTEGER := ((value'high+1)+3)/4;
+ variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
+ constant lne : INTEGER := (-VALUE'low+3)/4;
+ constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
+ (others => '0');
+ variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
+ begin
+ if value'length < 1 then
+ return NUS;
+ else
+ pad := (others => value(value'high));
+ if value'high < 0 then
+ return to_hstring (resize (value, 3, value'low), justified, field);
+ elsif value'low > 0 then
+ return to_hstring (resize (value, value'high, -4), justified, field);
+ else
+ slv := to_slv (value);
+ return justify(to_hstring(pad&slv(slv'high downto slv'high-VALUE'high))
+ & "."
+ & to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
+ justified, field);
+ end if;
+ end if;
+ end function to_hstring;
+
+ -- From string functions allow you to convert a string into a fixed
+ -- point number. Example:
+ -- signal uf1 : ufixed (3 downto -3);
+ -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
+ -- The "." is optional in this syntax, however it exist and is
+ -- in the wrong location an error is produced. Overflow will
+ -- result in saturation.
+ function from_string (
+ bstring : STRING; -- binary string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed is
+ variable result : ufixed (left_index downto right_index);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(bstring);
+ read (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
+ return result;
+ end function from_string;
+
+ -- Octal and hex conversions work as follows:
+ -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
+ -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
+ function from_ostring (
+ ostring : STRING; -- Octal string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed is
+ variable result : ufixed (left_index downto right_index);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(ostring);
+ oread (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
+ return result;
+ end function from_ostring;
+
+ function from_hstring (
+ hstring : STRING; -- hex string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return ufixed is
+ variable result : ufixed (left_index downto right_index);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(hstring);
+ hread (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
+ return result;
+ end function from_hstring;
+
+ function from_string (
+ bstring : STRING; -- binary string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed is
+ variable result : sfixed (left_index downto right_index);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(bstring);
+ read (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
+ return result;
+ end function from_string;
+
+ function from_ostring (
+ ostring : STRING; -- Octal string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed is
+ variable result : sfixed (left_index downto right_index);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(ostring);
+ oread (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
+ return result;
+ end function from_ostring;
+
+ function from_hstring (
+ hstring : STRING; -- hex string
+ constant left_index : INTEGER;
+ constant right_index : INTEGER)
+ return sfixed is
+ variable result : sfixed (left_index downto right_index);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(hstring);
+ hread (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
+ return result;
+ end function from_hstring;
+
+ -- Same as above, "size_res" is used for it's range only.
+ function from_string (
+ bstring : STRING; -- binary string
+ size_res : ufixed)
+ return ufixed is
+ variable result : ufixed (size_res'high downto size_res'low);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(bstring);
+ read (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
+ return result;
+ end function from_string;
+
+ function from_ostring (
+ ostring : STRING; -- Octal string
+ size_res : ufixed)
+ return ufixed is
+ variable result : ufixed (size_res'high downto size_res'low);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(ostring);
+ oread (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
+ return result;
+ end function from_ostring;
+
+ function from_hstring (
+ hstring : STRING; -- hex string
+ size_res : ufixed)
+ return ufixed is
+ variable result : ufixed (size_res'high downto size_res'low);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(hstring);
+ hread (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
+ return result;
+ end function from_hstring;
+
+ function from_string (
+ bstring : STRING; -- binary string
+ size_res : sfixed)
+ return sfixed is
+ variable result : sfixed (size_res'high downto size_res'low);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(bstring);
+ read (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
+ return result;
+ end function from_string;
+
+ function from_ostring (
+ ostring : STRING; -- Octal string
+ size_res : sfixed)
+ return sfixed is
+ variable result : sfixed (size_res'high downto size_res'low);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(ostring);
+ oread (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
+ return result;
+ end function from_ostring;
+
+ function from_hstring (
+ hstring : STRING; -- hex string
+ size_res : sfixed)
+ return sfixed is
+ variable result : sfixed (size_res'high downto size_res'low);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ begin
+ L := new STRING'(hstring);
+ hread (L, result, good);
+ deallocate (L);
+ assert (good)
+ report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
+ return result;
+ end function from_hstring;
+
+ -- purpose: find a dot in a string, return -1 if no dot (internal function)
+ function finddot (
+ arg : STRING)
+ return INTEGER is
+ alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto
+ begin
+ for i in xarg'reverse_range loop
+ if (xarg(i) = '.') then
+ return i-1;
+ end if;
+ end loop;
+ return -1;
+ end function finddot;
+
+ -- Direct converstion functions. Example:
+ -- signal uf1 : ufixed (3 downto -3);
+ -- uf1 <= from_string ("0110.100"); -- 6.5
+ -- In this case the "." is not optional, and the size of
+ -- the output must match exactly.
+ function from_string (
+ bstring : STRING) -- binary string
+ return ufixed is
+ variable result : ufixed (bstring'length-2 downto 0);
+ variable result_nodot : ufixed (bstring'length-1 downto 0);
+ variable bstring_nodot : STRING (1 to bstring'length-1);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ variable dot, i, j : INTEGER;
+ begin
+ dot := finddot(bstring);
+ if (dot = -1) then
+ L := new STRING'(bstring);
+ read (L, result_nodot, good);
+ assert (good)
+ report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
+ deallocate (L);
+ return result_nodot;
+ else
+ j := 1;
+ for i in 1 to bstring'high loop
+ if (bstring(i) /= '.') then
+ bstring_nodot(j) := bstring(i); -- get rid of the dot.
+ j := j + 1;
+ end if;
+ end loop;
+ L := new STRING'(bstring_nodot);
+ read (L, result, good);
+ assert (good)
+ report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
+ deallocate (L);
+ return to_ufixed(to_slv(result), bstring'length-dot-2, -dot);
+ end if;
+ end function from_string;
+
+ -- Direct octal and hex converstion functions. In this case
+ -- the string lengths must match. Example:
+ -- signal sf1 := sfixed (5 downto -3);
+ -- sf1 <= from_ostring ("71.4") -- -6.5
+ function from_ostring (
+ ostring : STRING) -- Octal string
+ return ufixed is
+ variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
+ variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
+ variable ostring_nodot : STRING (1 to ostring'length-1);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ variable dot, i, j : INTEGER;
+ begin
+ dot := finddot(ostring);
+ if (dot = -1) then
+ L := new STRING'(ostring);
+ oread (L, result_nodot, good);
+ assert (good)
+ report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
+ deallocate (L);
+ return to_ufixed(UNSIGNED(result_nodot));
+ else
+ j := 1;
+ for i in 1 to ostring'high loop
+ if (ostring(i) /= '.') then
+ ostring_nodot(j) := ostring(i); -- get rid of the dot.
+ j := j + 1;
+ end if;
+ end loop;
+ L := new STRING'(ostring_nodot);
+ oread (L, result, good);
+ assert (good)
+ report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
+ deallocate (L);
+ return to_ufixed(result, (ostring'length-1-dot)*3-1, -dot*3);
+ end if;
+ end function from_ostring;
+
+ function from_hstring (
+ hstring : STRING) -- hex string
+ return ufixed is
+ variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
+ variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
+ variable hstring_nodot : STRING (1 to hstring'length-1);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ variable dot, i, j : INTEGER;
+ begin
+ dot := finddot(hstring);
+ if (dot = -1) then
+ L := new STRING'(hstring);
+ hread (L, result_nodot, good);
+ assert (good)
+ report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
+ deallocate (L);
+ return to_ufixed(UNSIGNED(result_nodot));
+ else
+ j := 1;
+ for i in 1 to hstring'high loop
+ if (hstring(i) /= '.') then
+ hstring_nodot(j) := hstring(i); -- get rid of the dot.
+ j := j + 1;
+ end if;
+ end loop;
+ L := new STRING'(hstring_nodot);
+ hread (L, result, good);
+ assert (good)
+ report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
+ deallocate (L);
+ return to_ufixed(result, (hstring'length-1-dot)*4-1, -dot*4);
+ end if;
+ end function from_hstring;
+
+ function from_string (
+ bstring : STRING) -- binary string
+ return sfixed is
+ variable result : sfixed (bstring'length-2 downto 0);
+ variable result_nodot : sfixed (bstring'length-1 downto 0);
+ variable bstring_nodot : STRING (1 to bstring'length-1);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ variable dot, i, j : INTEGER;
+ begin
+ dot := finddot(bstring);
+ if (dot = -1) then
+ L := new STRING'(bstring);
+ read (L, result_nodot, good);
+ assert (good)
+ report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
+ deallocate (L);
+ return result_nodot;
+ else
+ j := 1;
+ for i in 1 to bstring'high loop
+ if (bstring(i) /= '.') then
+ bstring_nodot(j) := bstring(i); -- get rid of the dot.
+ j := j + 1;
+ end if;
+ end loop;
+ L := new STRING'(bstring_nodot);
+ read (L, result, good);
+ assert (good)
+ report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
+ deallocate (L);
+ return to_sfixed(to_slv(result), bstring'length-dot-2, -dot);
+ end if;
+ end function from_string;
+
+ function from_ostring (
+ ostring : STRING) -- Octal string
+ return sfixed is
+ variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
+ variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
+ variable ostring_nodot : STRING (1 to ostring'length-1);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ variable dot, i, j : INTEGER;
+ begin
+ dot := finddot(ostring);
+ if (dot = -1) then
+ L := new STRING'(ostring);
+ oread (L, result_nodot, good);
+ assert (good)
+ report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
+ deallocate (L);
+ return to_sfixed(SIGNED(result_nodot));
+ else
+ j := 1;
+ for i in 1 to ostring'high loop
+ if (ostring(i) /= '.') then
+ ostring_nodot(j) := ostring(i); -- get rid of the dot.
+ j := j + 1;
+ end if;
+ end loop;
+ L := new STRING'(ostring_nodot);
+ oread (L, result, good);
+ assert (good)
+ report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
+ deallocate (L);
+ return to_sfixed(result, (ostring'length-1-dot)*3-1, -dot*3);
+ end if;
+ end function from_ostring;
+
+ function from_hstring (
+ hstring : STRING) -- hex string
+ return sfixed is
+ variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
+ variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
+ variable hstring_nodot : STRING (1 to hstring'length-1);
+ variable L : LINE;
+ variable good : BOOLEAN;
+ variable dot, i, j : INTEGER;
+ begin
+ dot := finddot(hstring);
+ if (dot = -1) then
+ L := new STRING'(hstring);
+ hread (L, result_nodot, good);
+ assert (good)
+ report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
+ deallocate (L);
+ return sfixed(SIGNED(result_nodot));
+ else
+ j := 1;
+ for i in 1 to hstring'high loop
+ if (hstring(i) /= '.') then
+ hstring_nodot(j) := hstring(i); -- get rid of the dot.
+ j := j + 1;
+ end if;
+ end loop;
+ L := new STRING'(hstring_nodot);
+ hread (L, result, good);
+ assert (good)
+ report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
+ deallocate (L);
+ return to_sfixed(result, (hstring'length-1-dot)*4-1, -dot*4);
+ end if;
+ end function from_hstring;
+
+-- synthesis translate_on
+-- rtl_synthesis on
+ function to_StdLogicVector (
+ arg : ufixed) -- fp vector
+ return STD_LOGIC_VECTOR is
+ begin
+ return to_slv (arg);
+ end function to_StdLogicVector;
+ function to_Std_Logic_Vector (
+ arg : ufixed) -- fp vector
+ return STD_LOGIC_VECTOR is
+ begin
+ return to_slv (arg);
+ end function to_Std_Logic_Vector;
+ function to_StdLogicVector (
+ arg : sfixed) -- fp vector
+ return STD_LOGIC_VECTOR is
+ begin
+ return to_slv (arg);
+ end function to_StdLogicVector;
+ function to_Std_Logic_Vector (
+ arg : sfixed) -- fp vector
+ return STD_LOGIC_VECTOR is
+ begin
+ return to_slv (arg);
+ end function to_Std_Logic_Vector;
+ function to_StdULogicVector (
+ arg : ufixed) -- fp vector
+ return STD_ULOGIC_VECTOR is
+ begin
+ return to_sulv (arg);
+ end function to_StdULogicVector;
+ function to_Std_ULogic_Vector (
+ arg : ufixed) -- fp vector
+ return STD_ULOGIC_VECTOR is
+ begin
+ return to_sulv (arg);
+ end function to_Std_ULogic_Vector;
+ function to_StdULogicVector (
+ arg : sfixed) -- fp vector
+ return STD_ULOGIC_VECTOR is
+ begin
+ return to_sulv (arg);
+ end function to_StdULogicVector;
+ function to_Std_ULogic_Vector (
+ arg : sfixed) -- fp vector
+ return STD_ULOGIC_VECTOR is
+ begin
+ return to_sulv (arg);
+ end function to_Std_ULogic_Vector;
+end package body fixed_pkg;
diff --git a/lib/fixed_ja/fixed_ja.vhd b/lib/fixed_ja/fixed_ja.vhd
new file mode 100644
index 0000000..bcd2700
--- /dev/null
+++ b/lib/fixed_ja/fixed_ja.vhd
@@ -0,0 +1,322 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+package fixed_ja is
+
+
+ type ufixed_t is array (integer range <>) of STD_LOGIC;
+ type sfixed_t is array (integer range <>) of STD_LOGIC;
+ type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
+ type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
+
+ type round_mode_t is (none, round_to_zero, round_pos_infinity, round_neg_infinity, round_half_up, round_half_down, round_nearest, round_convergent);
+ type saturate_mode_t is (none, saturate);
+
+ -- Declare functions and procedure
+
+ constant ASSERT_NO_WARN : boolean := false;
+ constant default_round_mode : round_mode_t := none;
+ constant default_saturate_mode : saturate_mode_t := none;
+
+ -- null array constants
+ constant NAUF : ufixed_t (0 downto 1) := (others => '0');
+ constant NASF : sfixed_t (0 downto 1) := (others => '0');
+ constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
+
+ -- Constructor helpers
+ -- Use: variable v8u2 : ufixed_t(ufixed(8,2)'range);
+ function uproto (nbits : integer; nbits_int : integer) return ufixed_t;
+
+ -- Use: variable v8s2 : sfixed_t(sfixed(8,2)'range);
+ function sproto (nbits : integer; nbits_int : integer) return sfixed_t;
+
+ function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t;
+ function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t;
+
+ -- Conversion Functions
+ function to_ufixed(src : ufixed_t) return ufixed_t;
+ function to_sfixed(src : sfixed_t) return sfixed_t;
+ function to_ufixed(src : sfixed_t) return ufixed_t;
+ function to_sfixed(src : ufixed_t) return sfixed_t;
+
+ function to_ufixed
+ (
+ src : ufixed_t;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t;
+
+ function to_ufixed
+ (
+ src : ufixed_t;
+ proto : ufixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t;
+
+ function to_sfixed
+ (
+ src : sfixed_t;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t;
+
+ function to_sfixed
+ (
+ src : sfixed_t;
+ proto : sfixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t;
+
+ -- fixed <= integer
+ function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t;
+ function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t;
+
+ -- fixed <= integer
+ function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t;
+ function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t;
+
+ -- ufixed <= unsigned
+ function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t;
+ function to_ufixed (src : unsigned; proto : ufixed_t) return ufixed_t;
+
+ -- sfixed <= signed
+ function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t;
+ function to_sfixed (src : signed; proto : sfixed_t) return sfixed_t;
+
+ -- fixed <= slv
+ function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t;
+ function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t;
+ function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t;
+ function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t;
+
+ -- ufixed <= real
+ function to_ufixed
+ (
+ src : real;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t;
+
+ function to_ufixed
+ (
+ src : real;
+ proto : ufixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t;
+
+ -- sfixed <= real
+ function to_sfixed
+ (
+ src : real;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t;
+
+ function to_sfixed
+ (
+ src : real;
+ proto : sfixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t;
+
+ -- Slicing functions for unconstrained array types
+ function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t;
+ function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t;
+
+ -- ufixed <= string
+ function to_ufixed (src : string) return ufixed_t;
+
+ -- sfixed <= string
+ function to_sfixed (src : string) return sfixed_t;
+
+ -- real <= ufixed
+ function to_real(src : ufixed_t) return real;
+
+ -- real <= sfixed
+ function to_real(src : sfixed_t) return real;
+
+ -- slv <= ufixed
+ function to_slv(src : ufixed_t) return std_logic_vector;
+
+ -- slv <= sfixed
+ function to_slv(src : sfixed_t) return std_logic_vector;
+
+ -- UNSIGNED <= ufixed
+ function to_unsigned (src : ufixed_t) return UNSIGNED;
+
+ -- SIGNED <= sfixed
+ function to_signed (src : sfixed_t) return SIGNED;
+
+ -- integer <= ufixed
+ function to_integer (src : ufixed_t) return integer;
+
+ -- integer <= sfixed
+ function to_integer (src : sfixed_t) return integer;
+
+ function to_string(src : ufixed_t) return string;
+ function to_string(src : sfixed_t) return string;
+ function to_string(src : std_logic_vector) return string;
+
+ -------------------------------------------------------------
+ -- Arithmetic shift left
+ -------------------------------------------------------------
+ function "sla" (src : ufixed_t; count : integer) return ufixed_t;
+ function "sla" (src : sfixed_t; count : integer) return sfixed_t;
+
+ -------------------------------------------------------------
+ -- Arithmetic shift right
+ -------------------------------------------------------------
+ function "sra" (src : ufixed_t; count : integer) return ufixed_t;
+ function "sra" (src : sfixed_t; count : integer) return sfixed_t;
+
+ -------------------------------------------------------------
+ -- Multiplication
+ -------------------------------------------------------------
+ function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t;
+ function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t;
+ function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t;
+ function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t;
+
+ -------------------------------------------------------------
+ -- Sum
+ -------------------------------------------------------------
+ function "+" (a : ufixed_t; b : integer) return ufixed_t;
+ function "+" (a : sfixed_t; b : integer) return sfixed_t;
+ function "+" (a : ufixed_t; b : unsigned) return ufixed_t;
+ function "+" (a : sfixed_t; b : signed) return sfixed_t;
+ function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t;
+ function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t;
+ function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t;
+ function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t;
+ function "+" (a : ufixed_t; b : std_logic) return ufixed_t;
+ function "+" (a : sfixed_t; b : std_logic) return sfixed_t;
+
+
+ -------------------------------------------------------------
+ -- Difference
+ -------------------------------------------------------------
+ function "-" (a : ufixed_t; b : integer) return ufixed_t;
+ function "-" (a : sfixed_t; b : integer) return sfixed_t;
+ function "-" (a : ufixed_t; b : unsigned) return ufixed_t;
+ function "-" (a : sfixed_t; b : signed) return sfixed_t;
+ function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t;
+ function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t;
+ function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t;
+ function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t;
+ function "-" (a : ufixed_t; b : std_logic) return ufixed_t;
+ function "-" (a : sfixed_t; b : std_logic) return sfixed_t;
+
+ -------------------------------------------------------------
+ -- Equality
+ -------------------------------------------------------------
+ function "=" (a : ufixed_t; b : ufixed_t) return boolean;
+ function "=" (a : sfixed_t; b : sfixed_t) return boolean;
+ function "=" (a : ufixed_t; b : sfixed_t) return boolean;
+ function "=" (a : sfixed_t; b : ufixed_t) return boolean;
+
+ -------------------------------------------------------------
+ -- Inequality
+ -------------------------------------------------------------
+ function "/=" (a : ufixed_t; b : ufixed_t) return boolean;
+ function "/=" (a : sfixed_t; b : sfixed_t) return boolean;
+ function "/=" (a : ufixed_t; b : sfixed_t) return boolean;
+ function "/=" (a : sfixed_t; b : ufixed_t) return boolean;
+
+ -------------------------------------------------------------
+ -- Less than
+ -------------------------------------------------------------
+ function "<" (a : ufixed_t; b : ufixed_t) return boolean;
+ function "<" (a : sfixed_t; b : sfixed_t) return boolean;
+ function "<" (a : ufixed_t; b : sfixed_t) return boolean;
+ function "<" (a : sfixed_t; b : ufixed_t) return boolean;
+
+ -------------------------------------------------------------
+ -- Greater than
+ -------------------------------------------------------------
+ function ">" (a : ufixed_t; b : ufixed_t) return boolean;
+ function ">" (a : sfixed_t; b : sfixed_t) return boolean;
+ function ">" (a : ufixed_t; b : sfixed_t) return boolean;
+ function ">" (a : sfixed_t; b : ufixed_t) return boolean;
+
+ -------------------------------------------------------------
+ -- Less or equal than
+ -------------------------------------------------------------
+ function "<=" (a : ufixed_t; b : ufixed_t) return boolean;
+ function "<=" (a : sfixed_t; b : sfixed_t) return boolean;
+ function "<=" (a : ufixed_t; b : sfixed_t) return boolean;
+ function "<=" (a : sfixed_t; b : ufixed_t) return boolean;
+
+ -------------------------------------------------------------
+ -- Greater or equal than
+ -------------------------------------------------------------
+ function ">=" (a : ufixed_t; b : ufixed_t) return boolean;
+ function ">=" (a : sfixed_t; b : sfixed_t) return boolean;
+ function ">=" (a : ufixed_t; b : sfixed_t) return boolean;
+ function ">=" (a : sfixed_t; b : ufixed_t) return boolean;
+
+ -------------------------------------------------------------
+ -- Unary Arithmetic Operators
+ -------------------------------------------------------------
+ function "abs" (src : sfixed_t) return sfixed_t;
+ function "-" (src : ufixed_t) return sfixed_t;
+ function "-" (src : sfixed_t) return sfixed_t;
+
+ -------------------------------------------------------------
+ -- Misc. Operators
+ -------------------------------------------------------------
+ function ipart (src : ufixed_t) return ufixed_t;
+ function fpart (src : ufixed_t) return ufixed_t;
+ function ipart (src : sfixed_t) return sfixed_t;
+ function fpart (src : sfixed_t) return sfixed_t;
+
+ -------------------------------------------------------------
+ -- Print function
+ -------------------------------------------------------------
+ procedure print_info(src : in ufixed_t; prefix : in string);
+ procedure print_info(src : in sfixed_t; prefix : in string);
+ procedure print_info(src : in string; prefix : in string);
+
+ -------------------------------------------------------------
+ -- Helpers
+ -------------------------------------------------------------
+ function cmsb(src : ufixed_t) return integer;
+ function clsb(src : ufixed_t) return integer;
+
+ function MIN (X, Y: INTEGER) return INTEGER;
+ function MAX (X, Y: INTEGER) return INTEGER;
+
+ function "MOD" (X, Y: in REAL ) return REAL;
+ function ipart(src : real) return real;
+ function fpart(src : real) return real;
+
+ function and_red(arg : ufixed_t) return STD_ULOGIC;
+ function nand_red(arg : ufixed_t) return STD_ULOGIC;
+ function or_red(arg : ufixed_t) return STD_ULOGIC;
+ function nor_red(arg : ufixed_t) return STD_ULOGIC;
+ function xor_red(arg : ufixed_t) return STD_ULOGIC;
+ function xnor_red(arg : ufixed_t) return STD_ULOGIC;
+ function and_red(arg : sfixed_t) return STD_ULOGIC;
+ function nand_red(arg : sfixed_t) return STD_ULOGIC;
+ function or_red(arg : sfixed_t) return STD_ULOGIC;
+ function nor_red(arg : sfixed_t) return STD_ULOGIC;
+ function xor_red(arg : sfixed_t) return STD_ULOGIC;
+ function xnor_red(arg : sfixed_t) return STD_ULOGIC;
+
+ --------------------------------------------------------------
+
+end; -- package fixed_ja;
+
diff --git a/lib/fixed_ja/fixed_ja_body.vhd b/lib/fixed_ja/fixed_ja_body.vhd
new file mode 100644
index 0000000..a85b626
--- /dev/null
+++ b/lib/fixed_ja/fixed_ja_body.vhd
@@ -0,0 +1,1921 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use std.textio.all;
+
+package body fixed_ja is
+
+ -------------------------------------------------------------
+ -- Local Procedures
+ -------------------------------------------------------------
+ -- adds 1 to the LSB of the number
+ procedure round_up
+ (
+ src : in ufixed_t;
+ result : out ufixed_t;
+ overflowx : out BOOLEAN ) is
+
+ variable srcuns, resuns : UNSIGNED (src'high-src'low+1 downto 0) := (others => '0');
+ begin -- round_up
+ srcuns (srcuns'high-1 downto 0) := to_unsigned (src);
+ resuns := srcuns + 1;
+
+ result := to_ufixed(resuns(src'high-src'low downto 0), src);
+ overflowx := (resuns(resuns'high) = '1');
+
+ end procedure round_up;
+
+ -------------------------------------------------------------
+ -- adds 1 to the LSB of the number
+ procedure round_up
+ (
+ src : in sfixed_t;
+ result : out sfixed_t;
+ overflowx : out BOOLEAN ) is
+
+ variable srcs, ress : SIGNED (src'high-src'low+1 downto 0);
+ begin -- round_up
+ srcs (srcs'high-1 downto 0) := to_signed (src);
+ srcs(srcs'high) := src(src'high); -- sign extend
+ ress := srcs + 1;
+
+ result := to_sfixed(ress (ress'high-1 downto 0), src);
+ overflowx := ((src(src'high) /= ress(ress'high-1)) and (or_red (sfixed_t(ress)) /= '0'));
+
+ end procedure round_up;
+
+ -------------------------------------------------------------
+ -- Local functions
+ -------------------------------------------------------------
+ -- round_fixed()
+-- function round_fixed
+-- (
+-- src : ufixed_t;
+-- remainder : ufixed_t;
+-- rnd_mode : round_mode_t := default_round_mode
+-- ) return ufixed_t is
+-- variable res : ufixed_t(src'range);
+-- begin
+-- return res;
+--
+-- end round_fixed;
+
+ -------------------------------------------------------------
+-- function round_fixed
+-- (
+-- src : sfixed_t;
+-- remainder : sfixed_t;
+-- rnd_mode : round_mode_t := default_round_mode
+-- ) return sfixed_t is
+-- variable res : signed(src'length-1 downto 0);
+-- begin
+-- return src;
+--
+-- end round_fixed;
+
+ -------------------------------------------------------------
+ function reshape
+ (
+ src : ufixed_t;
+ proto : ufixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t is
+
+ variable RemainLow : ufixed_t (proto'low-1 downto src'low) := (others => '0');
+ variable RemainHigh : ufixed_t (src'high downto proto'high+1) := (others => '0');
+ variable dst, tmp : ufixed_t (proto'high downto proto'low) := (others => '0');
+ variable ovf, isTruncLo, isTruncHi : boolean := false;
+ begin
+
+ if proto'high < -1 then
+ assert false report "U: reshape: Bad dual point (Upper bound < (-1))" severity error;
+ end if;
+
+ -- Check for high and low truncation
+ isTruncLo := (src'low < dst'low);
+ isTruncHi := (src'high > dst'high);
+
+ -- Reshape
+ dst := (others => '0');
+ dst(min(src'high, dst'high) downto max(src'low, dst'low)) := src(min(src'high, dst'high) downto max(src'low, dst'low));
+ tmp := dst;
+
+ -- Get low remainder
+ if isTruncLo then
+ RemainLow := src(RemainLow'range);
+ end if;
+
+ -- Get high remainder
+ if isTruncHi then
+ RemainHigh := src(RemainHigh'range);
+ end if;
+
+ ovf := false;
+
+ -- Rounding
+ if isTruncLo then
+
+ case rnd_mode is
+
+ -- Round to positive infinity (round ceiling)
+ when round_pos_infinity =>
+ if or_red(RemainLow) = '1' then
+ round_up(tmp, dst, ovf);
+ end if;
+
+ -- Round Half-up
+ -- Round nearest
+ when round_half_up | round_nearest =>
+ if (RemainLow(RemainLow'high) = '1') then
+ round_up(tmp, dst, ovf);
+ end if;
+
+ -- Round convergent
+ when round_convergent =>
+ if RemainLow(RemainLow'high) = '1' then
+ if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then
+ round_up(tmp, dst, ovf);
+ elsif tmp(dst'low) = '1' then
+ round_up(tmp, dst, ovf);
+ end if;
+ end if;
+
+ -- Round to zero
+ when round_to_zero | none => null;
+
+ when others =>
+ assert false report "Reshape(U): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error;
+
+ end case;
+ end if;
+
+ -- Saturating
+ if sat_mode = saturate then
+
+ -- Check overflow
+ if isTruncHi then
+ ovf := ovf or or_red(RemainHigh) = '1';
+ end if;
+
+ -- Saturate
+ if ovf then
+ dst := (others => '1');
+ end if;
+
+ end if;
+
+ return dst;
+
+ end reshape;
+
+ -------------------------------------------------------------
+ function reshape
+ (
+ src : ufixed_t;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t is
+
+ begin
+ return reshape(src, uproto(nbits, nbits_int), rnd_mode, sat_mode);
+
+ end reshape;
+
+ -------------------------------------------------------------
+ function reshape
+ (
+ src : sfixed_t;
+ proto : sfixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t is
+
+ variable RemainLow : sfixed_t (proto'low-1 downto src'low) := (others => '0');
+ variable RemainHigh : sfixed_t (src'high-1 downto proto'high) := (others => '0');
+ variable dst, tmp : sfixed_t (proto'high downto proto'low) := (others => '0');
+ variable ovf, isTruncLo, isTruncHi : boolean := false;
+ variable sign : std_logic;
+ begin
+
+ if proto'high < 0 then
+ assert false report "Reshape(S): Bad dual point (Upper bound < (0))" severity error;
+ end if;
+
+ -- Check for high and low truncation
+ isTruncLo := (src'low < dst'low);
+ isTruncHi := (src'high > dst'high);
+
+ -- Reshape
+ sign := src(src'high);
+ dst := (others => '0');
+ dst(dst'high downto max(src'low, dst'low)) := (dst'high downto min(src'high, dst'high) => sign) & src(min(src'high, dst'high)-1 downto max(src'low, dst'low));
+ tmp := dst;
+
+ -- Get low remainder
+ if isTruncLo then
+ RemainLow := src(RemainLow'range);
+ end if;
+
+ -- Get high remainder
+ if isTruncHi then
+ RemainHigh := src(RemainHigh'range);
+ end if;
+
+ ovf := false;
+
+ -- Rounding
+ if isTruncLo then
+
+ case rnd_mode is
+
+ -- Round to positive infinity (round ceiling)
+ when round_pos_infinity =>
+ round_up(tmp, dst, ovf);
+ if ovf then
+ dst(dst'high) := '0';
+ end if;
+
+ -- Round Half-up
+ when round_half_up =>
+ if RemainLow(RemainLow'high) = '1' then
+ round_up(tmp, dst, ovf);
+ end if;
+
+ -- Round nearest
+ when round_nearest =>
+ if RemainLow(RemainLow'high) = '1' then
+ if RemainLow'length = 1 then
+ if sign = '0' then
+ round_up(tmp, dst, ovf);
+ end if;
+ elsif sign = '0' or (sign and or_red(RemainLow(RemainLow'high-1 downto RemainLow'low))) = '1' then
+ round_up(tmp, dst, ovf);
+ end if;
+ end if;
+
+ -- Round convergent
+ when round_convergent =>
+ if RemainLow(RemainLow'high) = '1' then
+ if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then
+ round_up(tmp, dst, ovf);
+ elsif tmp(dst'low) = '1' then
+ round_up(tmp, dst, ovf);
+ end if;
+ end if;
+
+ -- Round to zero
+ when round_to_zero =>
+ if (or_red(RemainLow) = '1' and sign = '1') then
+ round_up(tmp, dst, ovf);
+ end if;
+
+ -- No Round
+ when none =>
+ -- Same as RoundToZero but overflow detection is omitted
+ dst := tmp + (or_red(RemainLow) and sign);
+
+ when others =>
+ assert false report "Reshape(S): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error;
+
+ end case;
+
+ -- Check negative zero
+ if dst(dst'high) = '1' then
+ if or_red(dst(dst'high-1 downto dst'low)) = '0' then
+ dst(dst'high) := '0';
+ -- assert false report "Reshape(S): -0 detected" severity note;
+ end if;
+ end if;
+ end if;
+
+ -- Saturating
+ if sat_mode = saturate then
+
+ -- Check overflow
+ if isTruncHi then
+ ovf := ovf or
+ (sign = '1' and src(dst'high) = '0' and or_red(tmp(dst'high-1 downto dst'low)) = '1') or
+ (sign = '1' and src(dst'high) = '1' and or_red(tmp(dst'high-1 downto dst'low)) = '0') or
+ (sign = '0' and or_red(RemainHigh) = '1');
+ end if;
+
+ -- Saturate
+ if ovf then
+ if (sign = '1') then
+ dst := '1' & (dst'high-1 downto dst'low+1 => '0') & '1';
+ else
+ dst := '0' & (dst'high-1 downto dst'low => '1');
+ end if;
+ end if;
+
+ end if;
+
+ return dst;
+
+ end reshape;
+
+ -------------------------------------------------------------
+ function reshape
+ (
+ src : sfixed_t;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t is
+
+ begin
+ return reshape(src, sproto(nbits, nbits_int), rnd_mode, sat_mode);
+
+ end reshape;
+
+ -------------------------------------------------------------
+ -- Constuctor helpers
+ -------------------------------------------------------------
+ function uproto (nbits : integer; nbits_int : integer) return ufixed_t is
+ constant result : ufixed_t (nbits_int-1 downto nbits_int-nbits) := (others => '0');
+ begin
+ return result(nbits_int-1 downto nbits_int-nbits);
+ end uproto;
+
+ -------------------------------------------------------------
+ function sproto (nbits : integer; nbits_int : integer) return sfixed_t is
+ constant result : sfixed_t (nbits_int downto nbits_int-nbits+1) := (others => '0');
+ begin
+ return result(nbits_int downto nbits_int-nbits+1);
+ end sproto;
+
+ -------------------------------------------------------------
+ function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t is
+ constant result : ufixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0');
+ variable hi, lo : integer := 0;
+
+ begin
+
+ case op is
+ when '+' =>
+ hi := max(a'high, b'high);
+ if a'high = b'high then
+ hi := hi + 1;
+ end if;
+ lo := min(a'low, b'low);
+
+ when '-' =>
+ hi := max(a'high, b'high);
+ lo := min(a'low, b'low);
+
+ when '*' =>
+ hi := a'high + b'high + 1;
+ if (a'high < 0 or b'high < 0) then
+ if (hi > -1) then
+ hi := hi-1;
+ end if;
+ end if;
+ lo := hi - a'length - b'length + 1;
+
+ when others => null;
+
+ end case;
+
+ return result(hi downto lo);
+ end uproto;
+
+ -------------------------------------------------------------
+ function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t is
+ constant result : sfixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0');
+ variable hi, lo : integer := 0;
+
+ begin
+
+ case op is
+ when '+' =>
+ hi := max(a'high, b'high);
+ if a'high = b'high then
+ hi := hi + 1;
+ end if;
+ lo := min(a'low, b'low);
+
+ when '-' =>
+ hi := max(a'high, b'high);
+ lo := min(a'low, b'low);
+
+ when '*' =>
+ hi := a'high + b'high;
+ if (a'high = 0 or b'high = 0) then
+ if (hi > 0) then
+ hi := hi-1;
+ end if;
+ end if;
+ lo := hi - a'length - b'length + 1;
+
+ when others => null;
+
+ end case;
+
+ return result(hi downto lo);
+ end sproto;
+
+ -------------------------------------------------------------
+ -- Type conversions
+ -------------------------------------------------------------
+ -- ufixed <= ufixed
+ function to_ufixed(src : ufixed_t) return ufixed_t is
+ begin
+ return to_ufixed(src, src);
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- ufixed <= sfixed
+ function to_ufixed(src : sfixed_t) return ufixed_t is
+ variable dst : ufixed_t(src'range) := (others => '0');
+ begin
+ dst := ufixed_t(abs(src));
+ return dst(src'high-1 downto src'low);
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= sfixed
+ function to_sfixed(src : sfixed_t) return sfixed_t is
+ begin
+ return src;
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= ufixed
+ function to_sfixed(src : ufixed_t) return sfixed_t is
+ variable dst : sfixed_t(src'high+1 downto src'low) := (others => '0');
+ begin
+ dst(src'range) := sfixed_t(src);
+ return dst;
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ -- ufixed <= ufixed
+ function to_ufixed
+ (
+ src : ufixed_t;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t is
+ begin
+ return reshape(src, nbits, nbits_int, rnd_mode, sat_mode);
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- ufixed <= ufixed
+ function to_ufixed
+ (
+ src : ufixed_t;
+ proto : ufixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t is
+ begin
+ return reshape(src, proto, rnd_mode, sat_mode);
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= sfixed
+ function to_sfixed
+ (
+ src : sfixed_t;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t is
+ begin
+ return reshape(src, nbits, nbits_int, rnd_mode, sat_mode);
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= sfixed
+ function to_sfixed
+ (
+ src : sfixed_t;
+ proto : sfixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t is
+ begin
+ return reshape(src, proto, rnd_mode, sat_mode);
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ -- ufixed <= integer
+ function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t is
+ begin
+ return to_ufixed(src, uproto(nbits, nbits_int));
+
+ end to_ufixed;
+
+ function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t is
+ begin
+ return to_ufixed(to_unsigned(src, proto'length), proto);
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- ufixed <= unsigned
+ function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t is
+ begin
+ return to_ufixed(src, uproto(nbits, nbits_int));
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- ufixed <= unsigned
+ function to_ufixed(src : unsigned; proto : ufixed_t) return ufixed_t is
+ variable dst : ufixed_t(proto'high downto proto'low) := (others => '0');
+ begin
+
+ dst(dst'low + min(dst'length, src'length)-1 downto dst'low) := ufixed_t(src(min(dst'length, src'length)-1 downto 0));
+
+ return dst;
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= integer
+ function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t is
+ begin
+ return to_sfixed(src, sproto(nbits, nbits_int));
+
+ end to_sfixed;
+
+ function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t is
+ begin
+
+ return to_sfixed(to_signed(src, proto'length), proto);
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= signed
+ function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t is
+ begin
+ return to_sfixed(src, sproto(nbits, nbits_int));
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= signed
+ function to_sfixed(src : signed; proto : sfixed_t) return sfixed_t is
+ variable dst : sfixed_t(proto'high downto proto'low) := (others => '0');
+ begin
+
+ dst(dst'low + min(dst'length, src'length)-2 downto dst'low) := sfixed_t(src(min(dst'length, src'length)-2 downto 0));
+ dst(dst'high) := src(src'high);
+
+ return dst;
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t is
+ variable result : ufixed_t (proto'left downto proto'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_ufixed (unsigned(src), proto);
+ return result;
+ end if;
+
+ end function to_ufixed;
+
+ -------------------------------------------------------------
+ function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t is
+ begin
+ return to_ufixed(src, uproto(nbits, nbits_int));
+
+ end function to_ufixed;
+
+ -------------------------------------------------------------
+ function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t is
+ variable result : sfixed_t (proto'left downto proto'right);
+ begin
+ if (result'length < 1) then
+ return result;
+ else
+ result := to_sfixed (signed(src), proto);
+ return result;
+ end if;
+
+ end function to_sfixed;
+
+ -------------------------------------------------------------
+ function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t is
+ begin
+ return to_sfixed(src, sproto(nbits, nbits_int));
+
+ end to_sfixed;
+ -------------------------------------------------------------
+
+ -- ufixed <= real
+ function to_ufixed
+ (
+ src : real;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t is
+
+ constant nbits_ext : integer := nbits + 1;
+ constant fix_hi : integer := nbits_int - 1;
+ constant fix_lo : integer := nbits_int - nbits_ext;
+
+ variable dst : ufixed_t (fix_hi downto fix_lo) := (others => '0');
+ variable i : integer := 0;
+ variable remain : real := 0.0;
+
+ begin
+
+ if (nbits_int < 0) then
+ assert false report "to_ufixed: Bad dual point (N integer bits < 0)" severity error;
+ end if;
+
+ if ((2.0**nbits_int - 1.0) < ipart(abs(src))) then
+-- assert ASSERT_NO_WARN report "to_ufixed: Overflow (" & REAL'image(src) & ") " severity warning;
+-- print_info(dst, "dst: ");
+ end if;
+
+ remain := abs(src);
+ for i in dst'range loop
+ if remain >= 2.0**i then
+ dst(i) := '1';
+ remain := remain - 2.0**i;
+ else
+ dst(i) := '0';
+ end if;
+ end loop;
+
+ return to_ufixed(dst, nbits, nbits_int, rnd_mode, sat_mode);
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= real
+ function to_sfixed
+ (
+ src : real;
+ proto : sfixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t is
+
+ variable utmp : ufixed_t(proto'high-1 downto proto'low) := (others => '0');
+ variable dst : sfixed_t(proto'high downto proto'low) := (others => '0');
+
+ begin
+ utmp := to_ufixed(src, utmp, rnd_mode, sat_mode);
+ if (src < 0.0) then
+ dst := -to_sfixed(utmp);
+ else
+ dst := to_sfixed(utmp);
+ end if;
+
+ return dst;
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ -- ufixed <= real
+ function to_ufixed
+ (
+ src : real;
+ proto : ufixed_t;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return ufixed_t is
+ begin
+ return to_ufixed(src, proto'length, proto'high+1, rnd_mode, sat_mode);
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= real
+ function to_sfixed
+ (
+ src : real;
+ nbits : integer;
+ nbits_int : integer;
+ rnd_mode : round_mode_t := default_round_mode;
+ sat_mode : saturate_mode_t := default_saturate_mode
+ ) return sfixed_t is
+ begin
+ return to_sfixed(src, sproto(nbits, nbits_int), rnd_mode, sat_mode);
+ end to_sfixed;
+
+ -------------------------------------------------------------------------------
+ -- ufixed <= ufixed_array(i)
+ function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t is
+ variable dst : ufixed_t(src'range(2));
+ begin
+ for j in src'range(2) loop
+ dst(j) := src(index, j);
+ end loop;
+
+ return dst;
+
+ end to_ufixed;
+
+ -------------------------------------------------------------------------------
+ -- sfixed <= sfixed_array(i)
+ function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t is
+ variable dst : sfixed_t(src'range(2));
+ begin
+ for j in src'range(2) loop
+ dst(j) := src(index, j);
+ end loop;
+
+ return dst;
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ -- ufixed <= string
+ function to_ufixed (src : string) return ufixed_t is
+
+ variable i, j, nbits, nbits_int, nbits_frac : integer := 0;
+ variable dst : unsigned(src'length downto 0) := (others => '0');
+ variable dp_found : boolean := false;
+ begin
+
+ for i in src'reverse_range loop
+ case src(i) is
+ when '.' =>
+ if dp_found then
+ assert false report "More than one DP not found." severity error;
+ else
+ dp_found := true;
+ nbits_frac := j;
+ end if;
+
+ when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1;
+ when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1;
+ when others =>
+ assert false report "Illegal character in binary string." severity error;
+
+ end case;
+
+ end loop ;
+ if not dp_found then
+ assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning;
+ end if;
+
+ nbits_int := nbits - nbits_frac;
+
+ return to_ufixed(dst(nbits-1 downto 0), nbits, nbits_int);
+
+ end to_ufixed;
+
+ -------------------------------------------------------------
+ -- sfixed <= string
+ function to_sfixed (src : string) return sfixed_t is
+
+ variable i, j, nbits, nbits_int, nbits_frac : integer := 0;
+ variable dst : signed(src'length downto 0) := (others => '0');
+ variable dp_found : boolean := false;
+ variable is_neg : boolean := false;
+ begin
+
+ is_neg := src(src'left) = '-';
+
+ for i in src'reverse_range loop
+ case src(i) is
+ when '-' => null;
+ when '+' => null;
+
+ when '.' =>
+ if dp_found then
+ assert false report "More than one DP not found." severity error;
+ else
+ dp_found := true;
+ nbits_frac := j;
+ end if;
+
+ when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1;
+ when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1;
+ when others =>
+ assert false report "Illegal character in binary string." severity error;
+ end case;
+ end loop ;
+ nbits := nbits + 1;
+
+ if not dp_found then
+ assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning;
+ end if;
+
+ nbits_int := nbits - nbits_frac-1;
+
+ if is_neg then
+ dst(nbits-1 downto 0) := -dst(nbits-1 downto 0);
+ end if;
+
+ return to_sfixed(dst(nbits-1 downto 0), nbits, nbits_int);
+
+ end to_sfixed;
+
+ -------------------------------------------------------------
+ function to_unsigned (src : ufixed_t) return UNSIGNED is
+ subtype t is UNSIGNED(src'high - src'low downto 0);
+ variable slv : t;
+ begin
+ slv := t(src);
+ return UNSIGNED(to_X01(std_logic_vector(slv)));
+
+ end function to_unsigned;
+
+ -------------------------------------------------------------
+ function to_signed (src : sfixed_t) return SIGNED is
+ subtype t is SIGNED(src'high - src'low downto 0);
+ variable slv : t;
+ begin
+ slv := t(src);
+ return SIGNED(to_X01(std_logic_vector(slv)));
+
+ end function to_signed;
+
+ -------------------------------------------------------------
+ -- integer <= ufixed
+ function to_integer (src : ufixed_t) return integer is
+ begin
+ return to_integer(to_unsigned(src));
+ end to_integer;
+
+ -------------------------------------------------------------
+ -- integer <= sfixed
+ function to_integer (src : sfixed_t) return integer is
+ begin
+ return to_integer(to_signed(src));
+ end to_integer;
+
+ -------------------------------------------------------------
+ -- to_real
+ function to_real(src : ufixed_t) return real is
+ variable dst : real := 0.0;
+ begin
+ for i in src'range loop
+ if (src(i) = '1') then
+ dst := dst + real(2.0**i);
+ end if;
+ end loop;
+ return dst;
+
+ end to_real;
+
+ -------------------------------------------------------------
+ function to_real(src : sfixed_t) return real is
+ variable dst : real := 0.0;
+ begin
+ dst := to_real(to_ufixed(src));
+
+ if (src(src'high) = '1') then
+ dst := -dst;
+ end if;
+
+ return dst;
+
+ end to_real;
+
+ -------------------------------------------------------------
+ -- to_slv
+ function to_slv (src : ufixed_t) return STD_LOGIC_VECTOR is
+ subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0);
+ variable slv : t;
+ begin
+ if src'length < 1 then
+ return NSLV;
+ end if;
+ slv := t (src);
+ return slv;
+
+ end function to_slv;
+
+ -------------------------------------------------------------
+ -- to_slv
+ function to_slv (src : sfixed_t) return STD_LOGIC_VECTOR is
+ subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0);
+ variable slv : t;
+ begin
+ if src'length < 1 then
+ return NSLV;
+ end if;
+ slv := t (src);
+ return slv;
+
+ end function to_slv;
+
+ -------------------------------------------------------------
+ function to_string(src : ufixed_t) return string is
+ variable str : string(src'length+1 downto 1) := (others => '0');
+ variable i, j : integer := 0;
+
+ begin
+ j := src'length+1;
+ for i in src'high downto 0 loop
+ if (src(i) = '1') then
+ str(j) := '1';
+ end if;
+ j := j - 1;
+ end loop;
+
+ str(j) := '.';
+ j := j - 1;
+
+ for i in -1 downto src'low loop
+ if (src(i) = '1') then
+ str(j) := '1';
+ end if;
+ j := j - 1;
+ end loop;
+
+ return str;
+
+ end to_string;
+
+ -------------------------------------------------------------
+ function to_string(src : sfixed_t) return string is
+ variable str : string(src'length+1 downto 1) := (others => '0');
+ variable i, j, start : integer := 0;
+ variable strlen : integer := 0;
+ variable src_abs : sfixed_t(src'range) := (others => '0');
+
+ begin
+ if (src'high < 0) then
+ assert false report "Illegal signed fix point number" severity error;
+ end if;
+
+ start := src'high;
+ strlen := src'length;
+
+ j := src'length+1;
+ if (src(start) = '1') then
+ str(j) := '-';
+ j := j - 1;
+ start := start - 1;
+ strlen := strlen + 1;
+ end if;
+
+ src_abs := abs(src);
+
+ for i in start downto 0 loop
+ if (src_abs(i) = '1') then
+ str(j) := '1';
+ end if;
+ j := j - 1;
+ end loop;
+
+ str(j) := '.';
+ j := j - 1;
+
+ for i in -1 downto src'low loop
+ if (src_abs(i) = '1') then
+ str(j) := '1';
+ end if;
+ j := j - 1;
+ end loop;
+
+ return str(strlen downto 1);
+
+ end to_string;
+
+ -------------------------------------------------------------
+ function to_string(src : std_logic_vector) return string is
+ variable str : string(src'length downto 1) := (others => '0');
+ variable i : integer := 0;
+
+ begin
+ for i in src'range loop
+ if (src(i) = '1') then
+ str(i+1) := '1';
+ end if;
+ end loop;
+
+ return str;
+
+ end to_string;
+
+ -------------------------------------------------------------
+ -- Binary Operators
+ -------------------------------------------------------------
+ function "sla" (src : ufixed_t; count : integer) return ufixed_t is
+ variable result : ufixed_t (src'high downto src'low) := (others => '0');
+
+ begin
+ if (count = 0) then
+ result := src;
+ elsif (count < 0) then
+ result := src sra -count;
+ elsif (count < src'length) then
+ result(src'high downto src'low) := src(src'high-count downto src'low) & (count-1 downto 0 => '0');
+ end if;
+ return result;
+
+ end "sla";
+
+ -------------------------------------------------------------
+ function "sla" (src : sfixed_t; count : integer) return sfixed_t is
+ variable result : sfixed_t (src'high downto src'low) := (others => '0');
+ variable sign : std_logic := '0';
+
+ begin
+ sign := src(src'high);
+ if (count = 0) then
+ result := src;
+ elsif (count < 0) then
+ result := src sra -count;
+ elsif (count < src'length-1) then
+ result(src'high downto src'low) := sign & src(src'high-count-1 downto src'low) & (count-1 downto 0 => '0');
+ end if;
+ return result;
+
+ end "sla";
+
+ -------------------------------------------------------------
+ function "sra" (src : ufixed_t; count : integer) return ufixed_t is
+ variable result : ufixed_t (src'high downto src'low) := (others => '0');
+
+ begin
+ if (count = 0) then
+ result := src;
+ elsif (count < 0) then
+ result := src sla -count;
+ elsif (count < src'length) then
+ result(src'high downto src'low) := (count-1 downto 0 => '0') & src(src'high downto src'low + count);
+ end if;
+ return result;
+
+ end "sra";
+
+ -------------------------------------------------------------
+ function "sra" (src : sfixed_t; count : integer) return sfixed_t is
+ variable result : sfixed_t (src'high downto src'low) := (others => '0');
+ variable res_slv, src_slv : signed (src'length-1 downto 0) := (others => '0');
+ variable sign, do_sub : std_logic := '0';
+
+ begin
+ src_slv := to_signed(src);
+ sign := src(src'high);
+ do_sub := src(src'high) and src(src'low);
+ if (count = 0) then
+ result := src;
+ elsif (count < 0) then
+ result := src sla -count;
+ elsif (count < src'length-1) then
+ res_slv := (count downto 0 => sign) & src_slv(src'length-2 downto count);
+ if (do_sub = '1') then
+ result(src'high downto src'low) := to_sfixed(res_slv+1, result);
+ else
+ result(src'high downto src'low) := to_sfixed(res_slv, result);
+ end if;
+ end if;
+ return result;
+
+ end "sra";
+
+ -------------------------------------------------------------
+ function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t is
+ variable result : ufixed_t (uproto(a,'*',b)'high downto uproto(a,'*',b)'low);
+
+ begin
+ if (a'high < 0 and b'high >= 0) or (a'high >= 0 and b'high < 0) then
+ result := to_ufixed(to_unsigned(a) * to_unsigned(b), result) sla 1;
+ else
+ result := to_ufixed(to_unsigned(a) * to_unsigned(b), result);
+ end if;
+ return result;
+
+ end "*";
+
+ -------------------------------------------------------------
+ function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t is
+ variable result : sfixed_t (sproto(a,'*',b)'high downto sproto(a,'*',b)'low);
+
+ begin
+ if (a'high = 0 and b'high > 0) or (a'high > 0 and b'high = 0) then
+ result := to_sfixed(signed(a) * signed(b), result) sla 2;
+ else
+ result := to_sfixed(signed(a) * signed(b), result) sla 1;
+ end if;
+ return result;
+
+ end "*";
+
+ -------------------------------------------------------------
+ function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t is
+
+ begin
+ return to_sfixed(a) * b;
+
+ end "*";
+
+ -------------------------------------------------------------
+ function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t is
+
+ begin
+ return b * a;
+
+ end "*";
+
+ -------------------------------------------------------------
+ function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t is
+ variable result : ufixed_t (uproto(a,'+',b)'high downto uproto(a,'+',b)'low);
+
+ begin
+ result := ufixed_t(unsigned(reshape(a, result)) + unsigned(reshape(b, result)));
+ return result;
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t is
+ variable result : sfixed_t (sproto(a,'+',b)'high downto sproto(a,'+',b)'low);
+
+ begin
+ result := to_sfixed(signed(reshape(a,result)) + signed(reshape(b,result)), result);
+-- result := to_sfixed(signed(a) + signed(b), result);
+ return result;
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t is
+
+ begin
+ return to_sfixed(a) + b;
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t is
+
+ begin
+ return b + a;
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : ufixed_t; b : unsigned) return ufixed_t is
+
+ begin
+
+ return ufixed_t(unsigned(a) + b);
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : sfixed_t; b : signed) return sfixed_t is
+
+ begin
+
+ return sfixed_t(signed(a) + b);
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : ufixed_t; b : integer) return ufixed_t is
+
+ begin
+
+ return ufixed_t(unsigned(a) + to_unsigned(b, a'length));
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : sfixed_t; b : integer) return sfixed_t is
+
+ begin
+
+ return sfixed_t(signed(a) + to_signed(b, a'length));
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : ufixed_t; b : std_logic) return ufixed_t is
+ variable result : ufixed_t (a'high downto a'low);
+ variable buns : unsigned(a'length-1 downto 0);
+
+ begin
+ buns := (a'length-1 downto 1 => '0') & b;
+ result := ufixed_t(to_unsigned(a) + buns);
+ return result;
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "+" (a : sfixed_t; b : std_logic) return sfixed_t is
+ variable result : sfixed_t (a'high downto a'low);
+ variable bs : signed(a'length-1 downto 0);
+
+ begin
+ bs := (a'length-1 downto 1 => '0') & b;
+ result := sfixed_t(to_signed(a) + bs);
+ return result;
+
+ end "+";
+
+ -------------------------------------------------------------
+ function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t is
+ variable result : ufixed_t (uproto(a,'-',b)'high downto uproto(a,'-',b)'low);
+ begin
+ result := to_ufixed(to_sfixed(a) - to_sfixed(b));
+ return result;
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t is
+ variable result : sfixed_t (sproto(a,'-',b)'high downto sproto(a,'-',b)'low);
+
+ begin
+ result := to_sfixed(signed(reshape(a,result)) - signed(reshape(b,result)), result);
+ return result;
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t is
+ begin
+ return to_sfixed(a) - b;
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t is
+
+ begin
+ return a - to_sfixed(b);
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : ufixed_t; b : unsigned) return ufixed_t is
+
+ begin
+ return ufixed_t(unsigned(a) - b);
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : sfixed_t; b : signed) return sfixed_t is
+
+ begin
+ return sfixed_t(signed(a) - b);
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : ufixed_t; b : integer) return ufixed_t is
+
+ begin
+
+ return ufixed_t(unsigned(a) - to_unsigned(b, a'length));
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : sfixed_t; b : integer) return sfixed_t is
+
+ begin
+
+ return sfixed_t(signed(a) - to_signed(b, a'length));
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : ufixed_t; b : std_logic) return ufixed_t is
+ variable result : ufixed_t (a'high downto a'low);
+ variable buns : unsigned(a'length-1 downto 0);
+
+ begin
+ buns := (a'length-1 downto 1 => '0') & b;
+ result := ufixed_t(unsigned(a) - buns);
+ return result;
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (a : sfixed_t; b : std_logic) return sfixed_t is
+ variable result : sfixed_t (a'high downto a'low);
+ variable bs : signed(a'length-1 downto 0);
+
+ begin
+ bs := (a'length-1 downto 1 => '0') & b;
+ result := sfixed_t(signed(a) - bs);
+ return result;
+
+ end "-";
+
+ -------------------------------------------------------------
+ -- Unary Operators
+ -------------------------------------------------------------
+ function "abs" (src : sfixed_t) return sfixed_t is
+ begin
+ return to_sfixed(abs(signed(src)), src);
+
+ end "abs";
+
+ -------------------------------------------------------------
+ function "-" (src : ufixed_t) return sfixed_t is
+ begin
+ return -to_sfixed(src);
+
+ end "-";
+
+ -------------------------------------------------------------
+ function "-" (src : sfixed_t) return sfixed_t is
+ begin
+ return to_sfixed(-signed(src), src);
+
+ end "-";
+
+ -------------------------------------------------------------
+ -- Binary Equality
+ -------------------------------------------------------------
+ function "=" (a : ufixed_t; b : ufixed_t) return boolean is
+ variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
+ begin
+ ta := (others => '0');
+ tb := (others => '0');
+ ta := to_ufixed(a, ta);
+ tb := to_ufixed(b, tb);
+ return to_unsigned(ta) = to_unsigned(tb);
+
+ end "=";
+
+ -------------------------------------------------------------
+ function "=" (a : sfixed_t; b : sfixed_t) return boolean is
+ variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
+ begin
+ ta := (others => '0');
+ tb := (others => '0');
+ ta := to_sfixed(a, ta);
+ tb := to_sfixed(b, tb);
+ return to_signed(ta) = to_signed(tb);
+
+ end "=";
+
+ -------------------------------------------------------------
+ function "=" (a : ufixed_t; b : sfixed_t) return boolean is
+ begin
+ return to_sfixed(a) = b;
+ end "=";
+
+ -------------------------------------------------------------
+ function "=" (a : sfixed_t; b : ufixed_t) return boolean is
+ begin
+ return b = a;
+ end "=";
+
+ -------------------------------------------------------------
+ -- Binary Inequality
+ -------------------------------------------------------------
+ function "/=" (a : ufixed_t; b : ufixed_t) return boolean is
+ begin
+ return not (a = b);
+
+ end "/=";
+
+ -------------------------------------------------------------
+ function "/=" (a : sfixed_t; b : sfixed_t) return boolean is
+ begin
+ return not (a = b);
+
+ end "/=";
+
+ -------------------------------------------------------------
+ function "/=" (a : ufixed_t; b : sfixed_t) return boolean is
+ begin
+ return not (a = b);
+ end "/=";
+
+ -------------------------------------------------------------
+ function "/=" (a : sfixed_t; b : ufixed_t) return boolean is
+ begin
+ return not (a = b);
+ end "/=";
+
+ -------------------------------------------------------------
+ -- Binary less than
+ -------------------------------------------------------------
+ function "<" (a : ufixed_t; b : ufixed_t) return boolean is
+ variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
+ begin
+ ta := (others => '0');
+ tb := (others => '0');
+ ta := to_ufixed(a, ta);
+ tb := to_ufixed(b, tb);
+ return to_unsigned(ta) < to_unsigned(tb);
+
+ end "<";
+
+ -------------------------------------------------------------
+ function "<" (a : sfixed_t; b : sfixed_t) return boolean is
+ variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
+ begin
+ ta := (others => '0');
+ tb := (others => '0');
+ ta := to_sfixed(a, ta);
+ tb := to_sfixed(b, tb);
+ return to_signed(ta) < to_signed(tb);
+
+ end "<";
+
+ -------------------------------------------------------------
+ function "<" (a : ufixed_t; b : sfixed_t) return boolean is
+ begin
+ return to_sfixed(a) < b;
+
+ end "<";
+
+ -------------------------------------------------------------
+ function "<" (a : sfixed_t; b : ufixed_t) return boolean is
+ begin
+ return a < to_sfixed(b);
+
+ end "<";
+
+ -------------------------------------------------------------
+ -- Binary greater than
+ -------------------------------------------------------------
+ function ">" (a : ufixed_t; b : ufixed_t) return boolean is
+ variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
+ begin
+ ta := (others => '0');
+ tb := (others => '0');
+ ta := to_ufixed(a, ta);
+ tb := to_ufixed(b, tb);
+ return to_unsigned(ta) > to_unsigned(tb);
+
+ end ">";
+
+ -------------------------------------------------------------
+ function ">" (a : sfixed_t; b : sfixed_t) return boolean is
+ variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
+ begin
+ ta := (others => '0');
+ tb := (others => '0');
+ ta := to_sfixed(a, ta);
+ tb := to_sfixed(b, tb);
+ return to_signed(ta) > to_signed(tb);
+
+ end ">";
+
+ -------------------------------------------------------------
+ function ">" (a : ufixed_t; b : sfixed_t) return boolean is
+ begin
+ return to_sfixed(a) > b;
+ end ">";
+
+ -------------------------------------------------------------
+ function ">" (a : sfixed_t; b : ufixed_t) return boolean is
+ begin
+ return a > to_sfixed(b);
+ end ">";
+
+ -------------------------------------------------------------
+ -- Binary less equal than
+ -------------------------------------------------------------
+ function "<=" (a : ufixed_t; b : ufixed_t) return boolean is
+ begin
+ return not (a > b);
+ end "<=";
+
+ function "<=" (a : sfixed_t; b : sfixed_t) return boolean is
+ begin
+ return not (a > b);
+ end "<=";
+
+ function "<=" (a : ufixed_t; b : sfixed_t) return boolean is
+ begin
+ return not (a > b);
+ end "<=";
+
+ function "<=" (a : sfixed_t; b : ufixed_t) return boolean is
+ begin
+ return not (a > b);
+ end "<=";
+
+ -------------------------------------------------------------
+ -- Binary greater or equal than
+ -------------------------------------------------------------
+ function ">=" (a : ufixed_t; b : ufixed_t) return boolean is
+ begin
+ return not (a < b);
+ end ">=";
+
+ function ">=" (a : sfixed_t; b : sfixed_t) return boolean is
+ begin
+ return not (a < b);
+ end ">=";
+
+ function ">=" (a : ufixed_t; b : sfixed_t) return boolean is
+ begin
+ return not (a < b);
+ end ">=";
+
+ function ">=" (a : sfixed_t; b : ufixed_t) return boolean is
+ begin
+ return not (a < b);
+ end ">=";
+
+ -------------------------------------------------------------
+ -- Misc. Operators
+ -------------------------------------------------------------
+ function ipart (src : ufixed_t) return ufixed_t is
+ begin
+ return src(src'high downto 0);
+ end ipart;
+
+ function fpart (src : ufixed_t) return ufixed_t is
+ begin
+ return src(-1 downto src'low);
+ end fpart;
+
+ function ipart (src : sfixed_t) return sfixed_t is
+ begin
+ return src(src'high-1 downto 0);
+ end ipart;
+
+ function fpart (src : sfixed_t) return sfixed_t is
+ begin
+ return src(-1 downto src'low);
+ end fpart;
+
+ -------------------------------------------------------------
+ -- Print functions
+ -------------------------------------------------------------
+ procedure print_info(src : in ufixed_t; prefix : in string) is
+ variable L : line;
+
+ begin
+ write (L, prefix & "'length = ");write (L, src'length);
+ writeline (output, L);
+
+ write (L, prefix & "'high(left) = ");
+ write (L, src'high);
+ write (L, '(');
+ write (L, src'left);
+ write (L, ')');
+ writeline (output, L);
+
+ write (L, prefix & "'low(right) = ");
+ write (L, src'low);
+ write (L, '(');
+ write (L, src'right);
+ write (L, ')');
+ writeline (output, L);
+
+ write (L, prefix & "'value = B");write (L, to_string(src));
+ writeline (output, L);
+
+ write (L, prefix & "'value = ");write (L, to_real(src));
+ writeline (output, L);
+
+ -- write (L, prefix & "'cmsb = ");write (L, cmsb(src));
+ -- writeline (output, L);
+
+ -- write (L, prefix & "'clsb = ");write (L, clsb(src));
+ -- writeline (output, L);
+
+ writeline (output, L);
+
+ end print_info;
+
+ -------------------------------------------------------------
+ procedure print_info(src : in sfixed_t; prefix : in string) is
+ variable L : line;
+
+ begin
+ write (L, prefix & "'length = ");write (L, src'length);
+ writeline (output, L);
+
+ write (L, prefix & "'high(left) = ");
+ write (L, src'high);
+ write (L, '(');
+ write (L, src'left);
+ write (L, ')');
+ writeline (output, L);
+
+ write (L, prefix & "'low(right) = ");
+ write (L, src'low);
+ write (L, '(');
+ write (L, src'right);
+ write (L, ')');
+ writeline (output, L);
+
+ write (L, prefix & "'value = B");write (L, to_string(src));
+ writeline (output, L);
+
+ write (L, prefix & "'value = ");write (L, to_real(src));
+ writeline (output, L);
+
+ -- write (L, prefix & "'cmsb = ");write (L, cmsb(src));
+ -- writeline (output, L);
+
+ -- write (L, prefix & "'clsb = ");write (L, clsb(src));
+ -- writeline (output, L);
+
+ writeline (output, L);
+
+ end print_info;
+
+ -------------------------------------------------------------
+ procedure print_info(src : in string; prefix : in string) is
+ variable L : line;
+
+ begin
+ write (L, prefix & "'length = ");write (L, src'length);
+ writeline (output, L);
+
+ write (L, prefix & "'high(left) = ");
+ write (L, src'high);
+ write (L, '(');
+ write (L, src'left);
+ write (L, ')');
+ writeline (output, L);
+
+ write (L, prefix & "'low(right) = ");
+ write (L, src'low);
+ write (L, '(');
+ write (L, src'right);
+ write (L, ')');
+ writeline (output, L);
+
+ writeline (output, L);
+
+ end print_info;
+
+ -------------------------------------------------------------
+ -- Helpers
+ -------------------------------------------------------------
+ -- Count significant bits for integer part
+ function cmsb(src : ufixed_t) return integer is
+ variable j, i : integer := src'high;
+ begin
+ for i in src'range loop
+ if src(i) = '1' then
+ exit;
+ end if;
+ j := j - 1;
+ end loop;
+
+ -- LRM nachlesen: hier is i=src'high re-initialisert
+
+ return j;
+
+ end cmsb;
+
+ -------------------------------------------------------------
+ -- Count significant bits for fractional part
+ function clsb(src : ufixed_t) return integer is
+ variable j, i : integer := src'low;
+ begin
+ for i in src'reverse_range loop
+ if src(i) = '1' then
+ exit;
+ end if;
+ j := j + 1;
+ end loop;
+
+ -- LRM nachlesen: hier is i=src'low re-initialisert
+
+ return j;
+
+ end clsb;
+
+ -------------------------------------------------------------
+ function MIN (X, Y: INTEGER) return INTEGER is
+ variable res : integer := X;
+ begin
+ if Y < X then
+ res := Y;
+ end if;
+
+ return res;
+
+ end MIN;
+
+ -------------------------------------------------------------
+ function MAX (X, Y: INTEGER) return INTEGER is
+ variable res : integer := X;
+ begin
+ if Y > X then
+ res := Y;
+ end if;
+
+ return res;
+
+ end MAX;
+
+ -------------------------------------------------------------
+ function "MOD" (X, Y: in REAL ) return REAL is
+ -- Description:
+ -- See function declaration in IEEE Std 1076.2-1996
+ -- Notes:
+ -- a) Returns 0.0 on error
+
+ variable XNEGATIVE : BOOLEAN := X < 0.0;
+ variable YNEGATIVE : BOOLEAN := Y < 0.0;
+ variable VALUE : REAL;
+ begin
+ -- Check validity of input arguments
+ if (Y = 0.0) then
+ assert FALSE
+ report "MOD(X, 0.0) is undefined"
+ severity ERROR;
+ return 0.0;
+ end if;
+
+ -- Compute value
+ if ( XNEGATIVE ) then
+ if ( YNEGATIVE ) then
+ VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+ else
+ VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+ end if;
+ else
+ if ( YNEGATIVE ) then
+ VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
+ else
+ VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
+ end if;
+ end if;
+
+ return VALUE;
+
+ end "MOD";
+
+ -------------------------------------------------------------
+ -- misc. conversion
+ function ipart(src : real) return real is
+ begin
+ return floor(src);
+
+ end ipart;
+
+ -------------------------------------------------------------
+ function fpart(src : real) return real is
+ begin
+ return src - floor(src);
+
+ end fpart;
+
+ -------------------------------------------------------------
+ function or_red (arg : STD_LOGIC_VECTOR)
+ return STD_LOGIC is
+ variable Upper, Lower : STD_LOGIC;
+ variable Half : INTEGER;
+ variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
+ variable Result : STD_LOGIC;
+ begin
+ if (arg'length < 1) then -- In the case of a NULL range
+ Result := '0';
+ else
+ BUS_int := to_ux01 (arg);
+ if (BUS_int'length = 1) then
+ Result := BUS_int (BUS_int'left);
+ elsif (BUS_int'length = 2) then
+ Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
+ else
+ Half := (BUS_int'length + 1) / 2 + BUS_int'right;
+ Upper := or_red (BUS_int (BUS_int'left downto Half));
+ Lower := or_red (BUS_int (Half - 1 downto BUS_int'right));
+ Result := Upper or Lower;
+ end if;
+ end if;
+ return Result;
+
+ end function or_red;
+
+ -------------------------------------------------------------
+ function and_red (arg : STD_LOGIC_VECTOR)
+ return STD_LOGIC is
+ variable Upper, Lower : STD_LOGIC;
+ variable Half : INTEGER;
+ variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
+ variable Result : STD_LOGIC;
+ begin
+ if (arg'length < 1) then -- In the case of a NULL range
+ Result := '1';
+ else
+ BUS_int := to_ux01 (arg);
+ if (BUS_int'length = 1) then
+ Result := BUS_int (BUS_int'left);
+ elsif (BUS_int'length = 2) then
+ Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
+ else
+ Half := (BUS_int'length + 1) / 2 + BUS_int'right;
+ Upper := and_red (BUS_int (BUS_int'left downto Half));
+ Lower := and_red (BUS_int (Half - 1 downto BUS_int'right));
+ Result := Upper and Lower;
+ end if;
+ end if;
+ return Result;
+
+ end function and_red;
+
+ -------------------------------------------------------------
+ function xor_red (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
+ variable Upper, Lower : STD_ULOGIC;
+ variable Half : INTEGER;
+ variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
+ variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
+ begin
+ if (arg'length >= 1) then
+ BUS_int := to_ux01 (arg);
+ if (BUS_int'length = 1) then
+ Result := BUS_int (BUS_int'left);
+ elsif (BUS_int'length = 2) then
+ Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
+ else
+ Half := (BUS_int'length + 1) / 2 + BUS_int'right;
+ Upper := xor_red (BUS_int (BUS_int'left downto Half));
+ Lower := xor_red (BUS_int (Half - 1 downto BUS_int'right));
+ Result := Upper xor Lower;
+ end if;
+ end if;
+ return Result;
+
+ end function xor_red;
+
+ -------------------------------------------------------------
+ -- Reduction operators, same as numeric_std functions
+ function and_red(arg : ufixed_t) return STD_ULOGIC is
+ begin
+ return and_red (to_slv(arg));
+ end function and_red;
+
+ function nand_red(arg : ufixed_t) return STD_ULOGIC is
+ begin
+ return not and_red (to_slv(arg));
+ end function nand_red;
+
+ function or_red(arg : ufixed_t) return STD_ULOGIC is
+ begin
+ return or_red (to_slv(arg));
+ end function or_red;
+
+ function nor_red(arg : ufixed_t) return STD_ULOGIC is
+ begin
+ return not or_red (to_slv(arg));
+ end function nor_red;
+
+ function xor_red(arg : ufixed_t) return STD_ULOGIC is
+ begin
+ return xor_red (to_slv(arg));
+ end function xor_red;
+
+ function xnor_red(arg : ufixed_t) return STD_ULOGIC is
+ begin
+ return not xor_red (to_slv(arg));
+ end function xnor_red;
+
+ function and_red(arg : sfixed_t) return STD_ULOGIC is
+ begin
+ return and_red (to_slv(arg));
+ end function and_red;
+
+ function nand_red(arg : sfixed_t) return STD_ULOGIC is
+ begin
+ return not and_red (to_slv(arg));
+ end function nand_red;
+
+ function or_red(arg : sfixed_t) return STD_ULOGIC is
+ begin
+ return or_red (to_slv(arg));
+ end function or_red;
+
+ function nor_red(arg : sfixed_t) return STD_ULOGIC is
+ begin
+ return not or_red (to_slv(arg));
+ end function nor_red;
+
+ function xor_red(arg : sfixed_t) return STD_ULOGIC is
+ begin
+ return xor_red (to_slv(arg));
+ end function xor_red;
+
+ function xnor_red(arg : sfixed_t) return STD_ULOGIC is
+ begin
+ return not xor_red (to_slv(arg));
+ end function xnor_red;
+
+ -------------------------------------------------------------
+
+end; -- package body fixed_ja;
diff --git a/lib/jasm/cg.inc.jsm b/lib/jasm/cg.inc.jsm
new file mode 100644
index 0000000..01c36c4
--- /dev/null
+++ b/lib/jasm/cg.inc.jsm
@@ -0,0 +1,72 @@
+; -------------------------------------------------
+; lcd.inc.jsm
+; -------------------------------------------------
+; needs xio-address equates for
+; reg_cg_char_addr: equ 0xXX ; RW
+; reg_cg_line_addr: equ 0xXX ; RW
+; reg_cg_data: equ 0xXX ; RW
+; reg_cg_ctrl: equ 0xXX ; WO
+
+; needs delay.inc.jsm
+
+; -------------------------------------------------
+cg_clr_line: push R0
+ mov R0, 2
+ xout (reg_cg_ctrl), R0
+ pop R0
+ ret
+
+; -------------------------------------------------
+cg_clr_screen: push R0
+ mov R0, 1
+ xout (reg_cg_ctrl), R0
+ pop R0
+ ret
+
+; -------------------------------------------------
+; R0 : char address
+; R1 : line address
+cg_set_addr: call cg_wait_rdy
+ xout (reg_cg_line_addr), R1
+ xout (reg_cg_char_addr), R0
+ ret
+
+; -------------------------------------------------
+; R0 : character
+cg_putchar: call cg_wait_rdy
+ xout (reg_cg_data), R0
+ ret
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_puts: push R0
+cg_p_lp: movx R0, (R1)
+ inc R1
+ tst R0
+ jz ex_cgp
+ call cg_putchar
+ jmp cg_p_lp
+ex_cgp: pop R0
+ ret
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_clr_puts: call cg_clr_line
+ call cg_puts
+ ret
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_puts_clr: call cg_puts
+ call cg_clr_line
+ ret
+
+; -------------------------------------------------
+cg_wait_rdy: push R0
+cg_wr_lp: xin R0, (reg_hwstat)
+ and R0, 0x02
+ jz cg_wr_lp
+ pop R0
+ ret
+
+; -------------------------------------------------
diff --git a/lib/jasm/cregs.inc.jsm b/lib/jasm/cregs.inc.jsm
new file mode 100644
index 0000000..06d39d9
--- /dev/null
+++ b/lib/jasm/cregs.inc.jsm
@@ -0,0 +1,7 @@
+; JCPU On-Chip register
+cpu_revision: equ 0x00 ; RO
+cpu_control: equ 0x01 ; R/W
+cpu_status: equ 0x02 ; RO
+cpu_int_ctrl: equ 0x03 ; RW
+cpu_cmem_high: equ 0x04 ; RW
+cpu_stack_high: equ 0x05 ; RW
diff --git a/lib/jasm/delays.inc.jsm b/lib/jasm/delays.inc.jsm
new file mode 100644
index 0000000..6f002ee
--- /dev/null
+++ b/lib/jasm/delays.inc.jsm
@@ -0,0 +1,64 @@
+; -------------------------------------------------
+; Delays
+; -------------------------------------------------
+delay1s: push R15
+ mov R15, 10
+loop1s: call delay100ms
+ dec R15
+ jnz loop1s
+ pop R15
+ ret
+
+delay100ms: push R15
+ mov R15, 10
+loop100ms: call delay10ms
+ dec R15
+ jnz loop100ms
+ pop R15
+ ret
+
+delay10ms: push R15
+ mov R15, 10
+loop10ms: call delay1ms
+ dec R15
+ jnz loop10ms
+ pop R15
+ ret
+
+delay1ms: push R15
+ mov R15, 10
+loop1ms: call delay100us
+ dec R15
+ jnz loop1ms
+ pop R15
+ ret
+
+delay100us: push R15
+ mov R15, 10
+loop100us: call delay10us
+ dec R15
+ jnz loop100us
+ pop R15
+ ret
+
+delay10us: push R15
+ mov R15, 99
+loop10us: nop
+ nop
+ nop
+ dec R15
+ jnz loop10us
+ pop R15
+ ret
+
+delay1us: push R15
+ mov R15, 9
+loop1us: nop
+ nop
+ nop
+ dec R15
+ jnz loop1us
+ pop R15
+ ret
+
+; -------------------------------------------------
diff --git a/lib/jasm/lcd.inc.jsm b/lib/jasm/lcd.inc.jsm
new file mode 100644
index 0000000..d2883fa
--- /dev/null
+++ b/lib/jasm/lcd.inc.jsm
@@ -0,0 +1,208 @@
+; -------------------------------------------------
+; lcd.inc.jsm
+; -------------------------------------------------
+; needs xmem-address definition for
+; - lcd_port (LCD-Base)
+
+; needs delay.inc.jsm
+
+; -------------------------------------------------
+lcd_cmd: equ 0x00
+lcd_rd: equ 0x20
+lcd_data: equ 0x40
+lcd_enable: equ 0x80
+
+LCD_CMD_Z1: equ 0x80
+LCD_CMD_Z2: equ 0xC0
+LCD_CMD_CLEAR: equ 0x01
+
+; -------------------------------------------------
+; Init LCD
+; -------------------------------------------------
+LCD_init: mov R2, 0x00
+ mov R0, 0x03
+ call _write_lcd
+ call delay10ms
+ mov R2, 0x00
+ mov R0, 0x03
+ call _write_lcd
+ call delay10ms
+
+ mov R2, 0x00
+ mov R0, 0x02
+ call _write_lcd
+ call delay1ms
+
+ ; 1. Function set: 4-Bit mode, two display lines
+ mov R0, 0x28
+ call LCD_writecmd
+
+ ; 2. Display on, no cursor
+ mov R0, 0x0C
+ call LCD_writecmd
+
+ ; 3. Cursor shift during write
+ mov R0, 0x06
+ call LCD_writecmd
+
+ ; 4. Display clear
+ mov R0, 0x01
+ call LCD_writecmd
+
+ ret
+
+; -------------------------------------------------
+; LCD_waitbsy
+; -------------------------------------------------
+LCD_waitbsy: push R0
+bsy_loop: call LCD_readstat
+ and R0, 0x80
+ jz ex_bsy
+ call delay1us
+ jmp bsy_loop
+ex_bsy: pop R0
+ ret
+
+; -------------------------------------------------
+; LCD_writecmd
+; -------------------------------------------------
+; R0 = cmd
+LCD_writeaddr:
+LCD_writecmd: push R2
+ mov R2, lcd_cmd
+ call LCD_write
+ pop R2
+ ret
+
+; -------------------------------------------------
+; LCD_putsx
+; -------------------------------------------------
+; R1 = address of null-terminated string in XMEM
+LCD_putsx: push R0
+putsx_loop: movx R0, (R1)
+ inc R1
+ tst R0
+ jz putsx_ex
+ call LCD_writechar
+ jmp putsx_loop
+putsx_ex: pop R0
+ ret
+
+; -------------------------------------------------
+; LCD_putsc
+; -------------------------------------------------
+; R1 = address of null-terminated string in CMEM
+LCD_putsc: push R0
+putsc_loop: movc R0, (R1)
+ inc R1
+ tst R0
+ jz putsc_ex
+ call LCD_writechar
+ jmp putsc_loop
+putsc_ex: pop R0
+ ret
+
+; -------------------------------------------------
+; LCD_writechar
+; -------------------------------------------------
+; R0 = char
+LCD_writedata:
+LCD_writechar: push R2
+ mov R2, lcd_data
+ call LCD_write
+ pop R2
+ ret
+
+; -------------------------------------------------
+; LCD_write
+; -------------------------------------------------
+; R0 = input
+; R2 = register
+LCD_write: call LCD_waitbsy
+ push R0
+ swap R0
+ call _write_lcd
+ pop R0
+ call _write_lcd
+ ret
+
+; -------------------------------------------------
+; LCD_readstat
+; -------------------------------------------------
+; R0 = status
+LCD_readstat: push R2
+ mov R2, lcd_cmd
+ call LCD_read
+ pop R2
+ ret
+
+; -------------------------------------------------
+; LCD_read
+; -------------------------------------------------
+; R0 = output
+; R2 = register
+LCD_read: call _read_lcd
+ swap R0
+ push R0
+ call _read_lcd
+ pop R2
+ or R0, R2
+ ret
+
+; -------------------------------------------------
+; _write
+; -------------------------------------------------
+; R0 = input
+_write_lcd: push R1
+
+ and R0, 0x0F
+ mov R1, R0
+ or R1, R2
+ xout (lcd_port), R1
+ call delay1us
+
+ mov R1, R0
+ or R1, R2
+ or R1, lcd_enable
+ xout (lcd_port), R1
+ call delay1us
+
+ mov R1, R0
+ or R1, R2
+ xout (lcd_port), R1
+ call delay1us
+
+ or R1, lcd_rd
+ xout (lcd_port), R1
+
+ pop R1
+ ret
+
+; -------------------------------------------------
+; _read
+; -------------------------------------------------
+; R0 = output
+_read_lcd: push R1
+
+ mov R1, lcd_rd
+ or R1, R2
+ xout (lcd_port), R1
+ call delay1us
+
+ mov R1, lcd_rd
+ or R1, R2
+ or R1, lcd_enable
+ xout (lcd_port), R1
+ call delay1us
+ xin R0, (lcd_port)
+ and R0, 0x0F
+
+ mov R1, lcd_rd
+ or R1, R2
+ xout (lcd_port), R1
+ call delay1us
+
+ pop R1
+ ret
+
+
\ No newline at end of file
diff --git a/lib/jasm/mul8x8.inc.jsm b/lib/jasm/mul8x8.inc.jsm
new file mode 100644
index 0000000..2f66e2a
--- /dev/null
+++ b/lib/jasm/mul8x8.inc.jsm
@@ -0,0 +1,42 @@
+; -------------------------------------------------
+; mul8x8.inc.jsm
+; -------------------------------------------------
+
+; -------------------------------------------------
+; Parameter:
+; R0 : operand 1
+; R1 : operand 2
+; Return:
+; R0 : product low
+; R1 : product high
+mul8x8: push R2
+ push R3
+ push R4
+
+ mov R4, R1
+ mov R1, 0
+ mov R2, 0
+ mov R3, 0
+
+loop1: cmp R4, 0x01
+ jeq ende1
+
+ shr R4
+ jnc next1
+
+ add R2, R0
+ addc R3, R1
+
+next1: shl R0
+ rolc R1
+ jmp loop1
+
+ende1: add R0, R2
+ addc R1, R3
+
+ pop R4
+ pop R3
+ pop R2
+ ret
+
+; -------------------------------------------------
diff --git a/lib/jasm/uart.inc.jsm b/lib/jasm/uart.inc.jsm
new file mode 100644
index 0000000..df557b1
--- /dev/null
+++ b/lib/jasm/uart.inc.jsm
@@ -0,0 +1,32 @@
+; -------------------------------------------------
+; uart.inc.jsm
+; -------------------------------------------------
+; needs xmem-address definition for
+; - uart_status (Status register)
+; - uart_data (Data register)
+
+; -------------------------------------------------
+; sout
+; -------------------------------------------------
+; R0 = input
+sout: push R1
+sout1: xin R1, (uart_status)
+ and R1, 0x02
+ jnz sout1
+ xout (uart_data), R0
+ pop R1
+ ret
+
+; -------------------------------------------------
+; sin
+; -------------------------------------------------
+; R0 = output
+sin: push R1
+sin1: xin R1, (uart_status)
+ and R1, 0x10
+ jz sin1
+ xin R0, (uart_data)
+ pop R1
+ ret
+
+; -------------------------------------------------
diff --git a/lib/jasm/utils.inc.jsm b/lib/jasm/utils.inc.jsm
new file mode 100644
index 0000000..f354d7c
--- /dev/null
+++ b/lib/jasm/utils.inc.jsm
@@ -0,0 +1,32 @@
+; -------------------------------------------------
+; utils.inc.jsm
+; -------------------------------------------------
+
+
+; -------------------------------------------------
+; Parameter
+; R0 : Bin value in lower nibble
+; Return
+; R0 : Hex character representing lower nibble
+nibble2hex: and R0, 0x0F
+ cmp R0, 0x0A
+ jlt isNum1
+ add R0, 0x07
+isNum1: add R0, 0x30
+ ret
+
+; -------------------------------------------------
+; Parameter
+; R0 : Bin value
+; Return
+; R0 : Hex character high
+; R1 : Hex character low
+bin2hex: push R0
+ call nibble2hex
+ mov R1, R0
+ pop R0
+ swap R0
+ call nibble2hex
+ ret
+
+; -------------------------------------------------
diff --git a/lib/misc/debounce.vhd b/lib/misc/debounce.vhd
new file mode 100644
index 0000000..79317a5
--- /dev/null
+++ b/lib/misc/debounce.vhd
@@ -0,0 +1,91 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:34:24 10/23/05
+-- Design Name:
+-- Module Name: debounce - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity debounce is
+ Generic ( ncyc_latency : integer := 100);
+ Port ( rst : in std_logic;
+ clk : in std_logic;
+ input : in std_logic;
+ output : out std_logic);
+end debounce;
+
+architecture Behavioral of debounce is
+
+type debounce_state_t is (init_st, wait_st, rel_st);
+signal debounce_cs : debounce_state_t;
+signal debounce_ns : debounce_state_t;
+signal count : integer range 0 to ncyc_latency;
+signal input_last : std_logic;
+
+begin
+
+ debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
+ begin
+ if (rst = '1') then
+ count <= 0;
+ output <= input;
+ input_last <= input;
+ else
+ if rising_edge(clk) then
+ debounce_cs <= debounce_ns;
+ if (debounce_cs = wait_st) then
+ if (count /= 0) then
+ count <= count - 1;
+ end if;
+ else
+ count <= ncyc_latency;
+ if (debounce_cs = rel_st) then
+ output <= input;
+ input_last <= input;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
+ begin
+ debounce_ns <= debounce_cs;
+ case debounce_cs is
+ when init_st =>
+ if (input /= input_last) then
+ debounce_ns <= wait_st;
+ end if;
+ when wait_st =>
+ if (count = 0) then
+ debounce_ns <= rel_st;
+ end if;
+ when others =>
+ debounce_ns <= init_st;
+ end case;
+ end process;
+
+end Behavioral;
diff --git a/lib/misc/debounce2.vhd b/lib/misc/debounce2.vhd
new file mode 100644
index 0000000..206a61c
--- /dev/null
+++ b/lib/misc/debounce2.vhd
@@ -0,0 +1,142 @@
+-------------------------------------------------
+-- Signal Debouncer
+-- Jeff Bazinet
+-- February 14, 2002
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+library lpm;
+use lpm.lpm_components.lpm_counter;
+
+
+entity debounce is
+ generic(BUFFER_WIDTH: positive:= 30;
+ CLOCK_DIV: positive:= 15
+ );
+ port( clock: in std_logic;
+ reset: in std_logic;
+ signal_in: in std_logic;
+ signal_out: out std_logic
+ );
+end entity debounce;
+
+
+architecture rtl of debounce is
+
+ ---------------------------------------------------------------
+ -- SIGNAL DECLARATION
+ ---------------------------------------------------------------
+
+ -- General
+ signal reset_n: std_logic;
+
+ -- SLOW CLOCK GENERATION
+ signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0);
+ signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1);
+ signal clock_slow: std_logic;
+ signal clock_slow_wire: std_logic;
+
+ -- DATA BUFFER FILL
+ signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
+ signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0);
+
+ -- CHECK FOR DEBOUNCE STABILITY
+ signal stable: std_logic;
+ signal stable_old: std_logic;
+ signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
+
+ -- PUSH BUTTON ENABLE
+ signal button_pushed: std_logic;
+
+ begin
+
+ ---------------------------------------------------------------
+ -- SLOW CLOCK GENERATION
+ ---------------------------------------------------------------
+
+ COUNTER_1: lpm_counter
+ generic map (lpm_width => CLOCK_DIV)
+ port map (
+ clock => clock,
+ sclr => reset_n,
+ cout => clock_slow_wire
+ );
+
+ process (clock) is
+ begin
+
+ clock_slow <= clock_slow_wire;
+
+ end process;
+
+ ---------------------------------------------------------------
+ -- DATA BUFFER FILL
+ ---------------------------------------------------------------
+
+ process (clock) is
+ begin
+
+ if (reset = '0') then
+ -- Initialization
+ data_buffer_reg <= (others => '1');
+ elsif rising_edge(clock_slow) then
+ data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
+ end if;
+
+ end process;
+
+ ---------------------------------------------------------------
+ -- CHECK FOR DEBOUNCE STABILITY
+ ---------------------------------------------------------------
+
+ process (clock) is
+ begin
+
+ if (reset = '0') then
+ -- Initialization
+ stable <= '0';
+ stable_old <= '0';
+ stable_state_reg <= (others => '0');
+ elsif rising_edge(clock) then
+ if (data_buffer_reg = stable_state_reg) then
+ stable <= '1';
+ stable_state_reg <= (others => '0');
+ else
+ stable <= '0';
+ end if;
+ stable_old <= stable;
+ end if;
+
+ end process;
+
+ ---------------------------------------------------------------
+ -- PUSH BUTTON ENABLE
+ ---------------------------------------------------------------
+
+ process (clock) is
+ begin
+
+ if (reset = '0') then
+ -- Initialization
+ button_pushed <= '0';
+ elsif rising_edge(clock) then
+ if (stable_old = '0' and stable = '1') then
+ button_pushed <= '1';
+ else
+ button_pushed <= '0';
+ end if;
+ end if;
+
+ end process;
+
+ ---------------------------------------------------------------
+ ---------------------------------------------------------------
+
+ signal_out <= button_pushed;
+ reset_n <= not reset;
+
+end rtl;
diff --git a/lib/misc/dpram_1w1r.vhd b/lib/misc/dpram_1w1r.vhd
new file mode 100644
index 0000000..dee0972
--- /dev/null
+++ b/lib/misc/dpram_1w1r.vhd
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r is
+ Generic (
+ addr_width : integer := 3;
+ data_width : integer := 8
+ );
+ Port (
+ clka : in STD_LOGIC;
+ clkb : in STD_LOGIC;
+ en_a : in STD_LOGIC;
+ en_b : in STD_LOGIC;
+ we_a : in STD_LOGIC;
+ addr_a : in unsigned (addr_width-1 downto 0);
+ addr_b : in unsigned (addr_width-1 downto 0);
+ din_a : in unsigned (data_width-1 downto 0);
+ dout_b : out unsigned (data_width-1 downto 0)
+ );
+end dpram_1w1r;
+
+architecture Behavioral of dpram_1w1r is
+
+ constant depth : integer := 2**addr_width;
+ type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+ signal RAM : RAMtype;
+
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+ if en_a = '1' then
+ if we_a = '1' then
+ RAM(to_integer(addr_a)) <= din_a;
+ end if;
+ end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+ if en_b = '1' then
+ dout_b <= RAM(to_integer(addr_b));
+ end if;
+end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/lib/misc/dpram_1w1r_dist.vhd b/lib/misc/dpram_1w1r_dist.vhd
new file mode 100644
index 0000000..e07555c
--- /dev/null
+++ b/lib/misc/dpram_1w1r_dist.vhd
@@ -0,0 +1,84 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r_dist is
+ Generic
+ (
+ addr_width : integer := 3;
+ data_width : integer := 8
+ );
+ Port
+ (
+ clka : in STD_LOGIC;
+ clkb : in STD_LOGIC;
+ en_a : in STD_LOGIC;
+ en_b : in STD_LOGIC;
+ we_a : in STD_LOGIC;
+ addr_a : in unsigned (addr_width-1 downto 0);
+ addr_b : in unsigned (addr_width-1 downto 0);
+ din_a : in unsigned (data_width-1 downto 0);
+ dout_b : out unsigned (data_width-1 downto 0)
+ );
+end dpram_1w1r_dist;
+
+architecture Behavioral of dpram_1w1r_dist is
+
+ constant depth : integer := 2**addr_width;
+ type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+ signal RAM : RAMtype;
+
+ attribute ram_style : string;
+ attribute ram_style of RAM: signal is "distributed";
+
+begin
+
+process (clka)
+ begin
+ if clka'event and clka = '1' then
+ if en_a = '1' then
+ if we_a = '1' then
+ RAM(to_integer(addr_a)) <= din_a;
+ end if;
+ end if;
+ end if;
+end process;
+
+process (clkb)
+ begin
+ if clkb'event and clkb = '1' then
+ if en_b = '1' then
+ dout_b <= RAM(to_integer(addr_b));
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/lib/misc/dpram_2w2r.vhd b/lib/misc/dpram_2w2r.vhd
new file mode 100644
index 0000000..33152f3
--- /dev/null
+++ b/lib/misc/dpram_2w2r.vhd
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_2w2r is
+ Generic
+ (
+ addr_width : integer := 3;
+ data_width : integer := 8
+ );
+ Port
+ (
+ clk_a : in STD_LOGIC;
+ clk_b : in STD_LOGIC;
+ en_a : in STD_LOGIC;
+ en_b : in STD_LOGIC;
+ we_a : in STD_LOGIC;
+ we_b : in STD_LOGIC;
+ addr_a : in unsigned (addr_width-1 downto 0);
+ addr_b : in unsigned (addr_width-1 downto 0);
+ din_a : in unsigned (data_width-1 downto 0);
+ din_b : in unsigned (data_width-1 downto 0);
+ dout_a : out unsigned (data_width-1 downto 0);
+ dout_b : out unsigned (data_width-1 downto 0)
+ );
+end dpram_2w2r;
+
+architecture Behavioral of dpram_2w2r is
+
+ constant depth : integer := 2**addr_width;
+ type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+ shared variable RAM : RAMtype;
+
+begin
+
+process (clk_a)
+begin
+if clk_a'event and clk_a = '1' then
+ if en_a = '1' then
+ dout_a <= RAM(to_integer(addr_a));
+ if we_a = '1' then
+ RAM(to_integer(addr_a)) := din_a;
+ end if;
+ end if;
+end if;
+end process;
+
+process (clk_b)
+begin
+if clk_b'event and clk_b = '1' then
+ if en_b = '1' then
+ dout_b <= RAM(to_integer(addr_b));
+ if we_b = '1' then
+ RAM(to_integer(addr_b)) := din_b;
+ end if;
+ end if;
+end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/lib/misc/dpram_2w2r_virtex4.vhd b/lib/misc/dpram_2w2r_virtex4.vhd
new file mode 100644
index 0000000..6d8bc83
--- /dev/null
+++ b/lib/misc/dpram_2w2r_virtex4.vhd
@@ -0,0 +1,211 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r_virtex4.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity dpram_2w2r is
+ Generic
+ (
+ addr_width : integer := 3;
+ data_width : integer := 8
+ );
+ Port
+ (
+ clk_a : in STD_LOGIC;
+ clk_b : in STD_LOGIC;
+ en_a : in STD_LOGIC;
+ en_b : in STD_LOGIC;
+ we_a : in STD_LOGIC;
+ we_b : in STD_LOGIC;
+ addr_a : in unsigned (addr_width-1 downto 0);
+ addr_b : in unsigned (addr_width-1 downto 0);
+ din_a : in unsigned (data_width-1 downto 0);
+ din_b : in unsigned (data_width-1 downto 0);
+ dout_a : out unsigned (data_width-1 downto 0);
+ dout_b : out unsigned (data_width-1 downto 0)
+ );
+end dpram_2w2r;
+
+architecture Structure of dpram_2w2r is
+
+ signal do_a : std_logic_vector(31 downto 0);
+ signal do_b : std_logic_vector(31 downto 0);
+ signal di_a : std_logic_vector(31 downto 0);
+ signal di_b : std_logic_vector(31 downto 0);
+ signal ad_a : std_logic_vector(14 downto 0);
+ signal ad_b : std_logic_vector(14 downto 0);
+ signal wr_a : std_logic_vector(3 downto 0);
+ signal wr_b : std_logic_vector(3 downto 0);
+
+begin
+
+-- RAMB16: 16k+2k Parity Paramatizable block RAM
+-- Virtex-4
+-- Xilinx HDL Libraries Guide, version 9.1i
+RAMB16_inst : RAMB16
+generic map
+(
+ DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
+ DOB_REG => 0, -- Optional output registers on the B port (0 or 1)
+ INIT_A => X"000000000", -- Initial values on A output port
+ INIT_B => X"000000000", -- Initial values on B output port
+ INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE)
+ INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE)
+ RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
+ RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
+ READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
+ READ_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
+ SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
+
+ -- "GENERATE_X_ONLY" or "NONE"
+ SRVAL_A => X"000000000", -- Port A output value upon SSR assertion
+ SRVAL_B => X"000000000", -- Port B output value upon SSR assertion
+ WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
+ WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
+
+ -- The following INIT_xx declarations specify the initial contents of the RAM
+ INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+
+ -- The next set of INITP_xx are for the parity bits
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
+)
+port map
+(
+ CASCADEOUTA => open, -- 1-bit cascade output
+ CASCADEOUTB => open, -- 1-bit cascade output
+ DOA => do_a, -- 32-bit A port Data Output
+ DOB => do_b, -- 32-bit B port Data Output
+ DOPA => open, -- 4-bit A port Parity Output
+ DOPB => open, -- 4-bit B port Parity Output
+ ADDRA => ad_a, -- 15-bit A Port Address Input
+ ADDRB => ad_b, -- 15-bit B Port Address Input
+ CASCADEINA => '0', -- 1-bit cascade A input
+ CASCADEINB => '0', -- 1-bit cascade B input
+ CLKA => clk_a, -- Port A Clock
+ CLKB => clk_b, -- Port B Clock
+ DIA => di_a, -- 32-bit A port Data Input
+ DIB => di_b, -- 32-bit B port Data Input
+ DIPA => "0000", -- 4-bit A port parity Input
+ DIPB => "0000", -- 4-bit B port parity Input
+ ENA => en_a, -- 1-bit A port Enable Input
+ ENB => en_b, -- 1-bit B port Enable Input
+ REGCEA => '0', -- 1-bit A port register enable input
+ REGCEB => '0', -- 1-bit B port register enable input
+ SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input
+ SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input
+ WEA => wr_a, -- 4-bit A port Write Enable Input
+ WEB => wr_b -- 4-bit B port Write Enable Input
+);
+-- End of RAMB16_inst instantiation
+
+ dout_a <= unsigned(do_a(7 downto 0));
+ dout_b <= unsigned(do_b(7 downto 0));
+ di_a <= X"000000" & std_logic_vector(din_a);
+ di_b <= X"000000" & std_logic_vector(din_b);
+ ad_a <= '0' & std_logic_vector(addr_a) & "000";
+ ad_b <= '0' & std_logic_vector(addr_b) & "000";
+ wr_a <= (3 downto 0 => we_a);
+ wr_b <= (3 downto 0 => we_b);
+
+end Structure;
+
diff --git a/lib/misc/lcd_port.vhd b/lib/misc/lcd_port.vhd
new file mode 100644
index 0000000..11f97eb
--- /dev/null
+++ b/lib/misc/lcd_port.vhd
@@ -0,0 +1,69 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ ------------------------------------------------------------------
+entity lcd_port is
+ Port (
+ rst : in std_logic;
+ clk : in std_logic;
+ we : in std_logic;
+ din : in unsigned(7 downto 0);
+ dout : out unsigned(7 downto 0);
+ lcd_d : inout unsigned(3 downto 0);
+ lcd_e : out std_logic;
+ lcd_rs : out std_logic;
+ lcd_rw : out std_logic
+ );
+ end lcd_port;
+
+architecture Behavioral of lcd_port is
+
+ constant clcd_e : integer := 7;
+ constant clcd_rs : integer := 6;
+ constant clcd_rw : integer := 5;
+
+ type lcd_t is record
+ d : unsigned(3 downto 0);
+ e : std_logic;
+ rs : std_logic;
+ rw : std_logic;
+ end record;
+
+ ------------------------------------------------------------------
+ begin
+
+ proc_lcd_port:
+ process(rst, clk)
+ variable vlcd : lcd_t;
+ begin
+ if (rst = '1') then
+ dout <= (others => '0');
+ vlcd.d := (others => '0');
+ vlcd.e := '0';
+ vlcd.rw := '1';
+ vlcd.rs := '0';
+ elsif rising_edge(clk) then
+ dout <= unsigned("0000" & lcd_d);
+ if we = '1' then
+ vlcd.d := din(3 downto 0);
+ vlcd.e := din(clcd_e);
+ vlcd.rs := din(clcd_rs);
+ vlcd.rw := din(clcd_rw);
+ end if;
+ end if;
+ if vlcd.rw = '0' then
+ lcd_d <= unsigned(vlcd.d);
+ else
+ lcd_d <= (others => 'Z');
+ end if;
+ lcd_e <= vlcd.e;
+ lcd_rs <= vlcd.rs;
+ lcd_rw <= vlcd.rw;
+ end process;
+ ------------------------------------------------------------------
+
+end Behavioral;
diff --git a/lib/misc/oneshot.vhd b/lib/misc/oneshot.vhd
new file mode 100644
index 0000000..2f5d8bd
--- /dev/null
+++ b/lib/misc/oneshot.vhd
@@ -0,0 +1,223 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:52:19 10/22/05
+-- Design Name:
+-- Module Name: oneshot - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+-- Component Template
+--
+-- COMPONENT oneshot
+-- GENERIC (mode : integer);
+-- PORT(
+-- rst : IN std_logic;
+-- clk : IN std_logic;
+-- input : IN std_logic;
+-- output : OUT std_logic
+-- );
+-- END COMPONENT;
+--
+-- Instantation Template
+--
+-- oneshot_int: oneshot
+-- GENERIC MAP (
+-- mode => 1)
+-- PORT MAP(
+-- rst => ,
+-- clk => ,
+-- input => ,
+-- output =>
+-- );
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity oneshot is
+ Generic ( mode : integer range 0 to 2 := 1);
+ Port ( rst : in std_logic;
+ clk : in std_logic;
+ input : in std_logic;
+ output : out std_logic);
+end oneshot;
+
+architecture Behavioral of oneshot is
+
+type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
+
+signal shot_cs : shot_state_t;
+signal shot_ns : shot_state_t;
+
+begin
+
+mode_0:
+if mode = 0 generate
+begin
+ shot_clk: process(rst, clk, shot_ns, input)
+ begin
+ if (rst = '1') then
+ if (input = '1') then
+ shot_cs <= release_pos_st;
+ else
+ shot_cs <= release_neg_st;
+ end if;
+ else
+ if rising_edge(clk) then
+ shot_cs <= shot_ns;
+ end if;
+ end if;
+ end process;
+
+ shot_in: process(rst, clk, input, shot_cs)
+ begin
+ shot_ns <= shot_cs;
+ case shot_cs is
+ when release_pos_st =>
+ if (input = '0') then
+ shot_ns <= shot_neg_st;
+ end if;
+ when shot_neg_st =>
+ shot_ns <= release_neg_st;
+ when release_neg_st =>
+ if (input = '1') then
+ shot_ns <= release_pos_st;
+ end if;
+ when others => null;
+ end case;
+ end process;
+
+ shot_out: process(shot_cs)
+ begin
+ output <= '0';
+ case shot_cs is
+ when shot_pos_st =>
+ output <= '1';
+ when shot_neg_st =>
+ output <= '1';
+ when others => null;
+ end case;
+ end process;
+end generate;
+
+mode_1:
+if mode = 1 generate
+begin
+ shot_clk: process(rst, clk, shot_ns, input)
+ begin
+ if (rst = '1') then
+ if (input = '1') then
+ shot_cs <= release_pos_st;
+ else
+ shot_cs <= release_neg_st;
+ end if;
+ else
+ if rising_edge(clk) then
+ shot_cs <= shot_ns;
+ end if;
+ end if;
+ end process;
+
+ shot_in: process(rst, clk, input, shot_cs)
+ begin
+ shot_ns <= shot_cs;
+ case shot_cs is
+ when shot_pos_st =>
+ shot_ns <= release_pos_st;
+ when release_pos_st =>
+ if (input = '0') then
+ shot_ns <= release_neg_st;
+ end if;
+ when release_neg_st =>
+ if (input = '1') then
+ shot_ns <= shot_pos_st;
+ end if;
+ when others => null;
+ end case;
+ end process;
+
+ shot_out: process(shot_cs)
+ begin
+ output <= '0';
+ case shot_cs is
+ when shot_pos_st =>
+ output <= '1';
+ when shot_neg_st =>
+ output <= '1';
+ when others => null;
+ end case;
+ end process;
+end generate;
+
+mode_2:
+if mode = 2 generate
+begin
+ shot_clk: process(rst, clk, shot_ns, input)
+ begin
+ if (rst = '1') then
+ if (input = '1') then
+ shot_cs <= release_pos_st;
+ else
+ shot_cs <= release_neg_st;
+ end if;
+ else
+ if rising_edge(clk) then
+ shot_cs <= shot_ns;
+ end if;
+ end if;
+ end process;
+
+ shot_in: process(rst, clk, input, shot_cs)
+ begin
+ shot_ns <= shot_cs;
+ case shot_cs is
+ when shot_pos_st =>
+ shot_ns <= release_pos_st;
+ when release_pos_st =>
+ if (input = '0') then
+ shot_ns <= shot_neg_st;
+ end if;
+ when shot_neg_st =>
+ shot_ns <= release_neg_st;
+ when release_neg_st =>
+ if (input = '1') then
+ shot_ns <= shot_pos_st;
+ end if;
+ end case;
+ end process;
+
+ shot_out: process(shot_cs)
+ begin
+ output <= '0';
+ case shot_cs is
+ when shot_pos_st =>
+ output <= '1';
+ when shot_neg_st =>
+ output <= '1';
+ when others => null;
+ end case;
+ end process;
+end generate;
+
+
+
+end Behavioral;
diff --git a/lib/misc/pkg_template.vhd b/lib/misc/pkg_template.vhd
new file mode 100644
index 0000000..fe866e8
--- /dev/null
+++ b/lib/misc/pkg_template.vhd
@@ -0,0 +1,18 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package template_pkg is
+ -- Constants
+ -- Types
+ -- Functions
+
+end template_pkg;
+
+package body template_pkg is
+
+end template_pkg;
+
diff --git a/lib/misc/singleshot.vhd b/lib/misc/singleshot.vhd
new file mode 100644
index 0000000..25f7013
--- /dev/null
+++ b/lib/misc/singleshot.vhd
@@ -0,0 +1,155 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:52:19 10/22/05
+-- Design Name:
+-- Module Name: singleshot - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+-- Component Template
+--
+-- COMPONENT singleshot
+-- GENERIC (mode : integer);
+-- PORT(
+-- rst : IN std_logic;
+-- clk : IN std_logic;
+-- input : IN std_logic;
+-- output : OUT std_logic
+-- );
+-- END COMPONENT;
+--
+-- Instantation Template
+--
+-- singleshot_int: oneshot
+-- GENERIC MAP (
+-- mode => 1)
+-- PORT MAP(
+-- rst => ,
+-- clk => ,
+-- input => ,
+-- output =>
+-- );
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity singleshot is
+ Generic ( mode : integer range 0 to 2 := 1);
+ Port ( rst : in std_logic;
+ clk : in std_logic;
+ input : in std_logic;
+ output : out std_logic);
+end singleshot;
+
+architecture Behavioral of singleshot is
+
+type s_t is (idle, shot_in, active, shot_out);
+signal s, sn : s_t;
+
+begin
+
+process (rst, clk, sn)
+begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ s <= idle;
+ else
+ s <= sn;
+ end if;
+ end if;
+end process;
+
+mode_1:
+if mode = 1 generate
+begin
+ process (input, s)
+ begin
+ output <= '0';
+ sn <= s;
+ case s is
+ when idle =>
+ if input = '1' then
+ sn <= shot_in;
+ end if;
+ when shot_in =>
+ output <= '1';
+ sn <= active;
+ when active =>
+ if input = '0' then
+ sn <= shot_out;
+ end if;
+ when shot_out =>
+ sn <= idle;
+ when others => null;
+ end case;
+ end process;
+end generate;
+
+mode_0:
+if mode = 0 generate
+begin
+ process (input, s)
+ begin
+ output <= '0';
+ sn <= s;
+ case s is
+ when idle =>
+ if input = '1' then
+ sn <= shot_in;
+ end if;
+ when shot_in =>
+ sn <= active;
+ when active =>
+ if input = '0' then
+ sn <= shot_out;
+ end if;
+ when shot_out =>
+ output <= '1';
+ sn <= idle;
+ when others => null;
+ end case;
+ end process;
+end generate;
+
+mode_2:
+if mode = 2 generate
+begin
+ process (input, s)
+ begin
+ output <= '0';
+ sn <= s;
+ case s is
+ when idle =>
+ if input = '1' then
+ sn <= shot_in;
+ end if;
+ when shot_in =>
+ output <= '1';
+ sn <= active;
+ when active =>
+ if input = '0' then
+ sn <= shot_out;
+ end if;
+ when shot_out =>
+ output <= '1';
+ sn <= idle;
+ when others => null;
+ end case;
+ end process;
+end generate;
+
+end Behavioral;
diff --git a/lib/misc/tb_template.vhd b/lib/misc/tb_template.vhd
new file mode 100644
index 0000000..f96f294
--- /dev/null
+++ b/lib/misc/tb_template.vhd
@@ -0,0 +1,63 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_template IS
+END tb_template;
+
+ARCHITECTURE behavior OF tb_template IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT your_comp
+ GENERIC
+ (
+ );
+ PORT
+ (
+ );
+ END COMPONENT;
+
+ --Constants
+ constant PERIOD : time := 10 ns;
+
+ --Inputs
+ signal clk : STD_LOGIC := '0';
+
+ --Outputs
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: your_comp
+ GENERIC MAP
+ (
+ )
+ PORT MAP
+ (
+ );
+
+ tb_clk : PROCESS
+ BEGIN
+ clk <= not clk;
+ wait for PERIOD/2;
+ END PROCESS;
+
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 4*PERIOD;
+
+ assert false report "Test finished" severity error;
+ wait;
+
+ END PROCESS;
+
+END tb_template;
diff --git a/lib/misc/utils_pkg.vhd b/lib/misc/utils_pkg.vhd
new file mode 100644
index 0000000..2fcaec6
--- /dev/null
+++ b/lib/misc/utils_pkg.vhd
@@ -0,0 +1,63 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+
+package utils_pkg is
+
+ -- Constants
+
+ -- Functions
+ function NextPowerOfTwo(x : natural) return natural;
+ function NextExpBaseTwo(x : natural) return natural;
+ function GCD(a, b : natural) return natural;
+ function LCM(a, b : natural) return natural;
+
+end utils_pkg;
+
+
+package body utils_pkg is
+
+ function NextExpBaseTwo(x : natural) return natural is
+ begin
+ return natural(ceil(log2(real(x))));
+ end NextExpBaseTwo;
+
+ function NextPowerOfTwo(x : natural) return natural is
+ begin
+
+ return 2**NextExpBaseTwo(x);
+ end NextPowerOfTwo;
+
+ function GCD(a, b : natural) return natural is
+ variable aa : natural;
+ variable bb : natural;
+ begin
+ aa := a;
+ bb := b;
+ while bb /= 0 loop
+ if aa > bb then
+ aa := aa - bb;
+ else
+ bb := bb - aa;
+ end if;
+ end loop;
+
+ return aa;
+
+ end GCD;
+
+ function LCM(a, b : natural) return natural is
+ begin
+
+ return (a * b)/GCD(a, b);
+
+ end LCM;
+
+end utils_pkg;
+
+
diff --git a/lib/radio/mix/sim/tb_mix_cpx.fdo b/lib/radio/mix/sim/tb_mix_cpx.fdo
new file mode 100644
index 0000000..14d9422
--- /dev/null
+++ b/lib/radio/mix/sim/tb_mix_cpx.fdo
@@ -0,0 +1,13 @@
+vlib work
+vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd"
+vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit -93 "../src/mix_pkg.vhd"
+vcom -explicit -93 "../src/mix_cpx.vhd"
+vcom -explicit -93 "../src/tb_mix_cpx.vhd"
+vsim -t 1ps -lib work tb_mix_cpx
+do {tb_mix_cpx.wdo}
+view wave
+view structure
+view signals
+run 500ns
diff --git a/lib/radio/mix/sim/tb_mix_cpx.wdo b/lib/radio/mix/sim/tb_mix_cpx.wdo
new file mode 100644
index 0000000..c84c651
--- /dev/null
+++ b/lib/radio/mix/sim/tb_mix_cpx.wdo
@@ -0,0 +1,42 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mix_cpx/clk
+add wave -noupdate -format Logic /tb_mix_cpx/srst
+add wave -noupdate -divider {Fixed In}
+add wave -noupdate -format Logic /tb_mix_cpx/in_valid
+add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_re_in
+add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_im_in
+add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_re_in
+add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_im_in
+add wave -noupdate -divider {Fixed OUT}
+add wave -noupdate -format Logic /tb_mix_cpx/out_valid
+add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_re_out
+add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_im_out
+add wave -noupdate -divider {Convenient real out}
+add wave -noupdate -format Literal /tb_mix_cpx/x_re
+add wave -noupdate -format Literal /tb_mix_cpx/x_im
+add wave -noupdate -format Literal /tb_mix_cpx/y_re
+add wave -noupdate -format Literal /tb_mix_cpx/y_im
+add wave -noupdate -format Literal /tb_mix_cpx/z_re
+add wave -noupdate -format Literal /tb_mix_cpx/z_im
+add wave -noupdate -format Logic /tb_mix_cpx/fileout_enable
+add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_left
+add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_right
+add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_left
+add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_right
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {90000 ps} 0}
+configure wave -namecolwidth 193
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {348406 ps}
diff --git a/lib/radio/mix/sim/tb_mix_real.fdo b/lib/radio/mix/sim/tb_mix_real.fdo
new file mode 100644
index 0000000..cbf7dd0
--- /dev/null
+++ b/lib/radio/mix/sim/tb_mix_real.fdo
@@ -0,0 +1,13 @@
+vlib work
+vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd"
+vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit -93 "../src/mix_pkg.vhd"
+vcom -explicit -93 "../src/mix_real.vhd"
+vcom -explicit -93 "../src/tb_mix_real.vhd"
+vsim -t 1ps -lib work tb_mix_real
+do {tb_mix_real.wdo}
+view wave
+view structure
+view signals
+run 500ns
diff --git a/lib/radio/mix/sim/tb_mix_real.wdo b/lib/radio/mix/sim/tb_mix_real.wdo
new file mode 100644
index 0000000..6643ce3
--- /dev/null
+++ b/lib/radio/mix/sim/tb_mix_real.wdo
@@ -0,0 +1,36 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mix_real/clk
+add wave -noupdate -format Logic /tb_mix_real/srst
+add wave -noupdate -divider {Fixed In}
+add wave -noupdate -format Logic /tb_mix_real/in_valid
+add wave -noupdate -format Literal -radix decimal /tb_mix_real/x_re_din
+add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_re_din
+add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_im_din
+add wave -noupdate -divider {Fixed OUT}
+add wave -noupdate -format Logic /tb_mix_real/out_valid
+add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_re_dout
+add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_im_dout
+add wave -noupdate -divider {Convenient real out}
+add wave -noupdate -format Literal /tb_mix_real/x_re
+add wave -noupdate -format Literal /tb_mix_real/y_re
+add wave -noupdate -format Literal /tb_mix_real/y_im
+add wave -noupdate -format Literal /tb_mix_real/z_re
+add wave -noupdate -format Literal /tb_mix_real/z_im
+add wave -noupdate -format Logic /tb_mix_real/fileout_enable
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {120000 ps} 0}
+configure wave -namecolwidth 193
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {348406 ps}
diff --git a/lib/radio/mix/sim/tb_undc_real.fdo b/lib/radio/mix/sim/tb_undc_real.fdo
new file mode 100644
index 0000000..f7d989f
--- /dev/null
+++ b/lib/radio/mix/sim/tb_undc_real.fdo
@@ -0,0 +1,13 @@
+vlib work
+vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd"
+vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit -93 "../src/mix_pkg.vhd"
+vcom -explicit -93 "../src/undc_real.vhd"
+vcom -explicit -93 "../src/tb_undc_real.vhd"
+vsim -t 1ps -lib work tb_undc_real
+do {tb_undc_real.wdo}
+view wave
+view structure
+view signals
+run 500us
diff --git a/lib/radio/mix/sim/tb_undc_real.wdo b/lib/radio/mix/sim/tb_undc_real.wdo
new file mode 100644
index 0000000..f965905
--- /dev/null
+++ b/lib/radio/mix/sim/tb_undc_real.wdo
@@ -0,0 +1,38 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_undc_real/clk
+add wave -noupdate -format Logic /tb_undc_real/srst
+add wave -noupdate -format Logic /tb_undc_real/din_valid
+add wave -noupdate -format Logic /tb_undc_real/kin_valid
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/kin
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dc_out
+add wave -noupdate -format Logic /tb_undc_real/dout_valid
+add wave -noupdate -format Literal /tb_undc_real/k
+add wave -noupdate -format Literal /tb_undc_real/x
+add wave -noupdate -format Literal /tb_undc_real/y
+add wave -noupdate -format Literal /tb_undc_real/dc
+add wave -noupdate -divider UUT
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/k
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/x
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y1
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y2
+add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/dc
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {97905405 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {157500 ns}
diff --git a/lib/radio/mix/src/mix_cpx.vhd b/lib/radio/mix/src/mix_cpx.vhd
new file mode 100644
index 0000000..f77a312
--- /dev/null
+++ b/lib/radio/mix/src/mix_cpx.vhd
@@ -0,0 +1,166 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: mix_cpx - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.mix_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity mix_cpx is
+Generic
+(
+ nbits_in : integer := 12;
+ nbits_in_frac : integer := 12;
+ nbits_out : integer := 12;
+ nbits_out_frac : integer := 12;
+ nbits_scale_z : integer := 0;
+ has_in_reg : boolean := false;
+ has_pipe_reg : boolean := false;
+ has_out_reg : boolean := false;
+ rounding : boolean := true;
+ saturating : boolean := true
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ in_valid : in std_logic;
+ x_re_in : in sfixed;
+ x_im_in : in sfixed;
+ y_re_in : in sfixed;
+ y_im_in : in sfixed;
+ out_valid : out std_logic;
+ z_re_out : out sfixed;
+ z_im_out : out sfixed
+);
+end mix_cpx;
+
+architecture Behavioral of mix_cpx is
+constant nbits_prod : integer := nbits_out + nbits_scale_z;
+constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
+
+signal x_re, x_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+signal p_re_left, p_re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
+signal p_im_left, p_im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
+signal valid, p_valid : std_logic;
+------------------------------------------------------------
+begin
+
+
+------------------------------------------------------------
+ proc_in_reg: process(srst, clk, in_valid, x_re_in, x_im_in, y_re_in, y_im_in)
+ begin
+ if has_in_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ x_re <= to_sfixed(0, x_re);
+ x_im <= to_sfixed(0, x_im);
+ y_re <= to_sfixed(0, y_re);
+ y_im <= to_sfixed(0, y_im);
+ valid <= '0';
+ else
+ valid <= in_valid;
+ if in_valid = '1' then
+ x_re <= x_re_in;
+ x_im <= x_im_in;
+ y_re <= y_re_in;
+ y_im <= y_im_in;
+ end if;
+ end if;
+ end if;
+ else
+ x_re <= x_re_in;
+ x_im <= x_im_in;
+ y_re <= y_re_in;
+ y_im <= y_im_in;
+ valid <= in_valid;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_pipe_reg: process(srst, clk, valid, x_re, x_im, y_re, y_im)
+ variable re_left, re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
+ variable im_left, im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
+
+ begin
+ re_left := resize(x_re * y_re, re_left);
+ re_right := resize(x_im * y_im, re_right);
+ im_left := resize(x_re * y_im, im_left);
+ im_right := resize(x_im * y_re, im_right);
+ if has_pipe_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ p_re_left <= to_sfixed(0, p_re_left);
+ p_re_right <= to_sfixed(0, p_re_right);
+ p_im_left <= to_sfixed(0, p_im_left);
+ p_im_right <= to_sfixed(0, p_im_right);
+ p_valid <= '0';
+ else
+ p_re_left <= re_left;
+ p_re_right <= re_right;
+ p_im_left <= im_left;
+ p_im_right <= im_right;
+ p_valid <= valid;
+ end if;
+ end if;
+ else
+ p_re_left <= re_left;
+ p_re_right <= re_right;
+ p_im_left <= im_left;
+ p_im_right <= im_right;
+ p_valid <= valid;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_out_reg: process(srst, clk, p_valid, p_re_left, p_re_right, p_im_left, p_im_right)
+ variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ begin
+ sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, rounding, saturating);
+ sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, rounding, saturating);
+ if has_out_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ z_re_out <= to_sfixed(0, re);
+ z_im_out <= to_sfixed(0, im);
+ out_valid <= '0';
+ else
+ z_re_out <= sum_re;
+ z_im_out <= sum_im;
+ out_valid <= p_valid;
+ end if;
+ end if;
+ else
+ z_re_out <= re;
+ z_im_out <= im;
+ out_valid <= p_valid;
+ end if;
+ end process;
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/radio/mix/src/mix_pkg.vhd b/lib/radio/mix/src/mix_pkg.vhd
new file mode 100644
index 0000000..9e6dcbf
--- /dev/null
+++ b/lib/radio/mix/src/mix_pkg.vhd
@@ -0,0 +1,62 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.fixed_pkg.all;
+
+package mix_pkg is
+
+ -------------------------------------------------------------
+ -- Constructor helpers
+ -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
+ function uproto (nbits : integer; nbits_frac : integer) return ufixed;
+
+ -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
+ function sproto (nbits : integer; nbits_frac : integer) return sfixed;
+
+ function to_unsigned (src : ufixed) return UNSIGNED;
+ function to_signed (src : sfixed) return SIGNED;
+
+-------------------------------------------------------------------------------
+end; -- package mix_cpx_pkg;
+
+package body mix_pkg is
+
+ -------------------------------------------------------------
+ -- Constuctor helpers
+ function uproto (nbits : integer; nbits_frac : integer) return ufixed is
+ constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0');
+ begin
+ return result(nbits-nbits_frac-1 downto -nbits_frac);
+ end uproto;
+
+ -------------------------------------------------------------
+ function sproto (nbits : integer; nbits_frac : integer) return sfixed is
+ constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0');
+ begin
+ return result(nbits-nbits_frac downto -nbits_frac+1);
+ end sproto;
+
+ -------------------------------------------------------------
+ function to_unsigned (src : ufixed) return UNSIGNED is
+ subtype t is UNSIGNED(src'high - src'low downto 0);
+ variable slv : t;
+ begin
+ slv := t(src);
+ return UNSIGNED(to_X01(std_logic_vector(slv)));
+
+ end function to_unsigned;
+
+ -------------------------------------------------------------
+ function to_signed (src : sfixed) return SIGNED is
+ subtype t is SIGNED(src'high - src'low downto 0);
+ variable slv : t;
+ begin
+ slv := t(src);
+ return SIGNED(to_X01(std_logic_vector(slv)));
+
+ end function to_signed;
+
+
+-------------------------------------------------------------------------------
+end; -- package mix_pkg;
diff --git a/lib/radio/mix/src/mix_real.vhd b/lib/radio/mix/src/mix_real.vhd
new file mode 100644
index 0000000..3dfe3cc
--- /dev/null
+++ b/lib/radio/mix/src/mix_real.vhd
@@ -0,0 +1,155 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: mix_cpx - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.mix_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity mix_real is
+Generic
+(
+ nbits_in : integer := 12;
+ nbits_in_frac : integer := 12;
+ nbits_out : integer := 12;
+ nbits_out_frac : integer := 12;
+ nbits_scale_z : integer := 0;
+ has_in_reg : boolean := false;
+ has_pipe_reg : boolean := false;
+ has_out_reg : boolean := false;
+ rounding : boolean := true;
+ saturating : boolean := true
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ in_valid : in std_logic;
+ x_re_din : in sfixed;
+ y_re_din : in sfixed;
+ y_im_din : in sfixed;
+ out_valid : out std_logic;
+ z_re_dout : out sfixed;
+ z_im_dout : out sfixed
+);
+end mix_real;
+
+architecture Behavioral of mix_real is
+
+constant nbits_prod : integer := nbits_out + nbits_scale_z;
+constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
+
+signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
+signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
+signal valid, p_valid : std_logic;
+------------------------------------------------------------
+begin
+
+
+------------------------------------------------------------
+ proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din)
+ begin
+ if has_in_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ x_re <= to_sfixed(0, x_re);
+ y_re <= to_sfixed(0, y_re);
+ y_im <= to_sfixed(0, y_im);
+ valid <= '0';
+ else
+ valid <= in_valid;
+ if in_valid = '1' then
+ x_re <= x_re_din;
+ y_re <= y_re_din;
+ y_im <= y_im_din;
+ end if;
+ end if;
+ end if;
+ else
+ x_re <= x_re_din;
+ y_re <= y_re_din;
+ y_im <= y_im_din;
+ valid <= in_valid;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im)
+ variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
+ variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
+
+ begin
+ re_left := resize(x_re * y_re, re_left);
+ im_left := resize(x_re * y_im, im_left);
+ if has_pipe_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ p_re_left <= to_sfixed(0, p_re_left);
+ p_im_left <= to_sfixed(0, p_im_left);
+ p_valid <= '0';
+ else
+ p_re_left <= re_left;
+ p_im_left <= im_left;
+ p_valid <= valid;
+ end if;
+ end if;
+ else
+ p_re_left <= re_left;
+ p_im_left <= im_left;
+ p_valid <= valid;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left)
+ variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ begin
+ sum_re := resize(scalb(p_re_left, nbits_scale_z), re, rounding, saturating);
+ sum_im := resize(scalb(p_im_left, nbits_scale_z), im, rounding, saturating);
+ if has_out_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ z_re_dout <= to_sfixed(0, re);
+ z_im_dout <= to_sfixed(0, im);
+ out_valid <= '0';
+ else
+ z_re_dout <= sum_re;
+ z_im_dout <= sum_im;
+ out_valid <= p_valid;
+ end if;
+ end if;
+ else
+ z_re_dout <= re;
+ z_im_dout <= im;
+ out_valid <= p_valid;
+ end if;
+ end process;
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/radio/mix/src/tb_mix_cpx.vhd b/lib/radio/mix/src/tb_mix_cpx.vhd
new file mode 100644
index 0000000..7882185
--- /dev/null
+++ b/lib/radio/mix/src/tb_mix_cpx.vhd
@@ -0,0 +1,208 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:16:42 13.05.2007
+-- Design Name: tb_mix_cpx
+-- Module Name: tb_mix_cpx.vhd
+-- Project Name: mix_cpx
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; -- Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.mix_pkg.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_mix_cpx IS
+ Generic (
+ nbits_in : integer := 24;
+ nbits_in_frac : integer := 24;
+ nbits_out : integer := 24;
+ nbits_out_frac : integer := 24;
+ nbits_scale_z : integer := 0;
+ has_in_reg : boolean := true;
+ has_pipe_reg : boolean := true;
+ has_out_reg : boolean := true;
+ rounding : boolean := true;
+ saturating : boolean := true
+ );
+END tb_mix_cpx;
+
+ARCHITECTURE behavior OF tb_mix_cpx IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT mix_cpx
+ GENERIC
+ (
+ nbits_in : integer;
+ nbits_in_frac : integer;
+ nbits_out : integer;
+ nbits_out_frac : integer;
+ nbits_scale_z : integer;
+ has_in_reg : boolean;
+ has_pipe_reg : boolean;
+ has_out_reg : boolean;
+ rounding : boolean;
+ saturating : boolean
+ );
+ PORT
+ (
+ srst : in std_logic;
+ clk : in std_logic;
+ in_valid : in std_logic;
+ x_re_in : in sfixed;
+ x_im_in : in sfixed;
+ y_re_in : in sfixed;
+ y_im_in : in sfixed;
+ out_valid : out std_logic;
+ z_re_out : out sfixed;
+ z_im_out : out sfixed
+ );
+ END COMPONENT;
+
+ --Constants
+ constant PERIOD : time := 10 ns;
+
+
+ --Inputs
+ SIGNAL clk : std_logic := '0';
+ SIGNAL srst : std_logic := '1';
+ SIGNAL in_valid : std_logic := '0';
+ SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+ SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+ SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+ SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+
+ --Outputs
+ SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ SIGNAL out_valid : std_logic;
+
+ SIGNAL fileout_enable : std_logic := '0';
+ SIGNAL x_re : real := 0.0;
+ SIGNAL x_im : real := 0.0;
+ SIGNAL y_re : real := 0.0;
+ SIGNAL y_im : real := 0.0;
+ SIGNAL z_re : real := 0.0;
+ SIGNAL z_im : real := 0.0;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: mix_cpx
+ GENERIC MAP
+ (
+ nbits_in => nbits_in,
+ nbits_in_frac => nbits_in_frac,
+ nbits_out => nbits_out,
+ nbits_out_frac => nbits_out_frac,
+ nbits_scale_z => nbits_scale_z,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ rounding => rounding,
+ saturating => saturating
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => in_valid,
+ x_re_in => x_re_in,
+ x_im_in => x_im_in,
+ y_re_in => y_re_in,
+ y_im_in => y_im_in,
+ out_valid => out_valid,
+ z_re_out => z_re_out,
+ z_im_out => z_im_out
+ );
+
+ tb_clk : PROCESS
+ BEGIN
+ clk <= not clk;
+ wait for PERIOD/2;
+ END PROCESS;
+
+ tb : PROCESS
+
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 4*PERIOD;
+ srst <= '0';
+ ------------------------------------------
+ wait for 2*PERIOD;
+ wait until rising_edge(clk);
+ x_re_in <= to_sfixed(0.5, x_re_in);
+ x_im_in <= to_sfixed(0.5, x_im_in);
+ y_re_in <= to_sfixed(0.5, y_re_in);
+ y_im_in <= to_sfixed(0.5, y_im_in);
+ in_valid <= '1';
+ wait until rising_edge(clk);
+ in_valid <= '0';
+ wait for 5*PERIOD;
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_in <= to_sfixed(0.125, x_re_in);
+ x_im_in <= to_sfixed(0.25, x_im_in);
+ y_re_in <= to_sfixed(0.25, y_re_in);
+ y_im_in <= to_sfixed(0.125, y_im_in);
+ in_valid <= '1';
+ wait until rising_edge(clk);
+ in_valid <= '0';
+ wait for 5*PERIOD;
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_in <= to_sfixed(0.125, x_re_in);
+ x_im_in <= to_sfixed(-0.25, x_im_in);
+ y_re_in <= to_sfixed(0.25, y_re_in);
+ y_im_in <= to_sfixed(0.125, y_im_in);
+ in_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_in <= to_sfixed(0.125, x_re_in);
+ x_im_in <= to_sfixed(-0.25, x_im_in);
+ y_re_in <= to_sfixed(0.25, y_re_in);
+ y_im_in <= to_sfixed(0.125, y_im_in);
+ in_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_in <= to_sfixed(0.3, x_re_in);
+ x_im_in <= to_sfixed(0.0, x_im_in);
+ y_re_in <= to_sfixed(-0.5, y_re_in);
+ y_im_in <= to_sfixed(0.5, y_im_in);
+ in_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_in <= to_sfixed(0.0, x_re_in);
+ x_im_in <= to_sfixed(-0.7071, x_im_in);
+ y_re_in <= to_sfixed(0.0, y_re_in);
+ y_im_in <= to_sfixed(-0.7071, y_im_in);
+ in_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ in_valid <= '0';
+
+ wait for 20*PERIOD;
+
+ assert false report "Test finished" severity error;
+ wait;
+ END PROCESS;
+
+ x_re <= to_real(x_re_in);
+ x_im <= to_real(x_im_in);
+ y_re <= to_real(y_re_in);
+ y_im <= to_real(y_im_in);
+ z_re <= to_real(z_re_out);
+ z_im <= to_real(z_im_out);
+
+END;
diff --git a/lib/radio/mix/src/tb_mix_real.vhd b/lib/radio/mix/src/tb_mix_real.vhd
new file mode 100644
index 0000000..a9e458e
--- /dev/null
+++ b/lib/radio/mix/src/tb_mix_real.vhd
@@ -0,0 +1,197 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:16:42 13.05.2007
+-- Design Name: tb_mix_cpx
+-- Module Name: tb_mix_cpx.vhd
+-- Project Name: mix_cpx
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; -- Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.mix_pkg.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_mix_real IS
+ Generic (
+ nbits_in : integer := 24;
+ nbits_in_frac : integer := 24;
+ nbits_out : integer := 24;
+ nbits_out_frac : integer := 24;
+ nbits_scale_z : integer := 0;
+ has_in_reg : boolean := true;
+ has_pipe_reg : boolean := true;
+ has_out_reg : boolean := true;
+ rounding : boolean := true;
+ saturating : boolean := true
+ );
+END tb_mix_real;
+
+ARCHITECTURE behavior OF tb_mix_real IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT mix_real
+ GENERIC
+ (
+ nbits_in : integer;
+ nbits_in_frac : integer;
+ nbits_out : integer;
+ nbits_out_frac : integer;
+ nbits_scale_z : integer;
+ has_in_reg : boolean;
+ has_pipe_reg : boolean;
+ has_out_reg : boolean;
+ rounding : boolean;
+ saturating : boolean
+ );
+ PORT
+ (
+ srst : in std_logic;
+ clk : in std_logic;
+ in_valid : in std_logic;
+ x_re_din : in sfixed;
+ y_re_din : in sfixed;
+ y_im_din : in sfixed;
+ out_valid : out std_logic;
+ z_re_dout : out sfixed;
+ z_im_dout : out sfixed
+ );
+ END COMPONENT;
+
+ --Constants
+ constant PERIOD : time := 10 ns;
+
+
+ --Inputs
+ SIGNAL clk : std_logic := '0';
+ SIGNAL srst : std_logic := '1';
+ SIGNAL in_valid : std_logic := '0';
+ SIGNAL x_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+ SIGNAL y_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+ SIGNAL y_im_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
+
+ --Outputs
+ SIGNAL z_re_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ SIGNAL z_im_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
+ SIGNAL out_valid : std_logic;
+
+ SIGNAL fileout_enable : std_logic := '0';
+ SIGNAL x_re : real := 0.0;
+ SIGNAL y_re : real := 0.0;
+ SIGNAL y_im : real := 0.0;
+ SIGNAL z_re : real := 0.0;
+ SIGNAL z_im : real := 0.0;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: mix_real
+ GENERIC MAP
+ (
+ nbits_in => nbits_in,
+ nbits_in_frac => nbits_in_frac,
+ nbits_out => nbits_out,
+ nbits_out_frac => nbits_out_frac,
+ nbits_scale_z => nbits_scale_z,
+ has_in_reg => has_in_reg,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg,
+ rounding => rounding,
+ saturating => saturating
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ in_valid => in_valid,
+ x_re_din => x_re_din,
+ y_re_din => y_re_din,
+ y_im_din => y_im_din,
+ out_valid => out_valid,
+ z_re_dout => z_re_dout,
+ z_im_dout => z_im_dout
+ );
+
+ tb_clk : PROCESS
+ BEGIN
+ clk <= not clk;
+ wait for PERIOD/2;
+ END PROCESS;
+
+ tb : PROCESS
+
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 4*PERIOD;
+ srst <= '0';
+ ------------------------------------------
+ wait for 2*PERIOD;
+ wait until rising_edge(clk);
+ x_re_din <= to_sfixed(0.5, x_re_din);
+ y_re_din <= to_sfixed(0.5, y_re_din);
+ y_im_din <= to_sfixed(0.5, y_im_din);
+ in_valid <= '1';
+ wait until rising_edge(clk);
+ in_valid <= '0';
+ wait for 5*PERIOD;
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_din <= to_sfixed(0.125, x_re_din);
+ y_re_din <= to_sfixed(0.25, y_re_din);
+ y_im_din <= to_sfixed(0.125, y_im_din);
+ in_valid <= '1';
+ wait until rising_edge(clk);
+ in_valid <= '0';
+ wait for 5*PERIOD;
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_din <= to_sfixed(0.125, x_re_din);
+ y_re_din <= to_sfixed(0.25, y_re_din);
+ y_im_din <= to_sfixed(0.125, y_im_din);
+ in_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_din <= to_sfixed(0.125, x_re_din);
+ y_re_din <= to_sfixed(0.25, y_re_din);
+ y_im_din <= to_sfixed(0.125, y_im_din);
+ in_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_din <= to_sfixed(0.3, x_re_din);
+ y_re_din <= to_sfixed(-0.5, y_re_din);
+ y_im_din <= to_sfixed(0.5, y_im_din);
+ in_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ x_re_din <= to_sfixed(0.0, x_re_din);
+ y_re_din <= to_sfixed(0.0, y_re_din);
+ y_im_din <= to_sfixed(-0.7071, y_im_din);
+ in_valid <= '1';
+ ------------------------------------------
+ wait until rising_edge(clk);
+ in_valid <= '0';
+
+ wait for 20*PERIOD;
+
+ assert false report "Test finished" severity error;
+ wait;
+ END PROCESS;
+
+ x_re <= to_real(x_re_din);
+ y_re <= to_real(y_re_din);
+ y_im <= to_real(y_im_din);
+ z_re <= to_real(z_re_dout);
+ z_im <= to_real(z_im_dout);
+
+END;
diff --git a/lib/radio/mix/src/tb_undc_real.vhd b/lib/radio/mix/src/tb_undc_real.vhd
new file mode 100644
index 0000000..3c7a52f
--- /dev/null
+++ b/lib/radio/mix/src/tb_undc_real.vhd
@@ -0,0 +1,158 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:16:42 13.05.2007
+-- Design Name: tb_mix_cpx
+-- Module Name: tb_mix_cpx.vhd
+-- Project Name: mix_cpx
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; -- Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.mix_pkg.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_undc_real IS
+ Generic (
+ nbits_data : integer := 24;
+ nbits_data_frac : integer := 24;
+ nbits_k : integer := 24;
+ nbits_k_frac : integer := 24;
+ has_in_reg : boolean := true;
+ rounding : boolean := true;
+ saturating : boolean := true
+ );
+END tb_undc_real;
+
+ARCHITECTURE behavior OF tb_undc_real IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT undc_real
+ Generic
+ (
+ nbits_data : integer;
+ nbits_data_frac : integer;
+ nbits_k : integer;
+ nbits_k_frac : integer;
+ has_in_reg : boolean;
+ rounding : boolean;
+ saturating : boolean
+ );
+ Port
+ (
+ srst : in std_logic;
+ clk : in std_logic;
+ din_valid : in std_logic;
+ din : in sfixed;
+ kin_valid : in std_logic;
+ kin : in sfixed;
+ dout_valid : out std_logic;
+ dout : out sfixed;
+ dc_out : out sfixed
+ );
+ END COMPONENT;
+
+ --Constants
+ constant PERIOD : time := 10 ns;
+
+
+ --Inputs
+ SIGNAL clk : std_logic := '0';
+ SIGNAL srst : std_logic := '1';
+ SIGNAL din_valid : std_logic := '0';
+ SIGNAL kin_valid : std_logic := '0';
+ SIGNAL din : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
+ SIGNAL kin : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
+
+ --Outputs
+ SIGNAL dout : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
+ SIGNAL dc_out : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
+ SIGNAL dout_valid : std_logic;
+
+ SIGNAL k : real := 0.0;
+ SIGNAL x : real := 0.0;
+ SIGNAL y : real := 0.0;
+ SIGNAL dc : real := 0.0;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: undc_real
+ GENERIC MAP
+ (
+ nbits_data => nbits_data,
+ nbits_data_frac => nbits_data_frac,
+ nbits_k => nbits_k,
+ nbits_k_frac => nbits_k_frac,
+ has_in_reg => has_in_reg,
+ rounding => rounding,
+ saturating => saturating
+ )
+ PORT MAP
+ (
+ srst => srst,
+ clk => clk,
+ din_valid => din_valid,
+ din => din,
+ kin_valid => kin_valid,
+ kin => kin,
+ dout_valid => dout_valid,
+ dout => dout,
+ dc_out => dc_out
+ );
+
+ tb_clk : PROCESS
+ BEGIN
+ clk <= not clk;
+ wait for PERIOD/2;
+ END PROCESS;
+
+ tb : PROCESS
+
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 4*PERIOD;
+ srst <= '0';
+ ------------------------------------------
+ -- Load k
+ ------------------------------------------
+ wait for 2*PERIOD;
+ wait until rising_edge(clk);
+ kin <= to_sfixed(0.0005, kin);
+ kin_valid <= '1';
+ wait until rising_edge(clk);
+ kin_valid <= '1';
+ ------------------------------------------
+ -- Process
+ ------------------------------------------
+ wait for 2*PERIOD;
+ wait until rising_edge(clk);
+ din <= to_sfixed(0.5, din);
+ din_valid <= '1';
+ wait until rising_edge(clk);
+ din_valid <= '1';
+ wait for 5*PERIOD;
+
+ wait for 200*PERIOD;
+
+ assert false report "Test finished" severity error;
+ wait;
+ END PROCESS;
+
+ k <= to_real(kin);
+ x <= to_real(din);
+ y <= to_real(dout);
+ dc <= to_real(dc_out);
+
+END;
diff --git a/lib/radio/mix/src/undc_real.vhd b/lib/radio/mix/src/undc_real.vhd
new file mode 100644
index 0000000..be6df6e
--- /dev/null
+++ b/lib/radio/mix/src/undc_real.vhd
@@ -0,0 +1,139 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: mix_cpx - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.mix_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity undc_real is
+Generic
+(
+ nbits_data : integer := 12;
+ nbits_data_frac : integer := 12;
+ nbits_k : integer := 12;
+ nbits_k_frac : integer := 12;
+ has_in_reg : boolean := false;
+ rounding : boolean := true;
+ saturating : boolean := true
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ din_valid : in std_logic;
+ din : in sfixed;
+ kin_valid : in std_logic;
+ kin : in sfixed;
+ dout_valid : out std_logic;
+ dout : out sfixed;
+ dc_out : out sfixed
+);
+end undc_real;
+
+architecture Behavioral of undc_real is
+
+constant nbits_internal : integer := nbits_data + nbits_data;
+constant nbits_internal_frac : integer := nbits_data_frac + nbits_data_frac;
+
+signal x : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
+signal k : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
+signal dc : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
+signal y : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
+signal y1 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
+signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
+
+begin
+
+dout <= resize(y, sproto(nbits_data, nbits_data_frac), rounding, saturating);
+dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), false, false);
+
+------------------------------------------------------------
+ proc_din_reg: process(clk, din_valid, din)
+ begin
+ if has_in_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ x <= to_sfixed(0, x);
+ else
+ if din_valid = '1' then
+ x <= din;
+ end if;
+ end if;
+ end if;
+ else
+ x <= din;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_valid_reg: process(clk, din_valid)
+ begin
+ if has_in_reg = true then
+ if rising_edge(clk) then
+ if srst = '1' then
+ dout_valid <= '0';
+ else
+ dout_valid <= din_valid;
+ end if;
+ end if;
+ else
+ dout_valid <= din_valid;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_kin_reg: process(clk, kin_valid, kin)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ k <= to_sfixed(0, k);
+ else
+ if kin_valid = '1' then
+ k <= kin;
+ end if;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_pipe_y: process(clk, x, dc)
+ begin
+ y <= resize(x - dc, y, false, false);
+ if rising_edge(clk) then
+ if srst = '1' then
+ y1 <= to_sfixed(0, y1);
+ y2 <= to_sfixed(0, y2);
+ dc <= to_sfixed(0, dc);
+ else
+ y1 <= y;
+ y2 <= resize(y1 * k, y2, false, false);
+ dc <= resize(y2 + dc, dc, false, false);
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/radio/nco/sim/tb_nco.fdo b/lib/radio/nco/sim/tb_nco.fdo
new file mode 100644
index 0000000..ae31dbf
--- /dev/null
+++ b/lib/radio/nco/sim/tb_nco.fdo
@@ -0,0 +1,15 @@
+vlib work
+vcom -explicit -93 "../../../fixed/fixed_pkg_c.vhd"
+vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit -93 "../src/nco_pkg.vhd"
+vcom -explicit -93 "../src/waverom_dual.vhd"
+vcom -explicit -93 "../src/wavelut.vhd"
+vcom -explicit -93 "../src/nco_dbg.vhd"
+vcom -explicit -93 "../src/tb_nco.vhd"
+vsim -t 1ps -lib work tb_nco
+do {tb_nco.wdo}
+view wave
+view structure
+view signals
+run 250us
diff --git a/lib/radio/nco/sim/tb_nco.wdo b/lib/radio/nco/sim/tb_nco.wdo
new file mode 100644
index 0000000..0fd0917
--- /dev/null
+++ b/lib/radio/nco/sim/tb_nco.wdo
@@ -0,0 +1,46 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_nco/uut/srst
+add wave -noupdate -format Logic /tb_nco/uut/clk
+add wave -noupdate -format Logic /tb_nco/uut/pacc_clr
+add wave -noupdate -format Logic /tb_nco/uut/pacc_inc
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in
+add wave -noupdate -format Logic /tb_nco/uut/freq_load
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in
+add wave -noupdate -format Logic /tb_nco/uut/phase_load
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out
+add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_i
+add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_q
+add wave -noupdate -format Logic /tb_nco/uut/out_valid
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_ud
+add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_d
+add wave -noupdate -format Literal /tb_nco/uut/wave_i_d
+add wave -noupdate -format Literal /tb_nco/uut/wave_q_d
+add wave -noupdate -format Literal /tb_nco/uut/wave_i_ud
+add wave -noupdate -format Literal /tb_nco/uut/wave_q_ud
+add wave -noupdate -format Literal /tb_nco/uut/lfsr
+add wave -noupdate -format Literal /tb_nco/uut/lfsr_out
+add wave -noupdate -format Logic /tb_nco/uut/lut_addr_valid
+add wave -noupdate -format Logic /tb_nco/uut/lfsr_valid
+add wave -noupdate -format Logic /tb_nco/uut/wave_d_valid
+add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {249141632 ps} 0}
+configure wave -namecolwidth 193
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {249024188 ps} {250051359 ps}
diff --git a/lib/radio/nco/sim/tb_nco_results.m b/lib/radio/nco/sim/tb_nco_results.m
new file mode 100644
index 0000000..4147cea
--- /dev/null
+++ b/lib/radio/nco/sim/tb_nco_results.m
@@ -0,0 +1,61 @@
+% Read data
+function tb_nco_results(nbins)
+fa = 100.0;
+f = TEXTREAD('freq.txt')*1E-6
+
+I_ud = TEXTREAD('q_ud.txt')';
+I_d = TEXTREAD('q_d.txt')';
+LFSR = TEXTREAD('lfsr.txt');
+
+N= length(I_ud);
+N_fft = min(16384, N);
+N_fft2 = N_fft/2;
+
+fft_y2 = 2/N_fft*abs(fft(I_ud(1:N_fft).*hann(N_fft)'));
+fft_y3 = 2/N_fft*abs(fft(I_d(1:N_fft).*hann(N_fft)'));
+
+[i, v] = get_maxpur(fft_y2, fa, f);
+max_spur_freq = (i*fa/N_fft);
+max_spur_value = 20*log10(v);
+
+[i, v] = get_maxpur(fft_y3, fa, f);
+max_ditherd_spur_freq = (i*fa/N_fft);
+max_ditherd_spur_value = 20*log10(v);
+
+% Output
+close all;
+
+subplot(2,1,1)
+plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid;
+spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_spur_value, max_spur_freq);
+legend('With dithering', spur_legend);
+legend('No dithering', spur_legend);
+title('Table');
+ylabel('dB');
+xlabel('f/MHz');
+axis([0 fa/2 -120 0]);
+subplot(2,1,2)
+plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid;
+spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_ditherd_spur_value, max_ditherd_spur_freq);
+legend('With dithering', spur_legend);
+title('Table');
+ylabel('dB');
+xlabel('f/MHz');
+axis([0 fa/2 -120 0]);
+
+figure;
+hist(LFSR, nbins)
+
+function [max_i, max_v] = get_maxpur(spec, fa, f)
+max_v = 0;
+max_i = 0;
+for ii=1:fix(length(spec)/2+1),
+ fi = ii*fa/length(spec);
+ dfi = fi - f;
+ if abs(dfi) > 0.05*f
+ if spec(ii) > max_v
+ max_v = spec(ii);
+ max_i = ii;
+ end
+ end;
+end;
diff --git a/lib/radio/nco/src/nco.vhd b/lib/radio/nco/src/nco.vhd
new file mode 100644
index 0000000..25b7f1d
--- /dev/null
+++ b/lib/radio/nco/src/nco.vhd
@@ -0,0 +1,223 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: cordic_stage - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.nco_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity nco is
+Generic
+(
+ nbits_wave : integer := 18;
+ nbits_phase : integer := 16;
+ nbits_lut_depth : integer := 12;
+ nbits_dither : integer := 4;
+ nbits_lfsr : integer := 12;
+ q_phase : phase_relation_t := phase_90deg;
+ has_pipe_reg : boolean := false;
+ has_out_reg : boolean := false
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ pacc_clr : in std_logic;
+ pacc_inc : in std_logic;
+ freq_in : in unsigned(nbits_phase-1 downto 0);
+ freq_load : in std_logic;
+ phase_in : in unsigned(nbits_phase-1 downto 0);
+ phase_load : in std_logic;
+ phase_out : out unsigned(nbits_phase-1 downto 0);
+ wave_out_i : out sfixed;
+ wave_out_q : out sfixed;
+ out_valid : out std_logic
+);
+end nco;
+
+architecture Behavioral of nco is
+
+ COMPONENT wavelut
+ Generic
+ (
+ nbits_wave : integer;
+ nbits_wave_frac : integer;
+ nbits_lut_depth : integer;
+ q_phase : phase_relation_t;
+ has_out_reg : boolean
+ );
+ Port
+ (
+ clk : in std_logic;
+ rst : in std_logic;
+ addr_valid : in std_logic;
+ addr : in unsigned(nbits_lut_depth-1 downto 0);
+ wave_i_out : out sfixed;
+ wave_q_out : out sfixed;
+ valid_out : out std_logic
+ );
+ END COMPONENT;
+
+-------------------------------------------------------------------------------
+ constant nbits_wave_frac : integer := nbits_wave;
+
+-------------------------------------------------------------------------------
+ constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
+
+ signal phase : unsigned(nbits_phase-1 downto 0);
+ signal freq_in_r : unsigned(nbits_phase-1 downto 0);
+ signal phase_in_r : unsigned(nbits_phase-1 downto 0);
+ signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
+ signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+
+ type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
+ signal lfsr : lfsr_t;
+ signal lfsr_out : unsigned(nbits_dither-1 downto 0);
+ signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic;
+
+-------------------------------------------------------------------------------
+begin
+
+ wave_out_i <= wave_i_d;
+ wave_out_q <= wave_q_d;
+ out_valid <= wave_d_valid;
+
+------------------------------------------------------------
+ proc_lfsr: process(srst, clk, lfsr, pacc_inc)
+ variable lo : unsigned(nbits_dither-1 downto 0);
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ lfsr_valid <= '0';
+ lfsr_out <= (others => '0');
+ for i in lfsr'range loop
+ lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
+ end loop;
+ else
+ lfsr_valid <= '0';
+ if pacc_inc ='1' then
+ lfsr_valid <= '1';
+ lo := (others => '0');
+ for i in lfsr'range loop
+ if lfsr(i)(lfsr(i)'left) = '1' then
+ lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
+ else
+ lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
+ end if;
+ end loop;
+ for i in lfsr'range loop
+ lo := lo + lfsr(i)(nbits_dither-1 downto 0);
+ end loop;
+ -- lo := lfsr(0)(nbits_dither downto 0);
+ lfsr_out <= lo(nbits_dither-1 downto 0);
+ end if;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_phase_accu: process(clk, phase)
+ variable phase_accu : unsigned(nbits_phase-1 downto 0);
+
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ phase_accu := (others => '0');
+ else
+ phase <= phase_accu + phase_in_r;
+ if pacc_clr = '1' then
+ phase_accu := (others => '0');
+ elsif pacc_inc = '1' then
+ phase_accu := phase_accu + freq_in_r;
+ end if;
+ end if;
+ end if;
+ phase_out <= phase;
+ end process;
+
+------------------------------------------------------------
+ freq_in_reg: process(srst, clk, freq_load, freq_in)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ freq_in_r <= (others => '0');
+ elsif freq_load = '1' then
+ freq_in_r <= freq_in;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ phase_in_reg: process(srst, clk, phase_load, phase_in)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ phase_in_r <= (others => '0');
+ elsif phase_load = '1' then
+ phase_in_r <= phase_in;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_pipe_reg: process(clk)
+ variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
+ begin
+ if rising_edge(clk) then
+ lut_addr_valid <= '0';
+ if srst = '1' then
+ lfsr_sum := (others => '0');
+ elsif lfsr_valid = '1' then
+ lut_addr_valid <= '1';
+ lfsr_sum := lfsr_out + phase;
+ end if;
+ end if;
+ lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
+ end process;
+
+------------------------------------------------------------
+ inst_wavelut_d: wavelut
+ GENERIC MAP
+ (
+ nbits_wave => nbits_wave,
+ nbits_wave_frac => nbits_wave_frac,
+ nbits_lut_depth => nbits_lut_depth,
+ q_phase => q_phase,
+ has_out_reg => has_out_reg
+ )
+ PORT MAP
+ (
+ rst => srst,
+ clk => clk,
+ addr_valid => lut_addr_valid,
+ addr => lut_addr_d,
+ wave_i_out => wave_i_d,
+ wave_q_out => wave_q_d,
+ valid_out => wave_d_valid
+ );
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/radio/nco/src/nco.vhd.bak b/lib/radio/nco/src/nco.vhd.bak
new file mode 100644
index 0000000..657b97a
--- /dev/null
+++ b/lib/radio/nco/src/nco.vhd.bak
@@ -0,0 +1,240 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: cordic_stage - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.nco_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity nco is
+Generic
+(
+ nbits_wave : integer := 12;
+ nbits_phase : integer := 16;
+ nbits_lut_depth : integer := 12;
+ nbits_dither : integer := 4;
+ nbits_lfsr : integer := 12;
+ has_pipe_reg : boolean := false;
+ has_out_reg : boolean := false
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ pacc_clr : in std_logic;
+ pacc_inc : in std_logic;
+ freq_in : in unsigned(nbits_phase-1 downto 0);
+ freq_load : in std_logic;
+ phase_in : in unsigned(nbits_phase-1 downto 0);
+ phase_load : in std_logic;
+ phase_out : out unsigned(nbits_phase-1 downto 0);
+ wave_out_i : out sfixed;
+ wave_out_q : out sfixed;
+ out_valid : out std_logic
+);
+end nco;
+
+architecture Behavioral of nco is
+
+ COMPONENT wavelut
+ Generic
+ (
+ nbits_wave : integer;
+ nbits_wave_frac : integer;
+ nbits_lut_depth : integer;
+ has_out_reg : boolean
+ );
+ Port
+ (
+ clk : in std_logic;
+ addr_valid : in std_logic;
+ addr : in unsigned(nbits_lut_depth-1 downto 0);
+ wave_i_out : out sfixed;
+ wave_q_out : out sfixed
+ );
+ END COMPONENT;
+
+-------------------------------------------------------------------------------
+ constant nbits_wave_frac : integer := nbits_wave;
+
+-------------------------------------------------------------------------------
+ constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
+
+ signal valid : std_logic_vector(3 downto 0);
+ signal phase : unsigned(nbits_phase-1 downto 0);
+ signal freq_in_r : unsigned(nbits_phase-1 downto 0);
+ signal phase_in_r : unsigned(nbits_phase-1 downto 0);
+ signal lsfr_sum : unsigned(nbits_phase-1 downto 0);
+ signal lut_addr : unsigned(nbits_lut_depth-1 downto 0);
+ signal wave_i, wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+ type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
+ signal lfsr : lfsr_t;
+ signal lfsr_out : unsigned(nbits_dither-1 downto 0);
+ signal lut_addr_valid _ std_logic;
+
+-------------------------------------------------------------------------------
+begin
+
+ wave_out_i <= wave_i;
+ wave_out_q <= wave_q;
+
+------------------------------------------------------------
+ proc_ctrl: process(srst, clk, pacc_inc, pacc_clr)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ valid <= (others => '0');
+ else
+ valid <= valid(valid'left-1 downto valid'right) & (pacc_inc or pacc_clr);
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_lfsr: process(srst, clk, lfsr, pacc_inc)
+ variable lo : unsigned(nbits_dither downto 0);
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ for i in lfsr'range loop
+ lfsr(i) <= to_unsigned(1234+2**i, nbits_lfsr);
+ end loop;
+ elsif pacc_inc ='1' then
+ lo := (others => '0');
+ for i in lfsr'range loop
+ if lfsr(i)(lfsr(i)'left) = '1' then
+ lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
+ else
+ lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
+ end if;
+ end loop;
+ for i in lfsr'range loop
+ lo := lo + lfsr(i)(nbits_dither-1 downto 0);
+ end loop;
+-- lo := lfsr(0)(nbits_dither downto 0);
+ lfsr_out <= lo(nbits_dither-1 downto 0);
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
+ variable phase_accu : unsigned(nbits_phase-1 downto 0);
+
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ phase_accu := (others => '0');
+ else
+ phase <= phase_accu + phase_in_r;
+ if pacc_clr = '1' then
+ phase_accu := (others => '0');
+ elsif pacc_inc = '1' then
+ phase_accu := phase_accu + freq_in_r;
+ end if;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ freq_in_reg: process(srst, clk, freq_load, freq_in)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ freq_in_r <= (others => '0');
+ elsif freq_load = '1' then
+ freq_in_r <= freq_in;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ phase_in_reg: process(srst, clk, phase_load, phase_in)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ phase_in_r <= (others => '0');
+ elsif phase_load = '1' then
+ phase_in_r <= phase_in;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_pipe_reg: process(clk)
+ begin
+ if rising_edge(clk) then
+ lsfr_sum <= lfsr_out + phase;
+ lut_addr <= lsfr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_out_reg: process(clk, phase)
+ begin
+ if has_out_reg = true then
+ if rising_edge(clk) then
+ phase_out <= phase;
+ end if;
+ else
+ phase_out <= phase;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_valid_reg: process(clk, valid)
+ begin
+ out_valid <= valid(valid'right+1);
+ if has_out_reg = true then
+ out_valid <= valid(valid'right+2);
+ if has_pipe_reg = true then
+ out_valid <= valid(valid'right+3);
+ end if;
+ elsif has_pipe_reg = true then
+ out_valid <= valid(valid'right+2);
+ end if;
+ end process;
+
+------------------------------------------------------------
+ inst_wavelut_d: wavelut
+ GENERIC MAP
+ (
+ nbits_wave => nbits_wave,
+ nbits_wave_frac => nbits_wave_frac,
+ nbits_lut_depth => nbits_lut_depth,
+ has_out_reg => has_out_reg
+ )
+ PORT MAP
+ (
+ clk => clk,
+ addr => lut_addr,
+ addr_valid => lut_addr_valid,
+ wave_i_out => wave_i,
+ wave_q_out => wave_q
+ );
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/radio/nco/src/nco_dbg.vhd b/lib/radio/nco/src/nco_dbg.vhd
new file mode 100644
index 0000000..c0038a9
--- /dev/null
+++ b/lib/radio/nco/src/nco_dbg.vhd
@@ -0,0 +1,253 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: cordic_stage - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.nco_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity nco is
+Generic
+(
+ nbits_wave : integer := 18;
+ nbits_phase : integer := 16;
+ nbits_lut_depth : integer := 12;
+ nbits_dither : integer := 4;
+ nbits_lfsr : integer := 12;
+ q_phase : phase_relation_t := phase_90deg;
+ has_pipe_reg : boolean := false;
+ has_out_reg : boolean := false
+);
+Port
+(
+ srst : in std_logic;
+ clk : in std_logic;
+ pacc_clr : in std_logic;
+ pacc_inc : in std_logic;
+ freq_in : in unsigned(nbits_phase-1 downto 0);
+ freq_load : in std_logic;
+ phase_in : in unsigned(nbits_phase-1 downto 0);
+ phase_load : in std_logic;
+ phase_out : out unsigned(nbits_phase-1 downto 0);
+ wave_out_i : out sfixed;
+ wave_out_q : out sfixed;
+ out_valid : out std_logic;
+ debug_out : out debug_out_t
+);
+end nco;
+
+architecture Behavioral of nco is
+
+ COMPONENT wavelut
+ Generic
+ (
+ nbits_wave : integer;
+ nbits_wave_frac : integer;
+ nbits_lut_depth : integer;
+ q_phase : phase_relation_t;
+ has_out_reg : boolean
+ );
+ Port
+ (
+ clk : in std_logic;
+ rst : in std_logic;
+ addr_valid : in std_logic;
+ addr : in unsigned(nbits_lut_depth-1 downto 0);
+ wave_i_out : out sfixed;
+ wave_q_out : out sfixed;
+ valid_out : out std_logic
+ );
+ END COMPONENT;
+
+-------------------------------------------------------------------------------
+ constant nbits_wave_frac : integer := nbits_wave;
+
+-------------------------------------------------------------------------------
+ constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
+
+ signal phase : unsigned(nbits_phase-1 downto 0);
+ signal freq_in_r : unsigned(nbits_phase-1 downto 0);
+ signal phase_in_r : unsigned(nbits_phase-1 downto 0);
+ signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0);
+ signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
+ signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+ signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+
+ type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
+ signal lfsr : lfsr_t;
+ signal lfsr_out : unsigned(nbits_dither-1 downto 0);
+ signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic;
+
+-------------------------------------------------------------------------------
+begin
+
+ wave_out_i <= wave_i_d;
+ wave_out_q <= wave_q_d;
+ out_valid <= wave_d_valid;
+
+ debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out;
+ debug_out.i_d <= to_real(wave_i_d);
+ debug_out.q_d <= to_real(wave_q_d);
+ debug_out.i_ud <= to_real(wave_i_ud);
+ debug_out.q_ud <= to_real(wave_q_ud);
+
+------------------------------------------------------------
+ proc_lfsr: process(srst, clk, lfsr, pacc_inc)
+ variable lo : unsigned(nbits_dither-1 downto 0);
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ lfsr_valid <= '0';
+ lfsr_out <= (others => '0');
+ for i in lfsr'range loop
+ lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
+ end loop;
+ else
+ lfsr_valid <= '0';
+ if pacc_inc ='1' then
+ lfsr_valid <= '1';
+ lo := (others => '0');
+ for i in lfsr'range loop
+ if lfsr(i)(lfsr(i)'left) = '1' then
+ lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
+ else
+ lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
+ end if;
+ end loop;
+ for i in lfsr'range loop
+ lo := lo + lfsr(i)(nbits_dither-1 downto 0);
+ end loop;
+ -- lo := lfsr(0)(nbits_dither downto 0);
+ lfsr_out <= lo(nbits_dither-1 downto 0);
+ end if;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
+ variable phase_accu : unsigned(nbits_phase-1 downto 0);
+
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ phase_accu := (others => '0');
+ else
+ phase <= phase_accu + phase_in_r;
+ if pacc_clr = '1' then
+ phase_accu := (others => '0');
+ elsif pacc_inc = '1' then
+ phase_accu := phase_accu + freq_in_r;
+ end if;
+ end if;
+ end if;
+ phase_out <= phase;
+ end process;
+
+------------------------------------------------------------
+ freq_in_reg: process(srst, clk, freq_load, freq_in)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ freq_in_r <= (others => '0');
+ elsif freq_load = '1' then
+ freq_in_r <= freq_in;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ phase_in_reg: process(srst, clk, phase_load, phase_in)
+ begin
+ if rising_edge(clk) then
+ if srst = '1' then
+ phase_in_r <= (others => '0');
+ elsif phase_load = '1' then
+ phase_in_r <= phase_in;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+ proc_pipe_reg: process(clk)
+ variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
+ begin
+ if rising_edge(clk) then
+ lut_addr_valid <= '0';
+ if srst = '1' then
+ lfsr_sum := (others => '0');
+ elsif lfsr_valid = '1' then
+ lut_addr_valid <= '1';
+ lfsr_sum := lfsr_out + phase;
+ end if;
+ end if;
+ lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
+ lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
+ end process;
+
+------------------------------------------------------------
+ inst_wavelut_ud: wavelut
+ GENERIC MAP
+ (
+ nbits_wave => nbits_wave,
+ nbits_wave_frac => nbits_wave_frac,
+ nbits_lut_depth => nbits_lut_depth,
+ q_phase => q_phase,
+ has_out_reg => has_out_reg
+ )
+ PORT MAP
+ (
+ rst => srst,
+ clk => clk,
+ addr_valid => lut_addr_valid,
+ addr => lut_addr_ud,
+ wave_i_out => wave_i_ud,
+ wave_q_out => wave_q_ud,
+ valid_out => wave_ud_valid
+ );
+
+ inst_wavelut_d: wavelut
+ GENERIC MAP
+ (
+ nbits_wave => nbits_wave,
+ nbits_wave_frac => nbits_wave_frac,
+ nbits_lut_depth => nbits_lut_depth,
+ q_phase => q_phase,
+ has_out_reg => has_out_reg
+ )
+ PORT MAP
+ (
+ rst => srst,
+ clk => clk,
+ addr_valid => lut_addr_valid,
+ addr => lut_addr_d,
+ wave_i_out => wave_i_d,
+ wave_q_out => wave_q_d,
+ valid_out => wave_d_valid
+ );
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/radio/nco/src/nco_pkg.vhd b/lib/radio/nco/src/nco_pkg.vhd
new file mode 100644
index 0000000..0bb9cef
--- /dev/null
+++ b/lib/radio/nco/src/nco_pkg.vhd
@@ -0,0 +1,117 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use IEEE.MATH_REAL.ALL;
+use work.fixed_pkg.all;
+
+-------------------------------------------------------------------------------
+package nco_pkg is
+
+ constant tpd : time := 0 ns;
+
+ -- Global set arithmetic rounding mode
+ constant pi : real := 3.141592653589793e+000;
+ constant sqrt2 : real := 1.414213562373095e+000;
+ constant sqrt2_inv : real := 7.071067811865475e-001;
+
+ type real_array_t is array (natural range <>) of real;
+ type natural_array_t is array (natural range <>) of natural;
+ type phase_relation_t is (phase_90deg, phase_270deg);
+
+ type debug_out_t is record
+ lfsr : unsigned(31 downto 0);
+ i_ud : real;
+ q_ud : real;
+ i_d : real;
+ q_d : real;
+ end record;
+
+ constant lfsr_poly : natural_array_t(3 to 24) :=
+ (
+ 12, -- 3
+ 24, -- 4
+ 58, -- 5
+ 114, -- 6
+ 210, -- 7
+ 500, -- 8
+ 1000, -- 9
+ 1824, -- 10
+ 3712, -- 11
+ 7184, -- 12
+ 14592, -- 13
+ 28674, -- 14
+ 59392, -- 15
+ 106512, -- 16
+ 245760, -- 17
+ 466944, -- 18
+ 933888, -- 19
+ 1654784, -- 20
+ 3735552, -- 21
+ 7342080, -- 22
+ 14745600, -- 23
+ 14811138 -- 24
+ );
+
+ function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t;
+ function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t;
+
+ -------------------------------------------------------------
+ -- Constructor helpers
+ -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
+ function uproto (nbits : integer; nbits_frac : integer) return ufixed;
+
+ -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
+ function sproto (nbits : integer; nbits_frac : integer) return sfixed;
+
+end; -- package nco_pkg;
+
+-------------------------------------------------------------------------------
+package body nco_pkg is
+
+ function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is
+ variable tbl : real_array_t (0 to nsamples-1);
+ variable phi : real := phi_in;
+ variable dphi : real := 2.0*pi*omega;
+
+ begin
+ for i in 0 to nsamples-1 loop
+ tbl(i) := sin(phi);
+ phi := phi + dphi;
+ end loop;
+
+ return tbl;
+ end sin_tbl;
+
+ -------------------------------------------------------------
+ function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is
+ variable tbl : real_array_t (0 to nsamples-1);
+ variable phi : real := phi_in;
+ variable dphi : real := 2.0*pi*omega;
+
+ begin
+ for i in 0 to nsamples-1 loop
+ tbl(i) := cos(phi);
+ phi := phi + dphi;
+ end loop;
+
+ return tbl;
+ end cos_tbl;
+
+ -------------------------------------------------------------
+ -- Constuctor helpers
+ function uproto (nbits : integer; nbits_frac : integer) return ufixed is
+ constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0');
+ begin
+ return result(nbits-nbits_frac-1 downto -nbits_frac);
+ end uproto;
+
+ -------------------------------------------------------------
+ function sproto (nbits : integer; nbits_frac : integer) return sfixed is
+ constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0');
+ begin
+ return result(nbits-nbits_frac downto -nbits_frac+1);
+ end sproto;
+
+-------------------------------------------------------------------------------
+end; -- package nco_pkg;
diff --git a/lib/radio/nco/src/tb_nco.vhd b/lib/radio/nco/src/tb_nco.vhd
new file mode 100644
index 0000000..f2d930a
--- /dev/null
+++ b/lib/radio/nco/src/tb_nco.vhd
@@ -0,0 +1,299 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:16:42 13.05.2007
+-- Design Name: tb_nco
+-- Module Name: tb_nco.vhd
+-- Project Name: nco
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; -- Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.nco_pkg.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_nco IS
+ Generic (
+ nbits_wave : integer := 18;
+ nbits_phase : integer := 16;
+ nbits_lut_depth : integer := 12;
+ nbits_dither : integer := 4;
+ nbits_lfsr : integer := 12;
+ q_phase : phase_relation_t := phase_270deg;
+ has_pipe_reg : boolean := true;
+ has_out_reg : boolean := true
+ );
+END tb_nco;
+
+ARCHITECTURE behavior OF tb_nco IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT nco
+ GENERIC (
+ nbits_wave : integer;
+ nbits_phase : integer;
+ nbits_lut_depth : integer;
+ nbits_dither : integer;
+ nbits_lfsr : integer;
+ q_phase : phase_relation_t;
+ has_pipe_reg : boolean;
+ has_out_reg : boolean
+ );
+ PORT(
+ srst : in std_logic;
+ clk : in std_logic;
+-- ce : in std_logic;
+ pacc_clr : in std_logic;
+ pacc_inc : in std_logic;
+ freq_in : in unsigned(nbits_phase-1 downto 0);
+ freq_load : in std_logic;
+ phase_in : in unsigned(nbits_phase-1 downto 0);
+ phase_load : in std_logic;
+ phase_out : out unsigned(nbits_phase-1 downto 0);
+ wave_out_i : out sfixed;
+ wave_out_q : out sfixed;
+ out_valid : out std_logic;
+ debug_out : out debug_out_t
+ );
+ END COMPONENT;
+
+ --Constants
+ constant f : REAL := 4.1667E6;
+ constant df : REAL := 10.0E3;
+ constant fa : REAL := 100.0E6;
+ constant PERIOD : time := 10 ns;
+ constant nbits_wave_frac : integer := nbits_wave;
+
+ SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
+ SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
+
+ --Inputs
+ SIGNAL clk : std_logic := '0';
+-- SIGNAL ce : std_logic := '0';
+ SIGNAL srst : std_logic := '1';
+ SIGNAL pacc_clr : std_logic := '0';
+ SIGNAL pacc_inc : std_logic := '0';
+ SIGNAL phase_load : std_logic := '0';
+ SIGNAL freq_load : std_logic := '0';
+ SIGNAL freq_in : unsigned(nbits_phase-1 downto 0);
+ SIGNAL phase_in : unsigned(nbits_phase-1 downto 0);
+
+ --Outputs
+ SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+ SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+ SIGNAL out_valid : std_logic;
+ SIGNAL phase_out : unsigned(nbits_phase-1 downto 0);
+ SIGNAL debug_out : debug_out_t;
+
+ SIGNAL fileout_enable : std_logic := '0';
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: nco
+ GENERIC MAP (
+ nbits_wave => nbits_wave,
+ nbits_phase => nbits_phase,
+ nbits_lut_depth => nbits_lut_depth,
+ nbits_dither => nbits_dither,
+ nbits_lfsr => nbits_lfsr,
+ q_phase => q_phase,
+ has_pipe_reg => has_pipe_reg,
+ has_out_reg => has_out_reg
+ )
+ PORT MAP(
+ srst => srst,
+ clk => clk,
+-- ce => ce,
+ pacc_clr => pacc_clr,
+ pacc_inc => pacc_inc,
+ freq_in => freq_in,
+ freq_load => freq_load,
+ phase_in => phase_in,
+ phase_load => phase_load,
+ phase_out => phase_out,
+ wave_out_i => wave_out_i,
+ wave_out_q => wave_out_q,
+ out_valid => out_valid,
+ debug_out => debug_out
+ );
+
+ tb_clk : PROCESS
+ BEGIN
+ clk <= not clk;
+ wait for PERIOD/2;
+ END PROCESS;
+
+ tb : PROCESS
+ file RESULT_FREQ: text open write_mode is "freq.txt";
+ variable L: line;
+
+ BEGIN
+
+ -- Wait 100 ns for global reset to finish
+ wait for 4*PERIOD;
+ srst <= '0';
+
+ fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
+
+ wait for 2*PERIOD;
+-- ce <= '1';
+ -------------------------------------------
+ -- 1
+ phase_in <= to_unsigned(0,nbits_phase);
+ wait until rising_edge(clk);
+ phase_load <= '1';
+ wait until rising_edge(clk);
+ phase_load <= '0';
+
+ freq_in <= to_unsigned(1411,nbits_phase);
+ wait until rising_edge(clk);
+ freq_load <= '1';
+ wait until rising_edge(clk);
+ freq_load <= '0';
+
+ wait for 2*PERIOD;
+ pacc_inc <= '1';
+
+ wait for 2*PERIOD;
+ wait until rising_edge(clk);
+
+ wait for 40*PERIOD;
+ -------------------------------------------
+ freq_in <= to_unsigned(643,nbits_phase);
+ wait until rising_edge(clk);
+ freq_load <= '1';
+ wait until rising_edge(clk);
+ freq_load <= '0';
+
+ wait for 40*PERIOD;
+ -------------------------------------------
+ phase_in <= to_unsigned(800,nbits_phase);
+ wait until rising_edge(clk);
+ phase_load <= '1';
+ wait until rising_edge(clk);
+ phase_load <= '0';
+
+ wait for 20*PERIOD;
+ -------------------------------------------
+ phase_in <= to_unsigned(45072,nbits_phase);
+ wait until rising_edge(clk);
+ phase_load <= '1';
+ wait until rising_edge(clk);
+ phase_load <= '0';
+
+ wait for 20*PERIOD;
+ -------------------------------------------
+ phase_in <= to_unsigned(20593,nbits_phase);
+ wait until rising_edge(clk);
+ phase_load <= '1';
+ wait until rising_edge(clk);
+ phase_load <= '0';
+
+ -------------------------------------------
+ freq_in <= to_unsigned(freq_word,nbits_phase);
+ wait until rising_edge(clk);
+ freq_load <= '1';
+ wait until rising_edge(clk);
+ freq_load <= '0';
+
+ wait for 20*PERIOD;
+ fileout_enable <= '1';
+
+ wait for 20000*PERIOD;
+ fileout_enable <= '0';
+
+ -------------------------------------------
+ -- Sweep
+ freq_word <= 100;
+ for i in 1 to 200 loop
+ wait for 20*PERIOD;
+ freq_word <= freq_word + dfreq_word;
+
+ freq_in <= to_unsigned(freq_word,nbits_phase);
+ wait until rising_edge(clk);
+ freq_load <= '1';
+ wait until rising_edge(clk);
+ freq_load <= '0';
+
+ end loop;
+
+ pacc_inc <= '0';
+ wait for 20*PERIOD;
+ fileout_enable <= '0';
+ wait until rising_edge(clk);
+ pacc_clr <= '1';
+ wait until rising_edge(clk);
+ pacc_clr <= '0';
+ wait for 20*PERIOD;
+ pacc_inc <= '1';
+ wait for 20*PERIOD;
+ wait until rising_edge(clk);
+ pacc_clr <= '1';
+ wait until rising_edge(clk);
+ pacc_clr <= '0';
+ wait for 20*PERIOD;
+ pacc_inc <= '0';
+ wait for 20*PERIOD;
+ wait until rising_edge(clk);
+ pacc_inc <= '1';
+ wait until rising_edge(clk);
+ pacc_inc <= '0';
+ wait for 20*PERIOD;
+ wait until rising_edge(clk);
+ srst <= '1';
+ wait until rising_edge(clk);
+ srst <= '0';
+ freq_in <= to_unsigned(freq_word,nbits_phase);
+ wait until rising_edge(clk);
+ freq_load <= '1';
+ wait until rising_edge(clk);
+ freq_load <= '0';
+
+ wait for 20*PERIOD;
+ pacc_inc <= '1';
+ wait for 20*PERIOD;
+ wait until rising_edge(clk);
+ srst <= '1';
+ wait until rising_edge(clk);
+ srst <= '0';
+ wait for 20*PERIOD;
+ pacc_inc <= '0';
+
+ wait for 20*PERIOD;
+
+ assert false report "Test finished" severity error;
+ wait;
+ END PROCESS;
+
+ tb_fo : PROCESS(clk, fileout_enable, out_valid)
+ file RESULT_I: text open write_mode is "i_ud.txt";
+ file RESULT_Q: text open write_mode is "q_ud.txt";
+ file RESULT_ID: text open write_mode is "i_d.txt";
+ file RESULT_QD: text open write_mode is "q_d.txt";
+ file RESULT_LFSR: text open write_mode is "lfsr.txt";
+ variable L: line;
+
+ BEGIN
+ if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
+ fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud));
+ fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud));
+ fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d));
+ fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d));
+ fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr)));
+ end if;
+
+ END PROCESS;
+
+
+END;
diff --git a/lib/radio/nco/src/wavelut.vhd b/lib/radio/nco/src/wavelut.vhd
new file mode 100644
index 0000000..4b0f02e
--- /dev/null
+++ b/lib/radio/nco/src/wavelut.vhd
@@ -0,0 +1,239 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: cordic_stage - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.nco_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity wavelut is
+Generic
+(
+ nbits_wave : integer := 12;
+ nbits_wave_frac : integer := 12;
+ nbits_lut_depth : integer := 12;
+ q_phase : phase_relation_t := phase_90deg;
+ has_out_reg : boolean := false
+);
+Port
+(
+ rst : in std_logic;
+ clk : in std_logic;
+ addr_valid : in std_logic;
+ addr : in unsigned(nbits_lut_depth-1 downto 0);
+ wave_i_out : out sfixed;
+ wave_q_out : out sfixed;
+ valid_out : out std_logic
+);
+end wavelut;
+
+architecture Behavioral of wavelut is
+
+ COMPONENT waverom_dual
+ Generic
+ (
+ nbits_wave : integer;
+ nbits_wave_frac : integer;
+ nbits_rom_depth : integer
+ );
+ Port
+ (
+ clk : in std_logic;
+ addr_i : in unsigned(nbits_rom_depth-1 downto 0);
+ addr_q : in unsigned(nbits_rom_depth-1 downto 0);
+ wave_i_out : out sfixed;
+ wave_q_out : out sfixed
+ );
+ END COMPONENT;
+
+-------------------------------------------------------------------------------
+constant nbits_rom_depth : integer := nbits_lut_depth-2;
+
+-------------------------------------------------------------------------------
+signal wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+signal wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+signal inv_i : std_logic;
+signal inv_q : std_logic;
+signal addr_i : unsigned(nbits_rom_depth-1 downto 0);
+signal addr_q : unsigned(nbits_rom_depth-1 downto 0);
+signal zero_i : std_logic;
+signal zero_q : std_logic;
+
+-------------------------------------------------------------------------------
+begin
+
+ inst_waverom_dual: waverom_dual
+ GENERIC MAP
+ (
+ nbits_wave => nbits_wave,
+ nbits_wave_frac => nbits_wave_frac,
+ nbits_rom_depth => nbits_rom_depth
+ )
+ PORT MAP
+ (
+ clk => clk,
+ addr_i => addr_i,
+ addr_q => addr_q,
+ wave_i_out => wave_i,
+ wave_q_out => wave_q
+ );
+
+------------------------------------------------------------
+proc_valid: process(clk)
+ variable v : unsigned(0 to 1);
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ v := (others => '0');
+ valid_out <= '0';
+ else
+ valid_out <= v(1);
+ v(1) := v(0);
+ v(0) := addr_valid;
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------
+proc_tbl_addr_i: process(clk, addr)
+ variable index : unsigned(addr'left downto addr'right);
+ variable n2 : integer;
+ constant N_2 : integer := 2**(nbits_lut_depth-1);
+ constant N_4 : integer := 2**(nbits_lut_depth-2);
+ begin
+ n2 := to_integer(addr(addr'left-1 downto addr'right));
+ if n2 > N_4 then
+ index := to_unsigned(N_2 - n2, index'length);
+ else
+ index := to_unsigned(n2, index'length);
+ end if;
+
+ if rising_edge(clk) then
+ if rst = '1' then
+ addr_i <= (others => '0');
+ zero_i <= '0';
+ inv_i <= '0';
+ elsif addr_valid = '1' then
+ addr_i <= index(addr'left-2 downto addr'right);
+ zero_i <= index(addr'left-1);
+ inv_i <= addr(addr'left) xor addr(addr'left-1);
+ end if;
+ end if;
+
+ end process;
+
+-------------------------------------------------------------------------------
+proc_tbl_addr_q: process(clk, addr)
+ variable index : unsigned(addr'left downto addr'right);
+ variable n2 : integer;
+ constant N_4 : integer := 2**(nbits_lut_depth-2);
+
+ begin
+ n2 := to_integer(addr(addr'left-1 downto addr'right));
+ if n2 > N_4 then
+ index := to_unsigned(n2 - N_4, index'length);
+ else
+ index := to_unsigned(N_4 - n2, index'length);
+ end if;
+
+ if rising_edge(clk) then
+ if rst = '1' then
+ addr_q <= (others => '0');
+ zero_q <= '0';
+ inv_q <= '0';
+ elsif addr_valid = '1' then
+ addr_q <= index(addr'left-2 downto addr'right);
+ zero_q <= index(addr'left-1);
+ if q_phase = phase_90deg then
+ inv_q <= addr(addr'left);
+ elsif q_phase = phase_270deg then
+ inv_q <= not addr(addr'left);
+ end if;
+ end if;
+ end if;
+
+ end process;
+
+------------------------------------------------------------
+proc_out_i: process(clk, wave_i, inv_i, zero_i)
+ variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+ variable z, inv : std_logic;
+ begin
+
+ w := to_sfixed(0.0, w);
+ if z = '0' then
+ w := wave_i;
+ if inv = '1' then
+ w := resize(-wave_i, w, fixed_truncate, fixed_wrap);
+ end if;
+ end if;
+
+ if has_out_reg = true then
+ if rising_edge(clk) then
+ wave_i_out <= w;
+ end if;
+ else
+ wave_i_out <= w;
+ end if;
+
+ if rising_edge(clk) then
+ z := zero_i;
+ inv := inv_i;
+ end if;
+
+ end process;
+
+------------------------------------------------------------
+proc_out_q: process(clk, wave_q, inv_q, zero_q)
+ variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+ variable z, inv : std_logic;
+ begin
+
+ w := to_sfixed(0.0, w);
+ if z = '0' then
+ w := wave_q;
+ if inv = '1' then
+ w := resize(-wave_q, w, fixed_truncate, fixed_wrap);
+ end if;
+ end if;
+
+ if has_out_reg = true then
+ if rising_edge(clk) then
+ wave_q_out <= w;
+ end if;
+ else
+ wave_q_out <= w;
+ end if;
+
+ if rising_edge(clk) then
+ z := zero_q;
+ inv := inv_q;
+ end if;
+
+ end process;
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/radio/nco/src/waverom_dual.vhd b/lib/radio/nco/src/waverom_dual.vhd
new file mode 100644
index 0000000..4824eb0
--- /dev/null
+++ b/lib/radio/nco/src/waverom_dual.vhd
@@ -0,0 +1,86 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:16:14 10/02/05
+-- Design Name:
+-- Module Name: cordic_stage - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.nco_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity waverom_dual is
+Generic
+(
+ nbits_wave : integer := 12;
+ nbits_wave_frac : integer := 12;
+ nbits_rom_depth : integer := 12
+);
+Port
+(
+ clk : in std_logic;
+ addr_i : in unsigned(nbits_rom_depth-1 downto 0);
+ addr_q : in unsigned(nbits_rom_depth-1 downto 0);
+ wave_i_out : out sfixed;
+ wave_q_out : out sfixed
+);
+end waverom_dual;
+
+architecture Behavioral of waverom_dual is
+
+-------------------------------------------------------------------------------
+constant rom_depth : integer := 2**nbits_rom_depth;
+type wave_mem_t is array (0 to rom_depth-1) of sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
+
+constant sfixed_proto : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low) := (others => '0');
+
+-------------------------------------------------------------------------------
+function to_wave_mem(wave_real : real_array_t; len : integer; proto : sfixed) return wave_mem_t is
+variable res : wave_mem_t;
+begin
+ for i in 0 to len-1 loop
+ res(i) := to_sfixed(wave_real(i), proto, fixed_round, fixed_saturate);
+ end loop;
+
+ return res;
+end to_wave_mem;
+
+-------------------------------------------------------------------------------
+-- Create ROM
+constant real_wave_tbl : real_array_t(0 to rom_depth-1) := cos_tbl(rom_depth, 0.25/real(rom_depth), 0.0);
+constant wave_tbl : wave_mem_t := to_wave_mem(real_wave_tbl, rom_depth, sfixed_proto);
+
+-------------------------------------------------------------------------------
+begin
+
+-------------------------------------------------------------------------------
+proc_wave: process(clk)
+ begin
+ if rising_edge(clk) then
+ wave_i_out <= wave_tbl(to_integer(addr_i));
+ wave_q_out <= wave_tbl(to_integer(addr_q));
+ end if;
+ end process;
+
+------------------------------------------------------------
+end Behavioral;
diff --git a/lib/uart/bbfifo_16x8.vhd b/lib/uart/bbfifo_16x8.vhd
new file mode 100644
index 0000000..d6604a6
--- /dev/null
+++ b/lib/uart/bbfifo_16x8.vhd
@@ -0,0 +1,281 @@
+-- 'Bucket Brigade' FIFO
+-- 16 deep
+-- 8-bit data
+--
+-- Version : 1.10
+-- Version Date : 3rd December 2003
+-- Reason : '--translate' directives changed to '--synthesis translate' directives
+--
+-- Version : 1.00
+-- Version Date : 14th October 2002
+--
+-- Start of design entry : 14th October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for BBFIFO_16x8
+--
+entity bbfifo_16x8 is
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ reset : in std_logic;
+ write : in std_logic;
+ read : in std_logic;
+ full : out std_logic;
+ half_full : out std_logic;
+ data_present : out std_logic;
+ clk : in std_logic);
+ end bbfifo_16x8;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for BBFIFO_16x8
+--
+architecture low_level_definition of bbfifo_16x8 is
+--
+------------------------------------------------------------------------------------
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in BBFIFO_16x8
+--
+------------------------------------------------------------------------------------
+--
+signal pointer : std_logic_vector(3 downto 0);
+signal next_count : std_logic_vector(3 downto 0);
+signal half_count : std_logic_vector(3 downto 0);
+signal count_carry : std_logic_vector(2 downto 0);
+
+signal pointer_zero : std_logic;
+signal pointer_full : std_logic;
+signal decode_data_present : std_logic;
+signal data_present_int : std_logic;
+signal valid_write : std_logic;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- Attributes to define LUT contents during implementation
+-- The information is repeated in the generic map for functional simulation--
+--
+------------------------------------------------------------------------------------
+--
+attribute INIT : string;
+attribute INIT of zero_lut : label is "0001";
+attribute INIT of full_lut : label is "8000";
+attribute INIT of dp_lut : label is "BFA0";
+attribute INIT of valid_lut : label is "C4";
+--
+------------------------------------------------------------------------------------
+--
+-- Start of BBFIFO_16x8 circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- SRL16E data storage
+
+ data_width_loop: for i in 0 to 7 generate
+ --
+ attribute INIT : string;
+ attribute INIT of data_srl : label is "0000";
+ --
+ begin
+
+ data_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => data_in(i),
+ CE => valid_write,
+ CLK => clk,
+ A0 => pointer(0),
+ A1 => pointer(1),
+ A2 => pointer(2),
+ A3 => pointer(3),
+ Q => data_out(i) );
+
+ end generate data_width_loop;
+
+ -- 4-bit counter to act as data pointer
+ -- Counter is clock enabled by 'data_present'
+ -- Counter will be reset when 'reset' is active
+ -- Counter will increment when 'valid_write' is active
+
+ count_width_loop: for i in 0 to 3 generate
+ --
+ attribute INIT : string;
+ attribute INIT of count_lut : label is "6606";
+ --
+ begin
+
+ register_bit: FDRE
+ port map ( D => next_count(i),
+ Q => pointer(i),
+ CE => data_present_int,
+ R => reset,
+ C => clk);
+
+ count_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"6606")
+ --synthesis translate_on
+ port map( I0 => pointer(i),
+ I1 => read,
+ I2 => pointer_zero,
+ I3 => write,
+ O => half_count(i));
+
+ lsb_count: if i=0 generate
+ begin
+
+ count_muxcy: MUXCY
+ port map( DI => pointer(i),
+ CI => valid_write,
+ S => half_count(i),
+ O => count_carry(i));
+
+ count_xor: XORCY
+ port map( LI => half_count(i),
+ CI => valid_write,
+ O => next_count(i));
+
+ end generate lsb_count;
+
+ mid_count: if i>0 and i<3 generate
+ begin
+
+ count_muxcy: MUXCY
+ port map( DI => pointer(i),
+ CI => count_carry(i-1),
+ S => half_count(i),
+ O => count_carry(i));
+
+ count_xor: XORCY
+ port map( LI => half_count(i),
+ CI => count_carry(i-1),
+ O => next_count(i));
+
+ end generate mid_count;
+
+ upper_count: if i=3 generate
+ begin
+
+ count_xor: XORCY
+ port map( LI => half_count(i),
+ CI => count_carry(i-1),
+ O => next_count(i));
+
+ end generate upper_count;
+
+ end generate count_width_loop;
+
+
+ -- Detect when pointer is zero and maximum
+
+ zero_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0001")
+ --synthesis translate_on
+ port map( I0 => pointer(0),
+ I1 => pointer(1),
+ I2 => pointer(2),
+ I3 => pointer(3),
+ O => pointer_zero );
+
+
+ full_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"8000")
+ --synthesis translate_on
+ port map( I0 => pointer(0),
+ I1 => pointer(1),
+ I2 => pointer(2),
+ I3 => pointer(3),
+ O => pointer_full );
+
+
+ -- Data Present status
+
+ dp_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"BFA0")
+ --synthesis translate_on
+ port map( I0 => write,
+ I1 => read,
+ I2 => pointer_zero,
+ I3 => data_present_int,
+ O => decode_data_present );
+
+ dp_flop: FDR
+ port map ( D => decode_data_present,
+ Q => data_present_int,
+ R => reset,
+ C => clk);
+
+ -- Valid write signal
+
+ valid_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"C4")
+ --synthesis translate_on
+ port map( I0 => pointer_full,
+ I1 => write,
+ I2 => read,
+ O => valid_write );
+
+
+ -- assign internal signals to outputs
+
+ full <= pointer_full;
+ half_full <= pointer(3);
+ data_present <= data_present_int;
+
+end low_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE BBFIFO_16x8.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/lib/uart/kcuart_rx.vhd b/lib/uart/kcuart_rx.vhd
new file mode 100644
index 0000000..a7ac1a2
--- /dev/null
+++ b/lib/uart/kcuart_rx.vhd
@@ -0,0 +1,352 @@
+-- Constant (K) Compact UART Receiver
+--
+-- Version : 1.10
+-- Version Date : 3rd December 2003
+-- Reason : '--translate' directives changed to '--synthesis translate' directives
+--
+-- Version : 1.00
+-- Version Date : 16th October 2002
+--
+-- Start of design entry : 16th October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for KCUART_RX
+--
+entity kcuart_rx is
+ Port ( serial_in : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ data_strobe : out std_logic;
+ en_16_x_baud : in std_logic;
+ clk : in std_logic);
+ end kcuart_rx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for KCUART_RX
+--
+architecture low_level_definition of kcuart_rx is
+--
+------------------------------------------------------------------------------------
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in KCUART_RX
+--
+------------------------------------------------------------------------------------
+--
+signal sync_serial : std_logic;
+signal stop_bit : std_logic;
+signal data_int : std_logic_vector(7 downto 0);
+signal data_delay : std_logic_vector(7 downto 0);
+signal start_delay : std_logic;
+signal start_bit : std_logic;
+signal edge_delay : std_logic;
+signal start_edge : std_logic;
+signal decode_valid_char : std_logic;
+signal valid_char : std_logic;
+signal decode_purge : std_logic;
+signal purge : std_logic;
+signal valid_srl_delay : std_logic_vector(8 downto 0);
+signal valid_reg_delay : std_logic_vector(8 downto 0);
+signal decode_data_strobe : std_logic;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- Attributes to define LUT contents during implementation
+-- The information is repeated in the generic map for functional simulation--
+--
+------------------------------------------------------------------------------------
+--
+attribute INIT : string;
+attribute INIT of start_srl : label is "0000";
+attribute INIT of edge_srl : label is "0000";
+attribute INIT of valid_lut : label is "0040";
+attribute INIT of purge_lut : label is "54";
+attribute INIT of strobe_lut : label is "8";
+--
+------------------------------------------------------------------------------------
+--
+-- Start of KCUART_RX circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- Synchronise input serial data to system clock
+
+ sync_reg: FD
+ port map ( D => serial_in,
+ Q => sync_serial,
+ C => clk);
+
+ stop_reg: FD
+ port map ( D => sync_serial,
+ Q => stop_bit,
+ C => clk);
+
+
+ -- Data delays to capture data at 16 time baud rate
+ -- Each SRL16E is followed by a flip-flop for best timing
+
+ data_loop: for i in 0 to 7 generate
+ begin
+
+ lsbs: if i<7 generate
+ --
+ attribute INIT : string;
+ attribute INIT of delay15_srl : label is "0000";
+ --
+ begin
+
+ delay15_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => data_int(i+1),
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '0',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => data_delay(i) );
+
+ end generate lsbs;
+
+ msb: if i=7 generate
+ --
+ attribute INIT : string;
+ attribute INIT of delay15_srl : label is "0000";
+ --
+ begin
+
+ delay15_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => stop_bit,
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '0',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => data_delay(i) );
+
+ end generate msb;
+
+ data_reg: FDE
+ port map ( D => data_delay(i),
+ Q => data_int(i),
+ CE => en_16_x_baud,
+ C => clk);
+
+ end generate data_loop;
+
+ -- Assign internal signals to outputs
+
+ data_out <= data_int;
+
+ -- Data delays to capture start bit at 16 time baud rate
+
+ start_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => data_int(0),
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '0',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => start_delay );
+
+ start_reg: FDE
+ port map ( D => start_delay,
+ Q => start_bit,
+ CE => en_16_x_baud,
+ C => clk);
+
+
+ -- Data delays to capture start bit leading edge at 16 time baud rate
+ -- Delay ensures data is captured at mid-bit position
+
+ edge_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => start_bit,
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '1',
+ A1 => '0',
+ A2 => '1',
+ A3 => '0',
+ Q => edge_delay );
+
+ edge_reg: FDE
+ port map ( D => edge_delay,
+ Q => start_edge,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Detect a valid character
+
+ valid_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0040")
+ --synthesis translate_on
+ port map( I0 => purge,
+ I1 => stop_bit,
+ I2 => start_edge,
+ I3 => edge_delay,
+ O => decode_valid_char );
+
+ valid_reg: FDE
+ port map ( D => decode_valid_char,
+ Q => valid_char,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Purge of data status
+
+ purge_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"54")
+ --synthesis translate_on
+ port map( I0 => valid_reg_delay(8),
+ I1 => valid_char,
+ I2 => purge,
+ O => decode_purge );
+
+ purge_reg: FDE
+ port map ( D => decode_purge,
+ Q => purge,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Delay of valid_char pulse of length equivalent to the time taken
+ -- to purge data shift register of all data which has been used.
+ -- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
+ -- up to 16 delays and utilising the dedicated flip flop in each stage.
+
+ valid_loop: for i in 0 to 8 generate
+ begin
+
+ lsb: if i=0 generate
+ --
+ attribute INIT : string;
+ attribute INIT of delay15_srl : label is "0000";
+ --
+ begin
+
+ delay15_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => valid_char,
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '0',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => valid_srl_delay(i) );
+
+ end generate lsb;
+
+ msbs: if i>0 generate
+ --
+ attribute INIT : string;
+ attribute INIT of delay16_srl : label is "0000";
+ --
+ begin
+
+ delay16_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => valid_reg_delay(i-1),
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '1',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => valid_srl_delay(i) );
+
+ end generate msbs;
+
+ data_reg: FDE
+ port map ( D => valid_srl_delay(i),
+ Q => valid_reg_delay(i),
+ CE => en_16_x_baud,
+ C => clk);
+
+ end generate valid_loop;
+
+ -- Form data strobe
+
+ strobe_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"8")
+ --synthesis translate_on
+ port map( I0 => valid_char,
+ I1 => en_16_x_baud,
+ O => decode_data_strobe );
+
+ strobe_reg: FD
+ port map ( D => decode_data_strobe,
+ Q => data_strobe,
+ C => clk);
+
+end low_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE KCUART_RX.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/lib/uart/kcuart_tx.vhd b/lib/uart/kcuart_tx.vhd
new file mode 100644
index 0000000..556ac58
--- /dev/null
+++ b/lib/uart/kcuart_tx.vhd
@@ -0,0 +1,394 @@
+-- Constant (K) Compact UART Transmitter
+--
+-- Version : 1.10
+-- Version Date : 3rd December 2003
+-- Reason : '--translate' directives changed to '--synthesis translate' directives
+--
+-- Version : 1.00
+-- Version Date : 14th October 2002
+--
+-- Start of design entry : 2nd October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for KCUART_TX
+--
+entity kcuart_tx is
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ send_character : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ Tx_complete : out std_logic;
+ clk : in std_logic);
+ end kcuart_tx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for KCUART_TX
+--
+architecture low_level_definition of kcuart_tx is
+--
+------------------------------------------------------------------------------------
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in KCUART_TX
+--
+------------------------------------------------------------------------------------
+--
+signal data_01 : std_logic;
+signal data_23 : std_logic;
+signal data_45 : std_logic;
+signal data_67 : std_logic;
+signal data_0123 : std_logic;
+signal data_4567 : std_logic;
+signal data_01234567 : std_logic;
+signal bit_select : std_logic_vector(2 downto 0);
+signal next_count : std_logic_vector(2 downto 0);
+signal mask_count : std_logic_vector(2 downto 0);
+signal mask_count_carry : std_logic_vector(2 downto 0);
+signal count_carry : std_logic_vector(2 downto 0);
+signal ready_to_start : std_logic;
+signal decode_Tx_start : std_logic;
+signal Tx_start : std_logic;
+signal decode_Tx_run : std_logic;
+signal Tx_run : std_logic;
+signal decode_hot_state : std_logic;
+signal hot_state : std_logic;
+signal hot_delay : std_logic;
+signal Tx_bit : std_logic;
+signal decode_Tx_stop : std_logic;
+signal Tx_stop : std_logic;
+signal decode_Tx_complete : std_logic;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- Attributes to define LUT contents during implementation
+-- The information is repeated in the generic map for functional simulation--
+--
+------------------------------------------------------------------------------------
+--
+attribute INIT : string;
+attribute INIT of mux1_lut : label is "E4FF";
+attribute INIT of mux2_lut : label is "E4FF";
+attribute INIT of mux3_lut : label is "E4FF";
+attribute INIT of mux4_lut : label is "E4FF";
+attribute INIT of ready_lut : label is "10";
+attribute INIT of start_lut : label is "0190";
+attribute INIT of run_lut : label is "1540";
+attribute INIT of hot_state_lut : label is "94";
+attribute INIT of delay14_srl : label is "0000";
+attribute INIT of stop_lut : label is "0180";
+attribute INIT of complete_lut : label is "8";
+--
+------------------------------------------------------------------------------------
+--
+-- Start of KCUART_TX circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- 8 to 1 multiplexer to convert parallel data to serial
+
+ mux1_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"E4FF")
+ --synthesis translate_on
+ port map( I0 => bit_select(0),
+ I1 => data_in(0),
+ I2 => data_in(1),
+ I3 => Tx_run,
+ O => data_01 );
+
+ mux2_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"E4FF")
+ --synthesis translate_on
+ port map( I0 => bit_select(0),
+ I1 => data_in(2),
+ I2 => data_in(3),
+ I3 => Tx_run,
+ O => data_23 );
+
+ mux3_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"E4FF")
+ --synthesis translate_on
+ port map( I0 => bit_select(0),
+ I1 => data_in(4),
+ I2 => data_in(5),
+ I3 => Tx_run,
+ O => data_45 );
+
+ mux4_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"E4FF")
+ --synthesis translate_on
+ port map( I0 => bit_select(0),
+ I1 => data_in(6),
+ I2 => data_in(7),
+ I3 => Tx_run,
+ O => data_67 );
+
+ mux5_muxf5: MUXF5
+ port map( I1 => data_23,
+ I0 => data_01,
+ S => bit_select(1),
+ O => data_0123 );
+
+ mux6_muxf5: MUXF5
+ port map( I1 => data_67,
+ I0 => data_45,
+ S => bit_select(1),
+ O => data_4567 );
+
+ mux7_muxf6: MUXF6
+ port map( I1 => data_4567,
+ I0 => data_0123,
+ S => bit_select(2),
+ O => data_01234567 );
+
+ -- Register serial output and force start and stop bits
+
+ pipeline_serial: FDRS
+ port map ( D => data_01234567,
+ Q => serial_out,
+ R => Tx_start,
+ S => Tx_stop,
+ C => clk);
+
+ -- 3-bit counter
+ -- Counter is clock enabled by en_16_x_baud
+ -- Counter will be reset when 'Tx_start' is active
+ -- Counter will increment when Tx_bit is active
+ -- Tx_run must be active to count
+ -- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
+
+ count_width_loop: for i in 0 to 2 generate
+ --
+ attribute INIT : string;
+ attribute INIT of count_lut : label is "8";
+ --
+ begin
+
+ register_bit: FDRE
+ port map ( D => next_count(i),
+ Q => bit_select(i),
+ CE => en_16_x_baud,
+ R => Tx_start,
+ C => clk);
+
+ count_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"8")
+ --synthesis translate_on
+ port map( I0 => bit_select(i),
+ I1 => Tx_run,
+ O => mask_count(i));
+
+ mask_and: MULT_AND
+ port map( I0 => bit_select(i),
+ I1 => Tx_run,
+ LO => mask_count_carry(i));
+
+ lsb_count: if i=0 generate
+ begin
+
+ count_muxcy: MUXCY
+ port map( DI => mask_count_carry(i),
+ CI => Tx_bit,
+ S => mask_count(i),
+ O => count_carry(i));
+
+ count_xor: XORCY
+ port map( LI => mask_count(i),
+ CI => Tx_bit,
+ O => next_count(i));
+
+ end generate lsb_count;
+
+ upper_count: if i>0 generate
+ begin
+
+ count_muxcy: MUXCY
+ port map( DI => mask_count_carry(i),
+ CI => count_carry(i-1),
+ S => mask_count(i),
+ O => count_carry(i));
+
+ count_xor: XORCY
+ port map( LI => mask_count(i),
+ CI => count_carry(i-1),
+ O => next_count(i));
+
+ end generate upper_count;
+
+ end generate count_width_loop;
+
+ -- Ready to start decode
+
+ ready_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"10")
+ --synthesis translate_on
+ port map( I0 => Tx_run,
+ I1 => Tx_start,
+ I2 => send_character,
+ O => ready_to_start );
+
+ -- Start bit enable
+
+ start_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0190")
+ --synthesis translate_on
+ port map( I0 => Tx_bit,
+ I1 => Tx_stop,
+ I2 => ready_to_start,
+ I3 => Tx_start,
+ O => decode_Tx_start );
+
+ Tx_start_reg: FDE
+ port map ( D => decode_Tx_start,
+ Q => Tx_start,
+ CE => en_16_x_baud,
+ C => clk);
+
+
+ -- Run bit enable
+
+ run_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"1540")
+ --synthesis translate_on
+ port map( I0 => count_carry(2),
+ I1 => Tx_bit,
+ I2 => Tx_start,
+ I3 => Tx_run,
+ O => decode_Tx_run );
+
+ Tx_run_reg: FDE
+ port map ( D => decode_Tx_run,
+ Q => Tx_run,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Bit rate enable
+
+ hot_state_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"94")
+ --synthesis translate_on
+ port map( I0 => Tx_stop,
+ I1 => ready_to_start,
+ I2 => Tx_bit,
+ O => decode_hot_state );
+
+ hot_state_reg: FDE
+ port map ( D => decode_hot_state,
+ Q => hot_state,
+ CE => en_16_x_baud,
+ C => clk);
+
+ delay14_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => hot_state,
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '1',
+ A1 => '0',
+ A2 => '1',
+ A3 => '1',
+ Q => hot_delay );
+
+ Tx_bit_reg: FDE
+ port map ( D => hot_delay,
+ Q => Tx_bit,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Stop bit enable
+
+ stop_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0180")
+ --synthesis translate_on
+ port map( I0 => Tx_bit,
+ I1 => Tx_run,
+ I2 => count_carry(2),
+ I3 => Tx_stop,
+ O => decode_Tx_stop );
+
+ Tx_stop_reg: FDE
+ port map ( D => decode_Tx_stop,
+ Q => Tx_stop,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Tx_complete strobe
+
+ complete_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"8")
+ --synthesis translate_on
+ port map( I0 => count_carry(2),
+ I1 => en_16_x_baud,
+ O => decode_Tx_complete );
+
+ Tx_complete_reg: FD
+ port map ( D => decode_Tx_complete,
+ Q => Tx_complete,
+ C => clk);
+
+
+end low_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE KCUART_TX.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/lib/uart/uart_rx.vhd b/lib/uart/uart_rx.vhd
new file mode 100644
index 0000000..69eb70e
--- /dev/null
+++ b/lib/uart/uart_rx.vhd
@@ -0,0 +1,146 @@
+-- UART Receiver with integral 16 byte FIFO buffer
+--
+-- 8 bit, no parity, 1 stop bit
+--
+-- Version : 1.00
+-- Version Date : 16th October 2002
+--
+-- Start of design entry : 16th October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for UART_RX
+--
+entity uart_rx is
+ Port ( serial_in : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ read_buffer : in std_logic;
+ reset_buffer : in std_logic;
+ en_16_x_baud : in std_logic;
+ buffer_data_present : out std_logic;
+ buffer_full : out std_logic;
+ buffer_half_full : out std_logic;
+ clk : in std_logic);
+ end uart_rx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for UART_RX
+--
+architecture macro_level_definition of uart_rx is
+--
+------------------------------------------------------------------------------------
+--
+-- Components used in UART_RX and defined in subsequent entities.
+--
+------------------------------------------------------------------------------------
+--
+-- Constant (K) Compact UART Receiver
+--
+component kcuart_rx
+ Port ( serial_in : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ data_strobe : out std_logic;
+ en_16_x_baud : in std_logic;
+ clk : in std_logic);
+ end component;
+--
+-- 'Bucket Brigade' FIFO
+--
+component bbfifo_16x8
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ reset : in std_logic;
+ write : in std_logic;
+ read : in std_logic;
+ full : out std_logic;
+ half_full : out std_logic;
+ data_present : out std_logic;
+ clk : in std_logic);
+ end component;
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in UART_RX
+--
+------------------------------------------------------------------------------------
+--
+signal uart_data_out : std_logic_vector(7 downto 0);
+signal fifo_write : std_logic;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of UART_RX circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- 8 to 1 multiplexer to convert parallel data to serial
+
+ kcuart: kcuart_rx
+ port map ( serial_in => serial_in,
+ data_out => uart_data_out,
+ data_strobe => fifo_write,
+ en_16_x_baud => en_16_x_baud,
+ clk => clk );
+
+
+ buf: bbfifo_16x8
+ port map ( data_in => uart_data_out,
+ data_out => data_out,
+ reset => reset_buffer,
+ write => fifo_write,
+ read => read_buffer,
+ full => buffer_full,
+ half_full => buffer_half_full,
+ data_present => buffer_data_present,
+ clk => clk);
+
+end macro_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_RX.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/lib/uart/uart_tx.vhd b/lib/uart/uart_tx.vhd
new file mode 100644
index 0000000..8c4e63d
--- /dev/null
+++ b/lib/uart/uart_tx.vhd
@@ -0,0 +1,148 @@
+-- UART Transmitter with integral 16 byte FIFO buffer
+--
+-- 8 bit, no parity, 1 stop bit
+--
+-- Version : 1.00
+-- Version Date : 14th October 2002
+--
+-- Start of design entry : 14th October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for UART_TX
+--
+entity uart_tx is
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ write_buffer : in std_logic;
+ reset_buffer : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ buffer_full : out std_logic;
+ buffer_half_full : out std_logic;
+ clk : in std_logic);
+ end uart_tx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for UART_TX
+--
+architecture macro_level_definition of uart_tx is
+--
+------------------------------------------------------------------------------------
+--
+-- Components used in UART_TX and defined in subsequent entities.
+--
+------------------------------------------------------------------------------------
+--
+-- Constant (K) Compact UART Transmitter
+--
+component kcuart_tx
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ send_character : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ Tx_complete : out std_logic;
+ clk : in std_logic);
+ end component;
+--
+-- 'Bucket Brigade' FIFO
+--
+component bbfifo_16x8
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ reset : in std_logic;
+ write : in std_logic;
+ read : in std_logic;
+ full : out std_logic;
+ half_full : out std_logic;
+ data_present : out std_logic;
+ clk : in std_logic);
+ end component;
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in UART_TX
+--
+------------------------------------------------------------------------------------
+--
+signal fifo_data_out : std_logic_vector(7 downto 0);
+signal fifo_data_present : std_logic;
+signal fifo_read : std_logic;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of UART_TX circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- 8 to 1 multiplexer to convert parallel data to serial
+
+ kcuart: kcuart_tx
+ port map ( data_in => fifo_data_out,
+ send_character => fifo_data_present,
+ en_16_x_baud => en_16_x_baud,
+ serial_out => serial_out,
+ Tx_complete => fifo_read,
+ clk => clk);
+
+
+ buf: bbfifo_16x8
+ port map ( data_in => data_in,
+ data_out => fifo_data_out,
+ reset => reset_buffer,
+ write => write_buffer,
+ read => fifo_read,
+ full => buffer_full,
+ half_full => buffer_half_full,
+ data_present => fifo_data_present,
+ clk => clk);
+
+end macro_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_TX.VHD
+--
+------------------------------------------------------------------------------------
+
+