Initial import
git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,13 @@
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vlib work
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vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
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vcom -explicit -93 "../src/mix_pkg.vhd"
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vcom -explicit -93 "../src/mix_cpx.vhd"
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vcom -explicit -93 "../src/tb_mix_cpx.vhd"
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vsim -t 1ps -lib work tb_mix_cpx
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do {tb_mix_cpx.wdo}
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view wave
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view structure
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view signals
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run 500ns
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@@ -0,0 +1,42 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_mix_cpx/clk
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add wave -noupdate -format Logic /tb_mix_cpx/srst
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add wave -noupdate -divider {Fixed In}
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add wave -noupdate -format Logic /tb_mix_cpx/in_valid
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||||
add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_re_in
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add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_im_in
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||||
add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_re_in
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add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_im_in
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add wave -noupdate -divider {Fixed OUT}
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||||
add wave -noupdate -format Logic /tb_mix_cpx/out_valid
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add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_re_out
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||||
add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_im_out
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||||
add wave -noupdate -divider {Convenient real out}
|
||||
add wave -noupdate -format Literal /tb_mix_cpx/x_re
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add wave -noupdate -format Literal /tb_mix_cpx/x_im
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add wave -noupdate -format Literal /tb_mix_cpx/y_re
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add wave -noupdate -format Literal /tb_mix_cpx/y_im
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add wave -noupdate -format Literal /tb_mix_cpx/z_re
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add wave -noupdate -format Literal /tb_mix_cpx/z_im
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add wave -noupdate -format Logic /tb_mix_cpx/fileout_enable
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add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_left
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add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_right
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add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_left
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add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_right
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {90000 ps} 0}
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configure wave -namecolwidth 193
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {0 ps} {348406 ps}
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@@ -0,0 +1,13 @@
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vlib work
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vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
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vcom -explicit -93 "../src/mix_pkg.vhd"
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vcom -explicit -93 "../src/mix_real.vhd"
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vcom -explicit -93 "../src/tb_mix_real.vhd"
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vsim -t 1ps -lib work tb_mix_real
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do {tb_mix_real.wdo}
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view wave
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view structure
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view signals
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run 500ns
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@@ -0,0 +1,36 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_mix_real/clk
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add wave -noupdate -format Logic /tb_mix_real/srst
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add wave -noupdate -divider {Fixed In}
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add wave -noupdate -format Logic /tb_mix_real/in_valid
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add wave -noupdate -format Literal -radix decimal /tb_mix_real/x_re_din
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add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_re_din
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add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_im_din
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add wave -noupdate -divider {Fixed OUT}
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add wave -noupdate -format Logic /tb_mix_real/out_valid
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add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_re_dout
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add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_im_dout
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add wave -noupdate -divider {Convenient real out}
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add wave -noupdate -format Literal /tb_mix_real/x_re
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add wave -noupdate -format Literal /tb_mix_real/y_re
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add wave -noupdate -format Literal /tb_mix_real/y_im
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add wave -noupdate -format Literal /tb_mix_real/z_re
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add wave -noupdate -format Literal /tb_mix_real/z_im
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add wave -noupdate -format Logic /tb_mix_real/fileout_enable
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {120000 ps} 0}
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configure wave -namecolwidth 193
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {0 ps} {348406 ps}
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||||
@@ -0,0 +1,13 @@
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vlib work
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vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
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vcom -explicit -93 "../src/mix_pkg.vhd"
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vcom -explicit -93 "../src/undc_real.vhd"
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vcom -explicit -93 "../src/tb_undc_real.vhd"
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vsim -t 1ps -lib work tb_undc_real
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do {tb_undc_real.wdo}
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view wave
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view structure
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view signals
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run 500us
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@@ -0,0 +1,38 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_undc_real/clk
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add wave -noupdate -format Logic /tb_undc_real/srst
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add wave -noupdate -format Logic /tb_undc_real/din_valid
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add wave -noupdate -format Logic /tb_undc_real/kin_valid
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/din
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/kin
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dout
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dc_out
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add wave -noupdate -format Logic /tb_undc_real/dout_valid
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add wave -noupdate -format Literal /tb_undc_real/k
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add wave -noupdate -format Literal /tb_undc_real/x
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add wave -noupdate -format Literal /tb_undc_real/y
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add wave -noupdate -format Literal /tb_undc_real/dc
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add wave -noupdate -divider UUT
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/k
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/x
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y1
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y2
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add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/dc
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TreeUpdate [SetDefaultTree]
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||||
WaveRestoreCursors {{Cursor 1} {97905405 ps} 0}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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||||
configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {157500 ns}
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@@ -0,0 +1,166 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:16:14 10/02/05
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-- Design Name:
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-- Module Name: mix_cpx - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use work.fixed_pkg.all;
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use work.mix_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity mix_cpx is
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Generic
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(
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nbits_in : integer := 12;
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nbits_in_frac : integer := 12;
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nbits_out : integer := 12;
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nbits_out_frac : integer := 12;
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nbits_scale_z : integer := 0;
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has_in_reg : boolean := false;
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has_pipe_reg : boolean := false;
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has_out_reg : boolean := false;
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rounding : boolean := true;
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saturating : boolean := true
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);
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Port
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(
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srst : in std_logic;
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clk : in std_logic;
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in_valid : in std_logic;
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x_re_in : in sfixed;
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x_im_in : in sfixed;
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y_re_in : in sfixed;
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y_im_in : in sfixed;
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out_valid : out std_logic;
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z_re_out : out sfixed;
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z_im_out : out sfixed
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);
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end mix_cpx;
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architecture Behavioral of mix_cpx is
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constant nbits_prod : integer := nbits_out + nbits_scale_z;
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constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
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signal x_re, x_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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signal p_re_left, p_re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
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signal p_im_left, p_im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
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signal valid, p_valid : std_logic;
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------------------------------------------------------------
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begin
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------------------------------------------------------------
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proc_in_reg: process(srst, clk, in_valid, x_re_in, x_im_in, y_re_in, y_im_in)
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begin
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if has_in_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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x_re <= to_sfixed(0, x_re);
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x_im <= to_sfixed(0, x_im);
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y_re <= to_sfixed(0, y_re);
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y_im <= to_sfixed(0, y_im);
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valid <= '0';
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else
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valid <= in_valid;
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if in_valid = '1' then
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x_re <= x_re_in;
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x_im <= x_im_in;
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y_re <= y_re_in;
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y_im <= y_im_in;
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end if;
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end if;
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end if;
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else
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x_re <= x_re_in;
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x_im <= x_im_in;
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y_re <= y_re_in;
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y_im <= y_im_in;
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valid <= in_valid;
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end if;
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end process;
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------------------------------------------------------------
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proc_pipe_reg: process(srst, clk, valid, x_re, x_im, y_re, y_im)
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variable re_left, re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
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variable im_left, im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
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begin
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re_left := resize(x_re * y_re, re_left);
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re_right := resize(x_im * y_im, re_right);
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im_left := resize(x_re * y_im, im_left);
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im_right := resize(x_im * y_re, im_right);
|
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if has_pipe_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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p_re_left <= to_sfixed(0, p_re_left);
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p_re_right <= to_sfixed(0, p_re_right);
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p_im_left <= to_sfixed(0, p_im_left);
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p_im_right <= to_sfixed(0, p_im_right);
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p_valid <= '0';
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else
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p_re_left <= re_left;
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p_re_right <= re_right;
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p_im_left <= im_left;
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p_im_right <= im_right;
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p_valid <= valid;
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||||
end if;
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||||
end if;
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||||
else
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p_re_left <= re_left;
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p_re_right <= re_right;
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p_im_left <= im_left;
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p_im_right <= im_right;
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p_valid <= valid;
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||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_out_reg: process(srst, clk, p_valid, p_re_left, p_re_right, p_im_left, p_im_right)
|
||||
variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
begin
|
||||
sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, rounding, saturating);
|
||||
sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, rounding, saturating);
|
||||
if has_out_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
z_re_out <= to_sfixed(0, re);
|
||||
z_im_out <= to_sfixed(0, im);
|
||||
out_valid <= '0';
|
||||
else
|
||||
z_re_out <= sum_re;
|
||||
z_im_out <= sum_im;
|
||||
out_valid <= p_valid;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
z_re_out <= re;
|
||||
z_im_out <= im;
|
||||
out_valid <= p_valid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,62 @@
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
use work.fixed_pkg.all;
|
||||
|
||||
package mix_pkg is
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Constructor helpers
|
||||
-- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
|
||||
function uproto (nbits : integer; nbits_frac : integer) return ufixed;
|
||||
|
||||
-- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
|
||||
function sproto (nbits : integer; nbits_frac : integer) return sfixed;
|
||||
|
||||
function to_unsigned (src : ufixed) return UNSIGNED;
|
||||
function to_signed (src : sfixed) return SIGNED;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
end; -- package mix_cpx_pkg;
|
||||
|
||||
package body mix_pkg is
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Constuctor helpers
|
||||
function uproto (nbits : integer; nbits_frac : integer) return ufixed is
|
||||
constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0');
|
||||
begin
|
||||
return result(nbits-nbits_frac-1 downto -nbits_frac);
|
||||
end uproto;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function sproto (nbits : integer; nbits_frac : integer) return sfixed is
|
||||
constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0');
|
||||
begin
|
||||
return result(nbits-nbits_frac downto -nbits_frac+1);
|
||||
end sproto;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function to_unsigned (src : ufixed) return UNSIGNED is
|
||||
subtype t is UNSIGNED(src'high - src'low downto 0);
|
||||
variable slv : t;
|
||||
begin
|
||||
slv := t(src);
|
||||
return UNSIGNED(to_X01(std_logic_vector(slv)));
|
||||
|
||||
end function to_unsigned;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function to_signed (src : sfixed) return SIGNED is
|
||||
subtype t is SIGNED(src'high - src'low downto 0);
|
||||
variable slv : t;
|
||||
begin
|
||||
slv := t(src);
|
||||
return SIGNED(to_X01(std_logic_vector(slv)));
|
||||
|
||||
end function to_signed;
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
end; -- package mix_pkg;
|
||||
@@ -0,0 +1,155 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: mix_cpx - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
entity mix_real is
|
||||
Generic
|
||||
(
|
||||
nbits_in : integer := 12;
|
||||
nbits_in_frac : integer := 12;
|
||||
nbits_out : integer := 12;
|
||||
nbits_out_frac : integer := 12;
|
||||
nbits_scale_z : integer := 0;
|
||||
has_in_reg : boolean := false;
|
||||
has_pipe_reg : boolean := false;
|
||||
has_out_reg : boolean := false;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
in_valid : in std_logic;
|
||||
x_re_din : in sfixed;
|
||||
y_re_din : in sfixed;
|
||||
y_im_din : in sfixed;
|
||||
out_valid : out std_logic;
|
||||
z_re_dout : out sfixed;
|
||||
z_im_dout : out sfixed
|
||||
);
|
||||
end mix_real;
|
||||
|
||||
architecture Behavioral of mix_real is
|
||||
|
||||
constant nbits_prod : integer := nbits_out + nbits_scale_z;
|
||||
constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
|
||||
|
||||
signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
|
||||
signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
|
||||
signal valid, p_valid : std_logic;
|
||||
------------------------------------------------------------
|
||||
begin
|
||||
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din)
|
||||
begin
|
||||
if has_in_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
x_re <= to_sfixed(0, x_re);
|
||||
y_re <= to_sfixed(0, y_re);
|
||||
y_im <= to_sfixed(0, y_im);
|
||||
valid <= '0';
|
||||
else
|
||||
valid <= in_valid;
|
||||
if in_valid = '1' then
|
||||
x_re <= x_re_din;
|
||||
y_re <= y_re_din;
|
||||
y_im <= y_im_din;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
x_re <= x_re_din;
|
||||
y_re <= y_re_din;
|
||||
y_im <= y_im_din;
|
||||
valid <= in_valid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im)
|
||||
variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
|
||||
variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
|
||||
|
||||
begin
|
||||
re_left := resize(x_re * y_re, re_left);
|
||||
im_left := resize(x_re * y_im, im_left);
|
||||
if has_pipe_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
p_re_left <= to_sfixed(0, p_re_left);
|
||||
p_im_left <= to_sfixed(0, p_im_left);
|
||||
p_valid <= '0';
|
||||
else
|
||||
p_re_left <= re_left;
|
||||
p_im_left <= im_left;
|
||||
p_valid <= valid;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
p_re_left <= re_left;
|
||||
p_im_left <= im_left;
|
||||
p_valid <= valid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left)
|
||||
variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
begin
|
||||
sum_re := resize(scalb(p_re_left, nbits_scale_z), re, rounding, saturating);
|
||||
sum_im := resize(scalb(p_im_left, nbits_scale_z), im, rounding, saturating);
|
||||
if has_out_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
z_re_dout <= to_sfixed(0, re);
|
||||
z_im_dout <= to_sfixed(0, im);
|
||||
out_valid <= '0';
|
||||
else
|
||||
z_re_dout <= sum_re;
|
||||
z_im_dout <= sum_im;
|
||||
out_valid <= p_valid;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
z_re_dout <= re;
|
||||
z_im_dout <= im;
|
||||
out_valid <= p_valid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,208 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
use work.PCK_FIO.all;
|
||||
|
||||
ENTITY tb_mix_cpx IS
|
||||
Generic (
|
||||
nbits_in : integer := 24;
|
||||
nbits_in_frac : integer := 24;
|
||||
nbits_out : integer := 24;
|
||||
nbits_out_frac : integer := 24;
|
||||
nbits_scale_z : integer := 0;
|
||||
has_in_reg : boolean := true;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
END tb_mix_cpx;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mix_cpx IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT mix_cpx
|
||||
GENERIC
|
||||
(
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
nbits_scale_z : integer;
|
||||
has_in_reg : boolean;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
PORT
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
in_valid : in std_logic;
|
||||
x_re_in : in sfixed;
|
||||
x_im_in : in sfixed;
|
||||
y_re_in : in sfixed;
|
||||
y_im_in : in sfixed;
|
||||
out_valid : out std_logic;
|
||||
z_re_out : out sfixed;
|
||||
z_im_out : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL in_valid : std_logic := '0';
|
||||
SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
|
||||
--Outputs
|
||||
SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL out_valid : std_logic;
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
SIGNAL x_re : real := 0.0;
|
||||
SIGNAL x_im : real := 0.0;
|
||||
SIGNAL y_re : real := 0.0;
|
||||
SIGNAL y_im : real := 0.0;
|
||||
SIGNAL z_re : real := 0.0;
|
||||
SIGNAL z_im : real := 0.0;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: mix_cpx
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
nbits_scale_z => nbits_scale_z,
|
||||
has_in_reg => has_in_reg,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => srst,
|
||||
clk => clk,
|
||||
in_valid => in_valid,
|
||||
x_re_in => x_re_in,
|
||||
x_im_in => x_im_in,
|
||||
y_re_in => y_re_in,
|
||||
y_im_in => y_im_in,
|
||||
out_valid => out_valid,
|
||||
z_re_out => z_re_out,
|
||||
z_im_out => z_im_out
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.5, x_re_in);
|
||||
x_im_in <= to_sfixed(0.5, x_im_in);
|
||||
y_re_in <= to_sfixed(0.5, y_re_in);
|
||||
y_im_in <= to_sfixed(0.5, y_im_in);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 5*PERIOD;
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.125, x_re_in);
|
||||
x_im_in <= to_sfixed(0.25, x_im_in);
|
||||
y_re_in <= to_sfixed(0.25, y_re_in);
|
||||
y_im_in <= to_sfixed(0.125, y_im_in);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 5*PERIOD;
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.125, x_re_in);
|
||||
x_im_in <= to_sfixed(-0.25, x_im_in);
|
||||
y_re_in <= to_sfixed(0.25, y_re_in);
|
||||
y_im_in <= to_sfixed(0.125, y_im_in);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.125, x_re_in);
|
||||
x_im_in <= to_sfixed(-0.25, x_im_in);
|
||||
y_re_in <= to_sfixed(0.25, y_re_in);
|
||||
y_im_in <= to_sfixed(0.125, y_im_in);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.3, x_re_in);
|
||||
x_im_in <= to_sfixed(0.0, x_im_in);
|
||||
y_re_in <= to_sfixed(-0.5, y_re_in);
|
||||
y_im_in <= to_sfixed(0.5, y_im_in);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_in <= to_sfixed(0.0, x_re_in);
|
||||
x_im_in <= to_sfixed(-0.7071, x_im_in);
|
||||
y_re_in <= to_sfixed(0.0, y_re_in);
|
||||
y_im_in <= to_sfixed(-0.7071, y_im_in);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
x_re <= to_real(x_re_in);
|
||||
x_im <= to_real(x_im_in);
|
||||
y_re <= to_real(y_re_in);
|
||||
y_im <= to_real(y_im_in);
|
||||
z_re <= to_real(z_re_out);
|
||||
z_im <= to_real(z_im_out);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,197 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
use work.PCK_FIO.all;
|
||||
|
||||
ENTITY tb_mix_real IS
|
||||
Generic (
|
||||
nbits_in : integer := 24;
|
||||
nbits_in_frac : integer := 24;
|
||||
nbits_out : integer := 24;
|
||||
nbits_out_frac : integer := 24;
|
||||
nbits_scale_z : integer := 0;
|
||||
has_in_reg : boolean := true;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
END tb_mix_real;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mix_real IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT mix_real
|
||||
GENERIC
|
||||
(
|
||||
nbits_in : integer;
|
||||
nbits_in_frac : integer;
|
||||
nbits_out : integer;
|
||||
nbits_out_frac : integer;
|
||||
nbits_scale_z : integer;
|
||||
has_in_reg : boolean;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
PORT
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
in_valid : in std_logic;
|
||||
x_re_din : in sfixed;
|
||||
y_re_din : in sfixed;
|
||||
y_im_din : in sfixed;
|
||||
out_valid : out std_logic;
|
||||
z_re_dout : out sfixed;
|
||||
z_im_dout : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL in_valid : std_logic := '0';
|
||||
SIGNAL x_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
SIGNAL y_im_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
|
||||
|
||||
--Outputs
|
||||
SIGNAL z_re_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL z_im_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
|
||||
SIGNAL out_valid : std_logic;
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
SIGNAL x_re : real := 0.0;
|
||||
SIGNAL y_re : real := 0.0;
|
||||
SIGNAL y_im : real := 0.0;
|
||||
SIGNAL z_re : real := 0.0;
|
||||
SIGNAL z_im : real := 0.0;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: mix_real
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_in => nbits_in,
|
||||
nbits_in_frac => nbits_in_frac,
|
||||
nbits_out => nbits_out,
|
||||
nbits_out_frac => nbits_out_frac,
|
||||
nbits_scale_z => nbits_scale_z,
|
||||
has_in_reg => has_in_reg,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => srst,
|
||||
clk => clk,
|
||||
in_valid => in_valid,
|
||||
x_re_din => x_re_din,
|
||||
y_re_din => y_re_din,
|
||||
y_im_din => y_im_din,
|
||||
out_valid => out_valid,
|
||||
z_re_dout => z_re_dout,
|
||||
z_im_dout => z_im_dout
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.5, x_re_din);
|
||||
y_re_din <= to_sfixed(0.5, y_re_din);
|
||||
y_im_din <= to_sfixed(0.5, y_im_din);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 5*PERIOD;
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.125, x_re_din);
|
||||
y_re_din <= to_sfixed(0.25, y_re_din);
|
||||
y_im_din <= to_sfixed(0.125, y_im_din);
|
||||
in_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
wait for 5*PERIOD;
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.125, x_re_din);
|
||||
y_re_din <= to_sfixed(0.25, y_re_din);
|
||||
y_im_din <= to_sfixed(0.125, y_im_din);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.125, x_re_din);
|
||||
y_re_din <= to_sfixed(0.25, y_re_din);
|
||||
y_im_din <= to_sfixed(0.125, y_im_din);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.3, x_re_din);
|
||||
y_re_din <= to_sfixed(-0.5, y_re_din);
|
||||
y_im_din <= to_sfixed(0.5, y_im_din);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
x_re_din <= to_sfixed(0.0, x_re_din);
|
||||
y_re_din <= to_sfixed(0.0, y_re_din);
|
||||
y_im_din <= to_sfixed(-0.7071, y_im_din);
|
||||
in_valid <= '1';
|
||||
------------------------------------------
|
||||
wait until rising_edge(clk);
|
||||
in_valid <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
x_re <= to_real(x_re_din);
|
||||
y_re <= to_real(y_re_din);
|
||||
y_im <= to_real(y_im_din);
|
||||
z_re <= to_real(z_re_dout);
|
||||
z_im <= to_real(z_im_dout);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,158 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
use work.PCK_FIO.all;
|
||||
|
||||
ENTITY tb_undc_real IS
|
||||
Generic (
|
||||
nbits_data : integer := 24;
|
||||
nbits_data_frac : integer := 24;
|
||||
nbits_k : integer := 24;
|
||||
nbits_k_frac : integer := 24;
|
||||
has_in_reg : boolean := true;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
END tb_undc_real;
|
||||
|
||||
ARCHITECTURE behavior OF tb_undc_real IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT undc_real
|
||||
Generic
|
||||
(
|
||||
nbits_data : integer;
|
||||
nbits_data_frac : integer;
|
||||
nbits_k : integer;
|
||||
nbits_k_frac : integer;
|
||||
has_in_reg : boolean;
|
||||
rounding : boolean;
|
||||
saturating : boolean
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
din_valid : in std_logic;
|
||||
din : in sfixed;
|
||||
kin_valid : in std_logic;
|
||||
kin : in sfixed;
|
||||
dout_valid : out std_logic;
|
||||
dout : out sfixed;
|
||||
dc_out : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL din_valid : std_logic := '0';
|
||||
SIGNAL kin_valid : std_logic := '0';
|
||||
SIGNAL din : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
|
||||
SIGNAL kin : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
|
||||
|
||||
--Outputs
|
||||
SIGNAL dout : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
|
||||
SIGNAL dc_out : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
|
||||
SIGNAL dout_valid : std_logic;
|
||||
|
||||
SIGNAL k : real := 0.0;
|
||||
SIGNAL x : real := 0.0;
|
||||
SIGNAL y : real := 0.0;
|
||||
SIGNAL dc : real := 0.0;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: undc_real
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_data => nbits_data,
|
||||
nbits_data_frac => nbits_data_frac,
|
||||
nbits_k => nbits_k,
|
||||
nbits_k_frac => nbits_k_frac,
|
||||
has_in_reg => has_in_reg,
|
||||
rounding => rounding,
|
||||
saturating => saturating
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
srst => srst,
|
||||
clk => clk,
|
||||
din_valid => din_valid,
|
||||
din => din,
|
||||
kin_valid => kin_valid,
|
||||
kin => kin,
|
||||
dout_valid => dout_valid,
|
||||
dout => dout,
|
||||
dc_out => dc_out
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
-- Load k
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
kin <= to_sfixed(0.0005, kin);
|
||||
kin_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
kin_valid <= '1';
|
||||
------------------------------------------
|
||||
-- Process
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
din <= to_sfixed(0.5, din);
|
||||
din_valid <= '1';
|
||||
wait until rising_edge(clk);
|
||||
din_valid <= '1';
|
||||
wait for 5*PERIOD;
|
||||
|
||||
wait for 200*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
k <= to_real(kin);
|
||||
x <= to_real(din);
|
||||
y <= to_real(dout);
|
||||
dc <= to_real(dc_out);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,139 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: mix_cpx - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
use work.mix_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
entity undc_real is
|
||||
Generic
|
||||
(
|
||||
nbits_data : integer := 12;
|
||||
nbits_data_frac : integer := 12;
|
||||
nbits_k : integer := 12;
|
||||
nbits_k_frac : integer := 12;
|
||||
has_in_reg : boolean := false;
|
||||
rounding : boolean := true;
|
||||
saturating : boolean := true
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
din_valid : in std_logic;
|
||||
din : in sfixed;
|
||||
kin_valid : in std_logic;
|
||||
kin : in sfixed;
|
||||
dout_valid : out std_logic;
|
||||
dout : out sfixed;
|
||||
dc_out : out sfixed
|
||||
);
|
||||
end undc_real;
|
||||
|
||||
architecture Behavioral of undc_real is
|
||||
|
||||
constant nbits_internal : integer := nbits_data + nbits_data;
|
||||
constant nbits_internal_frac : integer := nbits_data_frac + nbits_data_frac;
|
||||
|
||||
signal x : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
|
||||
signal k : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
|
||||
signal dc : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
|
||||
signal y : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
|
||||
signal y1 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
|
||||
signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
|
||||
|
||||
begin
|
||||
|
||||
dout <= resize(y, sproto(nbits_data, nbits_data_frac), rounding, saturating);
|
||||
dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), false, false);
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_din_reg: process(clk, din_valid, din)
|
||||
begin
|
||||
if has_in_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
x <= to_sfixed(0, x);
|
||||
else
|
||||
if din_valid = '1' then
|
||||
x <= din;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
x <= din;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_valid_reg: process(clk, din_valid)
|
||||
begin
|
||||
if has_in_reg = true then
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
dout_valid <= '0';
|
||||
else
|
||||
dout_valid <= din_valid;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
dout_valid <= din_valid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_kin_reg: process(clk, kin_valid, kin)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
k <= to_sfixed(0, k);
|
||||
else
|
||||
if kin_valid = '1' then
|
||||
k <= kin;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_pipe_y: process(clk, x, dc)
|
||||
begin
|
||||
y <= resize(x - dc, y, false, false);
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
y1 <= to_sfixed(0, y1);
|
||||
y2 <= to_sfixed(0, y2);
|
||||
dc <= to_sfixed(0, dc);
|
||||
else
|
||||
y1 <= y;
|
||||
y2 <= resize(y1 * k, y2, false, false);
|
||||
dc <= resize(y2 + dc, dc, false, false);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,15 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "../src/nco_pkg.vhd"
|
||||
vcom -explicit -93 "../src/waverom_dual.vhd"
|
||||
vcom -explicit -93 "../src/wavelut.vhd"
|
||||
vcom -explicit -93 "../src/nco_dbg.vhd"
|
||||
vcom -explicit -93 "../src/tb_nco.vhd"
|
||||
vsim -t 1ps -lib work tb_nco
|
||||
do {tb_nco.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 250us
|
||||
@@ -0,0 +1,46 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_nco/uut/srst
|
||||
add wave -noupdate -format Logic /tb_nco/uut/clk
|
||||
add wave -noupdate -format Logic /tb_nco/uut/pacc_clr
|
||||
add wave -noupdate -format Logic /tb_nco/uut/pacc_inc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in
|
||||
add wave -noupdate -format Logic /tb_nco/uut/freq_load
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in
|
||||
add wave -noupdate -format Logic /tb_nco/uut/phase_load
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out
|
||||
add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_i
|
||||
add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_q
|
||||
add wave -noupdate -format Logic /tb_nco/uut/out_valid
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_ud
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_d
|
||||
add wave -noupdate -format Literal /tb_nco/uut/wave_i_d
|
||||
add wave -noupdate -format Literal /tb_nco/uut/wave_q_d
|
||||
add wave -noupdate -format Literal /tb_nco/uut/wave_i_ud
|
||||
add wave -noupdate -format Literal /tb_nco/uut/wave_q_ud
|
||||
add wave -noupdate -format Literal /tb_nco/uut/lfsr
|
||||
add wave -noupdate -format Literal /tb_nco/uut/lfsr_out
|
||||
add wave -noupdate -format Logic /tb_nco/uut/lut_addr_valid
|
||||
add wave -noupdate -format Logic /tb_nco/uut/lfsr_valid
|
||||
add wave -noupdate -format Logic /tb_nco/uut/wave_d_valid
|
||||
add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {249141632 ps} 0}
|
||||
configure wave -namecolwidth 193
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
update
|
||||
WaveRestoreZoom {249024188 ps} {250051359 ps}
|
||||
@@ -0,0 +1,61 @@
|
||||
% Read data
|
||||
function tb_nco_results(nbins)
|
||||
fa = 100.0;
|
||||
f = TEXTREAD('freq.txt')*1E-6
|
||||
|
||||
I_ud = TEXTREAD('q_ud.txt')';
|
||||
I_d = TEXTREAD('q_d.txt')';
|
||||
LFSR = TEXTREAD('lfsr.txt');
|
||||
|
||||
N= length(I_ud);
|
||||
N_fft = min(16384, N);
|
||||
N_fft2 = N_fft/2;
|
||||
|
||||
fft_y2 = 2/N_fft*abs(fft(I_ud(1:N_fft).*hann(N_fft)'));
|
||||
fft_y3 = 2/N_fft*abs(fft(I_d(1:N_fft).*hann(N_fft)'));
|
||||
|
||||
[i, v] = get_maxpur(fft_y2, fa, f);
|
||||
max_spur_freq = (i*fa/N_fft);
|
||||
max_spur_value = 20*log10(v);
|
||||
|
||||
[i, v] = get_maxpur(fft_y3, fa, f);
|
||||
max_ditherd_spur_freq = (i*fa/N_fft);
|
||||
max_ditherd_spur_value = 20*log10(v);
|
||||
|
||||
% Output
|
||||
close all;
|
||||
|
||||
subplot(2,1,1)
|
||||
plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid;
|
||||
spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_spur_value, max_spur_freq);
|
||||
legend('With dithering', spur_legend);
|
||||
legend('No dithering', spur_legend);
|
||||
title('Table');
|
||||
ylabel('dB');
|
||||
xlabel('f/MHz');
|
||||
axis([0 fa/2 -120 0]);
|
||||
subplot(2,1,2)
|
||||
plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid;
|
||||
spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_ditherd_spur_value, max_ditherd_spur_freq);
|
||||
legend('With dithering', spur_legend);
|
||||
title('Table');
|
||||
ylabel('dB');
|
||||
xlabel('f/MHz');
|
||||
axis([0 fa/2 -120 0]);
|
||||
|
||||
figure;
|
||||
hist(LFSR, nbins)
|
||||
|
||||
function [max_i, max_v] = get_maxpur(spec, fa, f)
|
||||
max_v = 0;
|
||||
max_i = 0;
|
||||
for ii=1:fix(length(spec)/2+1),
|
||||
fi = ii*fa/length(spec);
|
||||
dfi = fi - f;
|
||||
if abs(dfi) > 0.05*f
|
||||
if spec(ii) > max_v
|
||||
max_v = spec(ii);
|
||||
max_i = ii;
|
||||
end
|
||||
end;
|
||||
end;
|
||||
@@ -0,0 +1,223 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: cordic_stage - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
use work.nco_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity nco is
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer := 18;
|
||||
nbits_phase : integer := 16;
|
||||
nbits_lut_depth : integer := 12;
|
||||
nbits_dither : integer := 4;
|
||||
nbits_lfsr : integer := 12;
|
||||
q_phase : phase_relation_t := phase_90deg;
|
||||
has_pipe_reg : boolean := false;
|
||||
has_out_reg : boolean := false
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
pacc_clr : in std_logic;
|
||||
pacc_inc : in std_logic;
|
||||
freq_in : in unsigned(nbits_phase-1 downto 0);
|
||||
freq_load : in std_logic;
|
||||
phase_in : in unsigned(nbits_phase-1 downto 0);
|
||||
phase_load : in std_logic;
|
||||
phase_out : out unsigned(nbits_phase-1 downto 0);
|
||||
wave_out_i : out sfixed;
|
||||
wave_out_q : out sfixed;
|
||||
out_valid : out std_logic
|
||||
);
|
||||
end nco;
|
||||
|
||||
architecture Behavioral of nco is
|
||||
|
||||
COMPONENT wavelut
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer;
|
||||
nbits_wave_frac : integer;
|
||||
nbits_lut_depth : integer;
|
||||
q_phase : phase_relation_t;
|
||||
has_out_reg : boolean
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
addr_valid : in std_logic;
|
||||
addr : in unsigned(nbits_lut_depth-1 downto 0);
|
||||
wave_i_out : out sfixed;
|
||||
wave_q_out : out sfixed;
|
||||
valid_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
constant nbits_wave_frac : integer := nbits_wave;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
|
||||
|
||||
signal phase : unsigned(nbits_phase-1 downto 0);
|
||||
signal freq_in_r : unsigned(nbits_phase-1 downto 0);
|
||||
signal phase_in_r : unsigned(nbits_phase-1 downto 0);
|
||||
signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
|
||||
signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
|
||||
type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
|
||||
signal lfsr : lfsr_t;
|
||||
signal lfsr_out : unsigned(nbits_dither-1 downto 0);
|
||||
signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
wave_out_i <= wave_i_d;
|
||||
wave_out_q <= wave_q_d;
|
||||
out_valid <= wave_d_valid;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_lfsr: process(srst, clk, lfsr, pacc_inc)
|
||||
variable lo : unsigned(nbits_dither-1 downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
lfsr_valid <= '0';
|
||||
lfsr_out <= (others => '0');
|
||||
for i in lfsr'range loop
|
||||
lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
|
||||
end loop;
|
||||
else
|
||||
lfsr_valid <= '0';
|
||||
if pacc_inc ='1' then
|
||||
lfsr_valid <= '1';
|
||||
lo := (others => '0');
|
||||
for i in lfsr'range loop
|
||||
if lfsr(i)(lfsr(i)'left) = '1' then
|
||||
lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
|
||||
else
|
||||
lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
|
||||
end if;
|
||||
end loop;
|
||||
for i in lfsr'range loop
|
||||
lo := lo + lfsr(i)(nbits_dither-1 downto 0);
|
||||
end loop;
|
||||
-- lo := lfsr(0)(nbits_dither downto 0);
|
||||
lfsr_out <= lo(nbits_dither-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_phase_accu: process(clk, phase)
|
||||
variable phase_accu : unsigned(nbits_phase-1 downto 0);
|
||||
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
phase_accu := (others => '0');
|
||||
else
|
||||
phase <= phase_accu + phase_in_r;
|
||||
if pacc_clr = '1' then
|
||||
phase_accu := (others => '0');
|
||||
elsif pacc_inc = '1' then
|
||||
phase_accu := phase_accu + freq_in_r;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
phase_out <= phase;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
freq_in_reg: process(srst, clk, freq_load, freq_in)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
freq_in_r <= (others => '0');
|
||||
elsif freq_load = '1' then
|
||||
freq_in_r <= freq_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
phase_in_reg: process(srst, clk, phase_load, phase_in)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
phase_in_r <= (others => '0');
|
||||
elsif phase_load = '1' then
|
||||
phase_in_r <= phase_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_pipe_reg: process(clk)
|
||||
variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
lut_addr_valid <= '0';
|
||||
if srst = '1' then
|
||||
lfsr_sum := (others => '0');
|
||||
elsif lfsr_valid = '1' then
|
||||
lut_addr_valid <= '1';
|
||||
lfsr_sum := lfsr_out + phase;
|
||||
end if;
|
||||
end if;
|
||||
lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
inst_wavelut_d: wavelut
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_wave => nbits_wave,
|
||||
nbits_wave_frac => nbits_wave_frac,
|
||||
nbits_lut_depth => nbits_lut_depth,
|
||||
q_phase => q_phase,
|
||||
has_out_reg => has_out_reg
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => srst,
|
||||
clk => clk,
|
||||
addr_valid => lut_addr_valid,
|
||||
addr => lut_addr_d,
|
||||
wave_i_out => wave_i_d,
|
||||
wave_q_out => wave_q_d,
|
||||
valid_out => wave_d_valid
|
||||
);
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,240 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: cordic_stage - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
use work.nco_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity nco is
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer := 12;
|
||||
nbits_phase : integer := 16;
|
||||
nbits_lut_depth : integer := 12;
|
||||
nbits_dither : integer := 4;
|
||||
nbits_lfsr : integer := 12;
|
||||
has_pipe_reg : boolean := false;
|
||||
has_out_reg : boolean := false
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
pacc_clr : in std_logic;
|
||||
pacc_inc : in std_logic;
|
||||
freq_in : in unsigned(nbits_phase-1 downto 0);
|
||||
freq_load : in std_logic;
|
||||
phase_in : in unsigned(nbits_phase-1 downto 0);
|
||||
phase_load : in std_logic;
|
||||
phase_out : out unsigned(nbits_phase-1 downto 0);
|
||||
wave_out_i : out sfixed;
|
||||
wave_out_q : out sfixed;
|
||||
out_valid : out std_logic
|
||||
);
|
||||
end nco;
|
||||
|
||||
architecture Behavioral of nco is
|
||||
|
||||
COMPONENT wavelut
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer;
|
||||
nbits_wave_frac : integer;
|
||||
nbits_lut_depth : integer;
|
||||
has_out_reg : boolean
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
addr_valid : in std_logic;
|
||||
addr : in unsigned(nbits_lut_depth-1 downto 0);
|
||||
wave_i_out : out sfixed;
|
||||
wave_q_out : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
constant nbits_wave_frac : integer := nbits_wave;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
|
||||
|
||||
signal valid : std_logic_vector(3 downto 0);
|
||||
signal phase : unsigned(nbits_phase-1 downto 0);
|
||||
signal freq_in_r : unsigned(nbits_phase-1 downto 0);
|
||||
signal phase_in_r : unsigned(nbits_phase-1 downto 0);
|
||||
signal lsfr_sum : unsigned(nbits_phase-1 downto 0);
|
||||
signal lut_addr : unsigned(nbits_lut_depth-1 downto 0);
|
||||
signal wave_i, wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
|
||||
signal lfsr : lfsr_t;
|
||||
signal lfsr_out : unsigned(nbits_dither-1 downto 0);
|
||||
signal lut_addr_valid _ std_logic;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
wave_out_i <= wave_i;
|
||||
wave_out_q <= wave_q;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_ctrl: process(srst, clk, pacc_inc, pacc_clr)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
valid <= (others => '0');
|
||||
else
|
||||
valid <= valid(valid'left-1 downto valid'right) & (pacc_inc or pacc_clr);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_lfsr: process(srst, clk, lfsr, pacc_inc)
|
||||
variable lo : unsigned(nbits_dither downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
for i in lfsr'range loop
|
||||
lfsr(i) <= to_unsigned(1234+2**i, nbits_lfsr);
|
||||
end loop;
|
||||
elsif pacc_inc ='1' then
|
||||
lo := (others => '0');
|
||||
for i in lfsr'range loop
|
||||
if lfsr(i)(lfsr(i)'left) = '1' then
|
||||
lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
|
||||
else
|
||||
lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
|
||||
end if;
|
||||
end loop;
|
||||
for i in lfsr'range loop
|
||||
lo := lo + lfsr(i)(nbits_dither-1 downto 0);
|
||||
end loop;
|
||||
-- lo := lfsr(0)(nbits_dither downto 0);
|
||||
lfsr_out <= lo(nbits_dither-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
|
||||
variable phase_accu : unsigned(nbits_phase-1 downto 0);
|
||||
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
phase_accu := (others => '0');
|
||||
else
|
||||
phase <= phase_accu + phase_in_r;
|
||||
if pacc_clr = '1' then
|
||||
phase_accu := (others => '0');
|
||||
elsif pacc_inc = '1' then
|
||||
phase_accu := phase_accu + freq_in_r;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
freq_in_reg: process(srst, clk, freq_load, freq_in)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
freq_in_r <= (others => '0');
|
||||
elsif freq_load = '1' then
|
||||
freq_in_r <= freq_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
phase_in_reg: process(srst, clk, phase_load, phase_in)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
phase_in_r <= (others => '0');
|
||||
elsif phase_load = '1' then
|
||||
phase_in_r <= phase_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_pipe_reg: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
lsfr_sum <= lfsr_out + phase;
|
||||
lut_addr <= lsfr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_out_reg: process(clk, phase)
|
||||
begin
|
||||
if has_out_reg = true then
|
||||
if rising_edge(clk) then
|
||||
phase_out <= phase;
|
||||
end if;
|
||||
else
|
||||
phase_out <= phase;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_valid_reg: process(clk, valid)
|
||||
begin
|
||||
out_valid <= valid(valid'right+1);
|
||||
if has_out_reg = true then
|
||||
out_valid <= valid(valid'right+2);
|
||||
if has_pipe_reg = true then
|
||||
out_valid <= valid(valid'right+3);
|
||||
end if;
|
||||
elsif has_pipe_reg = true then
|
||||
out_valid <= valid(valid'right+2);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
inst_wavelut_d: wavelut
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_wave => nbits_wave,
|
||||
nbits_wave_frac => nbits_wave_frac,
|
||||
nbits_lut_depth => nbits_lut_depth,
|
||||
has_out_reg => has_out_reg
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
addr => lut_addr,
|
||||
addr_valid => lut_addr_valid,
|
||||
wave_i_out => wave_i,
|
||||
wave_q_out => wave_q
|
||||
);
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,253 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: cordic_stage - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
use work.nco_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity nco is
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer := 18;
|
||||
nbits_phase : integer := 16;
|
||||
nbits_lut_depth : integer := 12;
|
||||
nbits_dither : integer := 4;
|
||||
nbits_lfsr : integer := 12;
|
||||
q_phase : phase_relation_t := phase_90deg;
|
||||
has_pipe_reg : boolean := false;
|
||||
has_out_reg : boolean := false
|
||||
);
|
||||
Port
|
||||
(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
pacc_clr : in std_logic;
|
||||
pacc_inc : in std_logic;
|
||||
freq_in : in unsigned(nbits_phase-1 downto 0);
|
||||
freq_load : in std_logic;
|
||||
phase_in : in unsigned(nbits_phase-1 downto 0);
|
||||
phase_load : in std_logic;
|
||||
phase_out : out unsigned(nbits_phase-1 downto 0);
|
||||
wave_out_i : out sfixed;
|
||||
wave_out_q : out sfixed;
|
||||
out_valid : out std_logic;
|
||||
debug_out : out debug_out_t
|
||||
);
|
||||
end nco;
|
||||
|
||||
architecture Behavioral of nco is
|
||||
|
||||
COMPONENT wavelut
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer;
|
||||
nbits_wave_frac : integer;
|
||||
nbits_lut_depth : integer;
|
||||
q_phase : phase_relation_t;
|
||||
has_out_reg : boolean
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
addr_valid : in std_logic;
|
||||
addr : in unsigned(nbits_lut_depth-1 downto 0);
|
||||
wave_i_out : out sfixed;
|
||||
wave_q_out : out sfixed;
|
||||
valid_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
constant nbits_wave_frac : integer := nbits_wave;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
|
||||
|
||||
signal phase : unsigned(nbits_phase-1 downto 0);
|
||||
signal freq_in_r : unsigned(nbits_phase-1 downto 0);
|
||||
signal phase_in_r : unsigned(nbits_phase-1 downto 0);
|
||||
signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0);
|
||||
signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
|
||||
signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
|
||||
type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
|
||||
signal lfsr : lfsr_t;
|
||||
signal lfsr_out : unsigned(nbits_dither-1 downto 0);
|
||||
signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
wave_out_i <= wave_i_d;
|
||||
wave_out_q <= wave_q_d;
|
||||
out_valid <= wave_d_valid;
|
||||
|
||||
debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out;
|
||||
debug_out.i_d <= to_real(wave_i_d);
|
||||
debug_out.q_d <= to_real(wave_q_d);
|
||||
debug_out.i_ud <= to_real(wave_i_ud);
|
||||
debug_out.q_ud <= to_real(wave_q_ud);
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_lfsr: process(srst, clk, lfsr, pacc_inc)
|
||||
variable lo : unsigned(nbits_dither-1 downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
lfsr_valid <= '0';
|
||||
lfsr_out <= (others => '0');
|
||||
for i in lfsr'range loop
|
||||
lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
|
||||
end loop;
|
||||
else
|
||||
lfsr_valid <= '0';
|
||||
if pacc_inc ='1' then
|
||||
lfsr_valid <= '1';
|
||||
lo := (others => '0');
|
||||
for i in lfsr'range loop
|
||||
if lfsr(i)(lfsr(i)'left) = '1' then
|
||||
lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
|
||||
else
|
||||
lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
|
||||
end if;
|
||||
end loop;
|
||||
for i in lfsr'range loop
|
||||
lo := lo + lfsr(i)(nbits_dither-1 downto 0);
|
||||
end loop;
|
||||
-- lo := lfsr(0)(nbits_dither downto 0);
|
||||
lfsr_out <= lo(nbits_dither-1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
|
||||
variable phase_accu : unsigned(nbits_phase-1 downto 0);
|
||||
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
phase_accu := (others => '0');
|
||||
else
|
||||
phase <= phase_accu + phase_in_r;
|
||||
if pacc_clr = '1' then
|
||||
phase_accu := (others => '0');
|
||||
elsif pacc_inc = '1' then
|
||||
phase_accu := phase_accu + freq_in_r;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
phase_out <= phase;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
freq_in_reg: process(srst, clk, freq_load, freq_in)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
freq_in_r <= (others => '0');
|
||||
elsif freq_load = '1' then
|
||||
freq_in_r <= freq_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
phase_in_reg: process(srst, clk, phase_load, phase_in)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if srst = '1' then
|
||||
phase_in_r <= (others => '0');
|
||||
elsif phase_load = '1' then
|
||||
phase_in_r <= phase_in;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_pipe_reg: process(clk)
|
||||
variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
lut_addr_valid <= '0';
|
||||
if srst = '1' then
|
||||
lfsr_sum := (others => '0');
|
||||
elsif lfsr_valid = '1' then
|
||||
lut_addr_valid <= '1';
|
||||
lfsr_sum := lfsr_out + phase;
|
||||
end if;
|
||||
end if;
|
||||
lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
|
||||
lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
inst_wavelut_ud: wavelut
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_wave => nbits_wave,
|
||||
nbits_wave_frac => nbits_wave_frac,
|
||||
nbits_lut_depth => nbits_lut_depth,
|
||||
q_phase => q_phase,
|
||||
has_out_reg => has_out_reg
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => srst,
|
||||
clk => clk,
|
||||
addr_valid => lut_addr_valid,
|
||||
addr => lut_addr_ud,
|
||||
wave_i_out => wave_i_ud,
|
||||
wave_q_out => wave_q_ud,
|
||||
valid_out => wave_ud_valid
|
||||
);
|
||||
|
||||
inst_wavelut_d: wavelut
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_wave => nbits_wave,
|
||||
nbits_wave_frac => nbits_wave_frac,
|
||||
nbits_lut_depth => nbits_lut_depth,
|
||||
q_phase => q_phase,
|
||||
has_out_reg => has_out_reg
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => srst,
|
||||
clk => clk,
|
||||
addr_valid => lut_addr_valid,
|
||||
addr => lut_addr_d,
|
||||
wave_i_out => wave_i_d,
|
||||
wave_q_out => wave_q_d,
|
||||
valid_out => wave_d_valid
|
||||
);
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,117 @@
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
package nco_pkg is
|
||||
|
||||
constant tpd : time := 0 ns;
|
||||
|
||||
-- Global set arithmetic rounding mode
|
||||
constant pi : real := 3.141592653589793e+000;
|
||||
constant sqrt2 : real := 1.414213562373095e+000;
|
||||
constant sqrt2_inv : real := 7.071067811865475e-001;
|
||||
|
||||
type real_array_t is array (natural range <>) of real;
|
||||
type natural_array_t is array (natural range <>) of natural;
|
||||
type phase_relation_t is (phase_90deg, phase_270deg);
|
||||
|
||||
type debug_out_t is record
|
||||
lfsr : unsigned(31 downto 0);
|
||||
i_ud : real;
|
||||
q_ud : real;
|
||||
i_d : real;
|
||||
q_d : real;
|
||||
end record;
|
||||
|
||||
constant lfsr_poly : natural_array_t(3 to 24) :=
|
||||
(
|
||||
12, -- 3
|
||||
24, -- 4
|
||||
58, -- 5
|
||||
114, -- 6
|
||||
210, -- 7
|
||||
500, -- 8
|
||||
1000, -- 9
|
||||
1824, -- 10
|
||||
3712, -- 11
|
||||
7184, -- 12
|
||||
14592, -- 13
|
||||
28674, -- 14
|
||||
59392, -- 15
|
||||
106512, -- 16
|
||||
245760, -- 17
|
||||
466944, -- 18
|
||||
933888, -- 19
|
||||
1654784, -- 20
|
||||
3735552, -- 21
|
||||
7342080, -- 22
|
||||
14745600, -- 23
|
||||
14811138 -- 24
|
||||
);
|
||||
|
||||
function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t;
|
||||
function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Constructor helpers
|
||||
-- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
|
||||
function uproto (nbits : integer; nbits_frac : integer) return ufixed;
|
||||
|
||||
-- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
|
||||
function sproto (nbits : integer; nbits_frac : integer) return sfixed;
|
||||
|
||||
end; -- package nco_pkg;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
package body nco_pkg is
|
||||
|
||||
function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is
|
||||
variable tbl : real_array_t (0 to nsamples-1);
|
||||
variable phi : real := phi_in;
|
||||
variable dphi : real := 2.0*pi*omega;
|
||||
|
||||
begin
|
||||
for i in 0 to nsamples-1 loop
|
||||
tbl(i) := sin(phi);
|
||||
phi := phi + dphi;
|
||||
end loop;
|
||||
|
||||
return tbl;
|
||||
end sin_tbl;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is
|
||||
variable tbl : real_array_t (0 to nsamples-1);
|
||||
variable phi : real := phi_in;
|
||||
variable dphi : real := 2.0*pi*omega;
|
||||
|
||||
begin
|
||||
for i in 0 to nsamples-1 loop
|
||||
tbl(i) := cos(phi);
|
||||
phi := phi + dphi;
|
||||
end loop;
|
||||
|
||||
return tbl;
|
||||
end cos_tbl;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Constuctor helpers
|
||||
function uproto (nbits : integer; nbits_frac : integer) return ufixed is
|
||||
constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0');
|
||||
begin
|
||||
return result(nbits-nbits_frac-1 downto -nbits_frac);
|
||||
end uproto;
|
||||
|
||||
-------------------------------------------------------------
|
||||
function sproto (nbits : integer; nbits_frac : integer) return sfixed is
|
||||
constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0');
|
||||
begin
|
||||
return result(nbits-nbits_frac downto -nbits_frac+1);
|
||||
end sproto;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
end; -- package nco_pkg;
|
||||
@@ -0,0 +1,299 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_nco
|
||||
-- Module Name: tb_nco.vhd
|
||||
-- Project Name: nco
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.nco_pkg.all;
|
||||
use work.PCK_FIO.all;
|
||||
|
||||
ENTITY tb_nco IS
|
||||
Generic (
|
||||
nbits_wave : integer := 18;
|
||||
nbits_phase : integer := 16;
|
||||
nbits_lut_depth : integer := 12;
|
||||
nbits_dither : integer := 4;
|
||||
nbits_lfsr : integer := 12;
|
||||
q_phase : phase_relation_t := phase_270deg;
|
||||
has_pipe_reg : boolean := true;
|
||||
has_out_reg : boolean := true
|
||||
);
|
||||
END tb_nco;
|
||||
|
||||
ARCHITECTURE behavior OF tb_nco IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT nco
|
||||
GENERIC (
|
||||
nbits_wave : integer;
|
||||
nbits_phase : integer;
|
||||
nbits_lut_depth : integer;
|
||||
nbits_dither : integer;
|
||||
nbits_lfsr : integer;
|
||||
q_phase : phase_relation_t;
|
||||
has_pipe_reg : boolean;
|
||||
has_out_reg : boolean
|
||||
);
|
||||
PORT(
|
||||
srst : in std_logic;
|
||||
clk : in std_logic;
|
||||
-- ce : in std_logic;
|
||||
pacc_clr : in std_logic;
|
||||
pacc_inc : in std_logic;
|
||||
freq_in : in unsigned(nbits_phase-1 downto 0);
|
||||
freq_load : in std_logic;
|
||||
phase_in : in unsigned(nbits_phase-1 downto 0);
|
||||
phase_load : in std_logic;
|
||||
phase_out : out unsigned(nbits_phase-1 downto 0);
|
||||
wave_out_i : out sfixed;
|
||||
wave_out_q : out sfixed;
|
||||
out_valid : out std_logic;
|
||||
debug_out : out debug_out_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant f : REAL := 4.1667E6;
|
||||
constant df : REAL := 10.0E3;
|
||||
constant fa : REAL := 100.0E6;
|
||||
constant PERIOD : time := 10 ns;
|
||||
constant nbits_wave_frac : integer := nbits_wave;
|
||||
|
||||
SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
|
||||
SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
-- SIGNAL ce : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL pacc_clr : std_logic := '0';
|
||||
SIGNAL pacc_inc : std_logic := '0';
|
||||
SIGNAL phase_load : std_logic := '0';
|
||||
SIGNAL freq_load : std_logic := '0';
|
||||
SIGNAL freq_in : unsigned(nbits_phase-1 downto 0);
|
||||
SIGNAL phase_in : unsigned(nbits_phase-1 downto 0);
|
||||
|
||||
--Outputs
|
||||
SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
SIGNAL out_valid : std_logic;
|
||||
SIGNAL phase_out : unsigned(nbits_phase-1 downto 0);
|
||||
SIGNAL debug_out : debug_out_t;
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: nco
|
||||
GENERIC MAP (
|
||||
nbits_wave => nbits_wave,
|
||||
nbits_phase => nbits_phase,
|
||||
nbits_lut_depth => nbits_lut_depth,
|
||||
nbits_dither => nbits_dither,
|
||||
nbits_lfsr => nbits_lfsr,
|
||||
q_phase => q_phase,
|
||||
has_pipe_reg => has_pipe_reg,
|
||||
has_out_reg => has_out_reg
|
||||
)
|
||||
PORT MAP(
|
||||
srst => srst,
|
||||
clk => clk,
|
||||
-- ce => ce,
|
||||
pacc_clr => pacc_clr,
|
||||
pacc_inc => pacc_inc,
|
||||
freq_in => freq_in,
|
||||
freq_load => freq_load,
|
||||
phase_in => phase_in,
|
||||
phase_load => phase_load,
|
||||
phase_out => phase_out,
|
||||
wave_out_i => wave_out_i,
|
||||
wave_out_q => wave_out_q,
|
||||
out_valid => out_valid,
|
||||
debug_out => debug_out
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
file RESULT_FREQ: text open write_mode is "freq.txt";
|
||||
variable L: line;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
|
||||
fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
|
||||
|
||||
wait for 2*PERIOD;
|
||||
-- ce <= '1';
|
||||
-------------------------------------------
|
||||
-- 1
|
||||
phase_in <= to_unsigned(0,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '0';
|
||||
|
||||
freq_in <= to_unsigned(1411,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
wait for 2*PERIOD;
|
||||
pacc_inc <= '1';
|
||||
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
wait for 40*PERIOD;
|
||||
-------------------------------------------
|
||||
freq_in <= to_unsigned(643,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
wait for 40*PERIOD;
|
||||
-------------------------------------------
|
||||
phase_in <= to_unsigned(800,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
-------------------------------------------
|
||||
phase_in <= to_unsigned(45072,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
-------------------------------------------
|
||||
phase_in <= to_unsigned(20593,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
phase_load <= '0';
|
||||
|
||||
-------------------------------------------
|
||||
freq_in <= to_unsigned(freq_word,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
fileout_enable <= '1';
|
||||
|
||||
wait for 20000*PERIOD;
|
||||
fileout_enable <= '0';
|
||||
|
||||
-------------------------------------------
|
||||
-- Sweep
|
||||
freq_word <= 100;
|
||||
for i in 1 to 200 loop
|
||||
wait for 20*PERIOD;
|
||||
freq_word <= freq_word + dfreq_word;
|
||||
|
||||
freq_in <= to_unsigned(freq_word,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
end loop;
|
||||
|
||||
pacc_inc <= '0';
|
||||
wait for 20*PERIOD;
|
||||
fileout_enable <= '0';
|
||||
wait until rising_edge(clk);
|
||||
pacc_clr <= '1';
|
||||
wait until rising_edge(clk);
|
||||
pacc_clr <= '0';
|
||||
wait for 20*PERIOD;
|
||||
pacc_inc <= '1';
|
||||
wait for 20*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
pacc_clr <= '1';
|
||||
wait until rising_edge(clk);
|
||||
pacc_clr <= '0';
|
||||
wait for 20*PERIOD;
|
||||
pacc_inc <= '0';
|
||||
wait for 20*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
pacc_inc <= '1';
|
||||
wait until rising_edge(clk);
|
||||
pacc_inc <= '0';
|
||||
wait for 20*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
srst <= '1';
|
||||
wait until rising_edge(clk);
|
||||
srst <= '0';
|
||||
freq_in <= to_unsigned(freq_word,nbits_phase);
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '1';
|
||||
wait until rising_edge(clk);
|
||||
freq_load <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
pacc_inc <= '1';
|
||||
wait for 20*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
srst <= '1';
|
||||
wait until rising_edge(clk);
|
||||
srst <= '0';
|
||||
wait for 20*PERIOD;
|
||||
pacc_inc <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
tb_fo : PROCESS(clk, fileout_enable, out_valid)
|
||||
file RESULT_I: text open write_mode is "i_ud.txt";
|
||||
file RESULT_Q: text open write_mode is "q_ud.txt";
|
||||
file RESULT_ID: text open write_mode is "i_d.txt";
|
||||
file RESULT_QD: text open write_mode is "q_d.txt";
|
||||
file RESULT_LFSR: text open write_mode is "lfsr.txt";
|
||||
variable L: line;
|
||||
|
||||
BEGIN
|
||||
if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
|
||||
fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud));
|
||||
fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud));
|
||||
fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d));
|
||||
fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d));
|
||||
fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr)));
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,239 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: cordic_stage - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
use work.nco_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity wavelut is
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer := 12;
|
||||
nbits_wave_frac : integer := 12;
|
||||
nbits_lut_depth : integer := 12;
|
||||
q_phase : phase_relation_t := phase_90deg;
|
||||
has_out_reg : boolean := false
|
||||
);
|
||||
Port
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
addr_valid : in std_logic;
|
||||
addr : in unsigned(nbits_lut_depth-1 downto 0);
|
||||
wave_i_out : out sfixed;
|
||||
wave_q_out : out sfixed;
|
||||
valid_out : out std_logic
|
||||
);
|
||||
end wavelut;
|
||||
|
||||
architecture Behavioral of wavelut is
|
||||
|
||||
COMPONENT waverom_dual
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer;
|
||||
nbits_wave_frac : integer;
|
||||
nbits_rom_depth : integer
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
addr_i : in unsigned(nbits_rom_depth-1 downto 0);
|
||||
addr_q : in unsigned(nbits_rom_depth-1 downto 0);
|
||||
wave_i_out : out sfixed;
|
||||
wave_q_out : out sfixed
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
constant nbits_rom_depth : integer := nbits_lut_depth-2;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
signal wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
signal wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
signal inv_i : std_logic;
|
||||
signal inv_q : std_logic;
|
||||
signal addr_i : unsigned(nbits_rom_depth-1 downto 0);
|
||||
signal addr_q : unsigned(nbits_rom_depth-1 downto 0);
|
||||
signal zero_i : std_logic;
|
||||
signal zero_q : std_logic;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
inst_waverom_dual: waverom_dual
|
||||
GENERIC MAP
|
||||
(
|
||||
nbits_wave => nbits_wave,
|
||||
nbits_wave_frac => nbits_wave_frac,
|
||||
nbits_rom_depth => nbits_rom_depth
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
addr_i => addr_i,
|
||||
addr_q => addr_q,
|
||||
wave_i_out => wave_i,
|
||||
wave_q_out => wave_q
|
||||
);
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_valid: process(clk)
|
||||
variable v : unsigned(0 to 1);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
v := (others => '0');
|
||||
valid_out <= '0';
|
||||
else
|
||||
valid_out <= v(1);
|
||||
v(1) := v(0);
|
||||
v(0) := addr_valid;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_tbl_addr_i: process(clk, addr)
|
||||
variable index : unsigned(addr'left downto addr'right);
|
||||
variable n2 : integer;
|
||||
constant N_2 : integer := 2**(nbits_lut_depth-1);
|
||||
constant N_4 : integer := 2**(nbits_lut_depth-2);
|
||||
begin
|
||||
n2 := to_integer(addr(addr'left-1 downto addr'right));
|
||||
if n2 > N_4 then
|
||||
index := to_unsigned(N_2 - n2, index'length);
|
||||
else
|
||||
index := to_unsigned(n2, index'length);
|
||||
end if;
|
||||
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
addr_i <= (others => '0');
|
||||
zero_i <= '0';
|
||||
inv_i <= '0';
|
||||
elsif addr_valid = '1' then
|
||||
addr_i <= index(addr'left-2 downto addr'right);
|
||||
zero_i <= index(addr'left-1);
|
||||
inv_i <= addr(addr'left) xor addr(addr'left-1);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
proc_tbl_addr_q: process(clk, addr)
|
||||
variable index : unsigned(addr'left downto addr'right);
|
||||
variable n2 : integer;
|
||||
constant N_4 : integer := 2**(nbits_lut_depth-2);
|
||||
|
||||
begin
|
||||
n2 := to_integer(addr(addr'left-1 downto addr'right));
|
||||
if n2 > N_4 then
|
||||
index := to_unsigned(n2 - N_4, index'length);
|
||||
else
|
||||
index := to_unsigned(N_4 - n2, index'length);
|
||||
end if;
|
||||
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
addr_q <= (others => '0');
|
||||
zero_q <= '0';
|
||||
inv_q <= '0';
|
||||
elsif addr_valid = '1' then
|
||||
addr_q <= index(addr'left-2 downto addr'right);
|
||||
zero_q <= index(addr'left-1);
|
||||
if q_phase = phase_90deg then
|
||||
inv_q <= addr(addr'left);
|
||||
elsif q_phase = phase_270deg then
|
||||
inv_q <= not addr(addr'left);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_out_i: process(clk, wave_i, inv_i, zero_i)
|
||||
variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
variable z, inv : std_logic;
|
||||
begin
|
||||
|
||||
w := to_sfixed(0.0, w);
|
||||
if z = '0' then
|
||||
w := wave_i;
|
||||
if inv = '1' then
|
||||
w := resize(-wave_i, w, fixed_truncate, fixed_wrap);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if has_out_reg = true then
|
||||
if rising_edge(clk) then
|
||||
wave_i_out <= w;
|
||||
end if;
|
||||
else
|
||||
wave_i_out <= w;
|
||||
end if;
|
||||
|
||||
if rising_edge(clk) then
|
||||
z := zero_i;
|
||||
inv := inv_i;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
proc_out_q: process(clk, wave_q, inv_q, zero_q)
|
||||
variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
variable z, inv : std_logic;
|
||||
begin
|
||||
|
||||
w := to_sfixed(0.0, w);
|
||||
if z = '0' then
|
||||
w := wave_q;
|
||||
if inv = '1' then
|
||||
w := resize(-wave_q, w, fixed_truncate, fixed_wrap);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if has_out_reg = true then
|
||||
if rising_edge(clk) then
|
||||
wave_q_out <= w;
|
||||
end if;
|
||||
else
|
||||
wave_q_out <= w;
|
||||
end if;
|
||||
|
||||
if rising_edge(clk) then
|
||||
z := zero_q;
|
||||
inv := inv_q;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,86 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: cordic_stage - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use work.fixed_pkg.all;
|
||||
use work.nco_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity waverom_dual is
|
||||
Generic
|
||||
(
|
||||
nbits_wave : integer := 12;
|
||||
nbits_wave_frac : integer := 12;
|
||||
nbits_rom_depth : integer := 12
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
addr_i : in unsigned(nbits_rom_depth-1 downto 0);
|
||||
addr_q : in unsigned(nbits_rom_depth-1 downto 0);
|
||||
wave_i_out : out sfixed;
|
||||
wave_q_out : out sfixed
|
||||
);
|
||||
end waverom_dual;
|
||||
|
||||
architecture Behavioral of waverom_dual is
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
constant rom_depth : integer := 2**nbits_rom_depth;
|
||||
type wave_mem_t is array (0 to rom_depth-1) of sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
|
||||
|
||||
constant sfixed_proto : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low) := (others => '0');
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
function to_wave_mem(wave_real : real_array_t; len : integer; proto : sfixed) return wave_mem_t is
|
||||
variable res : wave_mem_t;
|
||||
begin
|
||||
for i in 0 to len-1 loop
|
||||
res(i) := to_sfixed(wave_real(i), proto, fixed_round, fixed_saturate);
|
||||
end loop;
|
||||
|
||||
return res;
|
||||
end to_wave_mem;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
-- Create ROM
|
||||
constant real_wave_tbl : real_array_t(0 to rom_depth-1) := cos_tbl(rom_depth, 0.25/real(rom_depth), 0.0);
|
||||
constant wave_tbl : wave_mem_t := to_wave_mem(real_wave_tbl, rom_depth, sfixed_proto);
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
begin
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
proc_wave: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
wave_i_out <= wave_tbl(to_integer(addr_i));
|
||||
wave_q_out <= wave_tbl(to_integer(addr_q));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
Reference in New Issue
Block a user