Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b

lib/misc/tb_template.vhd

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+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_template IS
+END tb_template;
+
+ARCHITECTURE behavior OF tb_template IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT your_comp
+	GENERIC
+	(
+	);
+	PORT
+	(
+	);
+	END COMPONENT;
+
+	--Constants
+	constant PERIOD : time := 10 ns;
+
+	--Inputs
+	signal clk		: STD_LOGIC := '0';
+
+	--Outputs
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: your_comp 
+	GENERIC MAP
+	(
+	)
+	PORT MAP
+	(
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 4*PERIOD;
+
+		assert false report "Test finished" severity error;
+		wait; 
+		
+	END PROCESS;
+	
+END tb_template;