Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b

lib/misc/lcd_port.vhd

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+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
+-----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+	------------------------------------------------------------------
+entity lcd_port is
+	Port (
+			rst			: in std_logic;
+			clk			: in std_logic;
+			we			: in std_logic;
+			din			: in unsigned(7 downto 0);
+			dout		: out unsigned(7 downto 0);
+			lcd_d		: inout unsigned(3 downto 0);
+			lcd_e		: out std_logic;
+			lcd_rs		: out std_logic;
+			lcd_rw		: out std_logic
+		);
+	end lcd_port;
+
+architecture Behavioral of lcd_port is
+
+	constant clcd_e : integer := 7;
+	constant clcd_rs : integer := 6;
+	constant clcd_rw : integer := 5;
+	
+	type lcd_t is record
+		d	: unsigned(3 downto 0);
+		e	: std_logic;
+		rs	: std_logic;
+		rw	: std_logic;
+	end record;
+	
+	------------------------------------------------------------------
+	begin
+
+	proc_lcd_port:
+	process(rst, clk)
+	variable vlcd : lcd_t;
+	begin
+		if (rst = '1') then
+			dout	<= (others => '0');
+			vlcd.d	:= (others => '0');
+			vlcd.e	:= '0';
+			vlcd.rw	:= '1';
+			vlcd.rs	:= '0';
+		elsif rising_edge(clk) then
+			dout <= unsigned("0000" & lcd_d);
+			if we = '1' then
+				vlcd.d	:= din(3 downto 0);
+				vlcd.e	:= din(clcd_e);
+				vlcd.rs	:= din(clcd_rs);
+				vlcd.rw	:= din(clcd_rw);
+			end if;
+		end if;	
+		if vlcd.rw = '0' then	
+			lcd_d <= unsigned(vlcd.d);
+		else
+			lcd_d <= (others => 'Z');
+		end if;
+		lcd_e	<= vlcd.e;
+		lcd_rs	<= vlcd.rs;
+		lcd_rw	<= vlcd.rw;
+	end process;
+	------------------------------------------------------------------
+
+end Behavioral;