Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b

lib/VGA_ctrl/src/vga_backend.vhd

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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    11:25:45 10/15/05
+-- Design Name:    
+-- Module Name:    vga_backend - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+entity vga_backend is
+	Generic
+	(
+		sys_freq					: integer    		:= 100E6;
+		fifo_depth					: integer    		:= 2048;
+		fifo_almost_full_thresh		: natural 			:= 2000;
+		fifo_almost_empty_thresh	: natural 			:= 48;
+		tsvga						: vga_timespec_t	:= ts_vga_800_600_72
+	);
+	Port
+	(
+		-- System signals
+		sys_rst				: in std_logic;
+		sys_clk				: in std_logic;
+		vga_ready			: out std_logic;
+		
+		-- Buffered channel (Graphics plane)
+		color_in			: in color_t;
+		color_fifo_we		: in std_logic;
+		color_fifo_full		: out std_logic;
+		color_fifo_afull	: out std_logic;
+
+		-- Direct channel (Character plane)
+		direct_color_in		: in color_t;
+		direct_draw_en		: in std_logic;
+		
+		-- Status signals
+		stat_hsync			: out std_logic;
+		stat_vsync			: out std_logic;
+		stat_hready			: out std_logic;
+		stat_vready			: out std_logic;
+		stat_hscan			: out std_logic;
+		stat_vscan			: out std_logic;
+		stat_hpos			: out natural range 0 to tsvga.ts_h.ncyc_scan-1;
+		stat_vpos			: out natural range 0 to tsvga.ts_v.ncyc_scan-1;
+		
+		-- VGA domain signals
+		vga_clk_out			: out std_logic;
+		vga_color_out		: out color_t;
+		vga_blank_n			: out std_logic;
+		vga_sync_n			: out std_logic;
+		vga_hsync			: out std_logic;
+		vga_vsync			: out std_logic
+	);
+end vga_backend;
+
+architecture Behavioral of vga_backend is
+
+	signal scan_enable			: std_logic;
+	signal fifo_full			: std_logic;
+	signal fifo_empty			: std_logic;
+	signal fifo_almost_empty	: std_logic;
+	signal fifo_almost_full		: std_logic;
+	signal is_scan				: std_logic;
+	signal is_hscan				: std_logic;
+	signal is_vscan				: std_logic;
+	signal hsync				: std_logic;
+	signal vsync				: std_logic;
+	signal hready				: std_logic;
+	signal vready				: std_logic;
+	signal color				: color_t;
+	signal vga_clk				: std_logic;
+	signal dcm_locked			: std_logic;
+	signal rst					: std_logic;
+
+begin
+
+	vga_clk_out			<= vga_clk;
+	vga_ready			<= dcm_locked;
+	
+	inst_clkgen: entity work.clkgen
+	GENERIC MAP
+	(
+		sys_freq	=> sys_freq,
+		tsvga 		=> tsvga
+	)		
+	PORT MAP
+	(
+		rst			=> sys_rst,
+		clk			=> sys_clk,
+		vga_clk		=> vga_clk,
+		dcm_locked	=> dcm_locked
+	);
+
+	inst_vga_timing: entity work.vga_timing 
+	GENERIC MAP
+	(
+		tsvga => tsvga
+	)		
+	PORT MAP
+	(
+		sys_rst		=> sys_rst,
+		vga_clk		=> vga_clk,
+		vga_ce		=> dcm_locked,
+		sync_h		=> hsync,
+		sync_v		=> vsync,
+		scan_pos_h	=> stat_hpos,
+		scan_pos_v	=> stat_vpos,
+		is_scan_h	=> is_hscan,
+		is_scan_v	=> is_vscan,
+		scan_rdy_h	=> hready,
+		scan_rdy_v	=> vready
+	);
+
+	inst_linefifo: entity work.linefifo
+	GENERIC MAP 
+	(
+		depth				=> fifo_depth,
+		almost_full_thresh	=> fifo_almost_full_thresh,
+		almost_empty_thresh	=> fifo_almost_empty_thresh
+	)
+	PORT MAP(
+		rst			=> sys_rst,
+		clk_w		=> sys_clk,
+		clk_r		=> vga_clk,
+		we_w		=> color_fifo_we,
+		re_r		=> is_scan,
+		color_w		=> color_in,
+		color_r		=> color,
+		fifo_full	=> fifo_full,
+		fifo_empty	=> fifo_empty,
+		fifo_afull	=> fifo_almost_full,
+		fifo_aempty	=> fifo_almost_empty
+		
+	);
+
+	---------------------------------------------------------------------------------------------
+	rst					<= not dcm_locked;
+	stat_hsync			<= hsync;
+	stat_vsync			<= vsync;
+	stat_hscan			<= is_hscan;
+	stat_vscan			<= is_vscan;
+	stat_hready			<= hready;
+	stat_vready			<= vready;
+	
+	vga_blank_n			<= '1';
+	vga_sync_n			<= '0';
+	is_scan				<= is_hscan and is_vscan and scan_enable;
+	
+	color_fifo_full 	<= fifo_full;
+	color_fifo_afull 	<= fifo_almost_full;
+
+	---------------------------------------------------------------------------------------------
+	proc_vga_start:
+	process (rst, vga_clk)
+	begin
+		if rst = '1' then
+			scan_enable <= '0';
+		elsif rising_edge(vga_clk) then
+			if vsync = '1' then
+				if fifo_empty = '0' then
+					scan_enable <= '1';
+				else
+					scan_enable <= '0';
+				end if;	
+			end if;	
+		end if;
+	end process;
+
+	proc_vga_color_out:
+	process (rst, vga_clk)
+	variable do_scan : std_logic;
+	begin
+		if rst = '1' then
+			do_scan := '0';
+		elsif rising_edge(vga_clk) then
+			vga_color_out <= (X"00", X"00", X"00");
+			if do_scan = '1' then
+				if direct_draw_en = '1' then
+					vga_color_out <= direct_color_in;
+				else
+					vga_color_out <= color;
+				end if;	
+			end if;
+			do_scan := is_scan;
+		end if;
+	end process;
+		
+	---------------------------------------------------------------------------------------------
+	proc_vga_sync_out:
+	process (rst, vga_clk)
+	variable hsync_r : std_logic;
+	variable vsync_r : std_logic;
+	begin
+		if rst = '1' then
+			vga_hsync	<= tsvga.ts_h.sync_polarity;
+			vga_vsync	<= tsvga.ts_v.sync_polarity;
+			hsync_r		:= tsvga.ts_h.sync_polarity;
+			vsync_r		:= tsvga.ts_v.sync_polarity;
+		elsif rising_edge(vga_clk) then
+			vga_hsync	<= hsync_r;
+			vga_vsync	<= vsync_r;
+			hsync_r		:= hsync xor (not tsvga.ts_h.sync_polarity);
+			vsync_r		:= vsync xor (not tsvga.ts_v.sync_polarity);
+		end if;
+	end process;
+
+end Behavioral;