Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b
2008-08-23 08:20:30 +00:00
parent bfbeba5129
commit d3bd08bb52
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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    11:25:45 10/15/05
+-- Design Name:    
+-- Module Name:    vga_ctrl_core - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.vga_types.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clkgen is
+	Generic
+	(
+		sys_freq	: integer  			:= 100E6;
+		tsvga       : vga_timespec_t	:= ts_vga_800_600_72
+	);
+	Port
+	(
+		rst			: in std_logic;
+		clk			: in std_logic;
+		vga_clk		: out std_logic;
+		dcm_locked	: out std_logic
+	);
+end clkgen;
+
+architecture tech of clkgen is
+
+	signal vga_clk0               : std_logic;
+	signal dcm_clk0               : std_logic;
+	signal dcm_clk_fb             : std_logic;
+
+	begin
+	
+	-- Compnent instantiation
+	DCM_VGA_CLK_inst : DCM_BASE
+	generic map (
+		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+						   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+		CLKFX_DIVIDE => DCM_FREQ_D(sys_freq, tsvga.f_pxl_clk),   -- Can be any interger from 1 to 32
+		CLKFX_MULTIPLY => DCM_FREQ_M(sys_freq, tsvga.f_pxl_clk), -- Can be any integer from 2 to 32
+		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+		CLKIN_PERIOD => DCM_PERIOD(sys_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
+		CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
+		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
+		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
+		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+											 --   an integer from 0 to 15
+		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
+		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
+		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
+		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
+		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+	port map (
+		CLK0 => dcm_clk0,         -- 0 degree DCM CLK ouptput
+		CLK180 => open,     -- 180 degree DCM CLK output
+		CLK270 => open,     -- 270 degree DCM CLK output
+		CLK2X => open,       -- 2X DCM CLK output
+		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+		CLK90 => open,       -- 90 degree DCM CLK output
+		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
+		CLKFX => vga_clk0,       -- DCM CLK synthesis out (M/D)
+		CLKFX180 => open, -- 180 degree CLK synthesis out
+		LOCKED => dcm_locked,     -- DCM LOCK status output
+		CLKFB => dcm_clk_fb,       -- DCM clock feedback
+		CLKIN => clk,       -- Clock input (from IBUFG, BUFG or DCM)
+		RST => rst            -- DCM asynchronous reset input
+	);
+
+	BUFG_dcm_clk_fb : BUFG
+	port map
+	(
+		O => dcm_clk_fb,     -- Clock buffer output
+		I => dcm_clk0        -- Clock buffer input
+	);
+
+	BUFG_vga_clk : BUFG
+	port map
+	(
+		O => vga_clk,     -- Clock buffer output
+		I => vga_clk0     -- Clock buffer input
+	);
+
+
+end tech;