Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/src/tb_gray_counter.vhd

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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_gray_counter
+-- Module Name:   tb_gray_counter.vhd
+-- Project Name:  gray_counter package
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+ENTITY tb_gray_counter IS
+END tb_gray_counter;
+
+ARCHITECTURE behavior OF tb_gray_counter IS 
+
+	constant PERIOD		: time := 10 ns;
+	constant WIDTH		: integer := 3;
+
+	--Signals
+	signal gcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal bcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal gnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal bnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal rst			: STD_LOGIC := '1';
+	signal clk			: STD_LOGIC := '0';
+	signal ce			: STD_LOGIC := '0';
+
+BEGIN
+
+inst_gray_counter : entity work.gray_counter
+	generic map (width => WIDTH)
+	port map (
+		rst			=> rst,
+		clk			=> clk,
+		ce			=> ce, 
+		bcnt		=> bcnt,
+		bnxt		=> bnxt,
+		gcnt		=> gcnt,
+		gnxt		=> gnxt
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+ 	tb_counter : PROCESS
+ 	
+	BEGIN
+
+		wait for 4*PERIOD;
+		rst <= '0';
+		wait for 1*PERIOD;
+		ce <= '1';
+		wait for 3*PERIOD;
+		ce <= '0';
+		wait for 4*PERIOD;
+		ce <= '1';
+		wait for 1*PERIOD;
+		ce <= '0';
+		wait for 1*PERIOD;
+		ce <= '1';
+		
+		wait;
+		
+	END PROCESS;
+
+END behavior;