jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Initial import

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-08-23 08:20:30 +00:00
parent bfbeba5129
commit d3bd08bb52
160 changed files with 56260 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/FIFO/src/async_fifo_ctrl.vhd
+244
View File
@@ -0,0 +1,244 @@
-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: The call/return/data stack
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
LIBRARY WORK;
USE WORK.FIFO_CTRL_PKG.ALL;
entity async_fifo_ctrl is
Generic (
addr_width : integer := 3;
almost_full_thresh : integer := 6;
almost_empty_thresh : integer := 2
);
Port
(
rst : in STD_LOGIC;
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
ptr_w : out unsigned (addr_width-1 downto 0);
ptr_r : out unsigned (addr_width-1 downto 0);
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC
);
end async_fifo_ctrl;
architecture Behavioral of async_fifo_ctrl is
signal gcnt_w : unsigned (addr_width downto 0);
signal gcnt2_w : unsigned (addr_width downto 0);
signal bcnt2_aw : unsigned (addr_width downto 0);
signal bcnt_w : unsigned (addr_width downto 0);
signal gnxt_w : unsigned (addr_width downto 0);
signal bnxt_w : unsigned (addr_width downto 0);
signal gcnt_r : unsigned (addr_width downto 0);
signal gcnt2_r : unsigned (addr_width downto 0);
signal bcnt2_ar : unsigned (addr_width downto 0);
signal bcnt_r : unsigned (addr_width downto 0);
signal gnxt_r : unsigned (addr_width downto 0);
signal bnxt_r : unsigned (addr_width downto 0);
signal empty, full : std_logic;
signal write_inhibit, read_inhibit : std_logic;
signal winc, rinc : std_logic;
-- synthesis translate_off
signal diffw : signed (addr_width downto 0);
signal diffr : signed (addr_width downto 0);
-- synthesis translate_on
begin
ptr_w <= bcnt_w(addr_width-1 downto 0);
ptr_r <= bcnt_r(addr_width-1 downto 0);
winc <= we and (not write_inhibit);
rinc <= re and (not read_inhibit);
fifo_full <= write_inhibit;
fifo_empty <= read_inhibit;
proc_write_inhibit:
process(rst, clk_w)
begin
if rst = '1' then
write_inhibit <= '0';
elsif rising_edge(clk_w) then
write_inhibit <= full;
end if;
end process;
proc_read_inhibit:
process(rst, clk_r)
begin
if rst = '1' then
read_inhibit <= '1';
elsif rising_edge(clk_r) then
read_inhibit <= empty;
end if;
end process;
proc_sync_grptr:
process(clk_w)
variable p1, p2 : unsigned (addr_width downto 0);
begin
if rising_edge(clk_w) then
gcnt2_r <= p2;
p2 := p1;
p1 := gcnt_r;
end if;
end process;
proc_ptr_gwptr:
process(clk_r)
variable p1, p2 : unsigned (addr_width downto 0);
begin
if rising_edge(clk_r) then
gcnt2_w <= p2;
p2 := p1;
p1 := gcnt_w;
end if;
end process;
proc_status_full:
process(gnxt_w, gcnt2_r)
begin
if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
full <= '1';
else
full <= '0';
end if;
end process;
proc_status_empty:
process(gnxt_r, gcnt2_w)
begin
if (gnxt_r = gcnt2_w) then
empty <= '1';
else
empty <= '0';
end if;
end process;
proc_sync_arptr:
process(clk_w)
variable p1, p2 : unsigned (addr_width downto 0);
begin
if rising_edge(clk_w) then
bcnt2_ar <= p2;
p2 := p1;
p1 := bcnt_r;
end if;
end process;
proc_ptr_awptr:
process(clk_r)
variable p1, p2 : unsigned (addr_width downto 0);
begin
if rising_edge(clk_r) then
bcnt2_aw <= p2;
p2 := p1;
p1 := bcnt_w;
end if;
end process;
proc_status_almost_full:
process(rst, clk_w)
variable diff : unsigned (addr_width downto 0);
begin
-- synthesis translate_off
diffw <= signed(diff);
-- synthesis translate_on
if rst = '1' then
fifo_afull <= '0';
diff := (others => '0');
elsif rising_edge(clk_w) then
if diff >= almost_full_thresh-1 then
fifo_afull <= '1';
else
fifo_afull <= '0';
end if;
diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
end if;
end process;
proc_status_almost_empty:
process(rst, clk_r)
variable diff : unsigned (addr_width downto 0);
begin
-- synthesis translate_off
diffr <= signed(diff);
-- synthesis translate_on
if rst = '1' then
fifo_aempty <= '1';
diff := (others => '0');
elsif rising_edge(clk_r) then
if diff <= almost_empty_thresh+1 then
fifo_aempty <= '1';
else
fifo_aempty <= '0';
end if;
diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
end if;
end process;
inst_gray_counter_w : entity work.gray_counter
generic map (
width => addr_width+1,
init_value => 0
)
port map (
rst => rst,
clk => clk_w,
ce => winc,
bcnt => bcnt_w,
bnxt => bnxt_w,
gcnt => gcnt_w,
gnxt => gnxt_w
);
inst_gray_counter_r : entity work.gray_counter
generic map (
width => addr_width+1,
init_value => 0
)
port map (
rst => rst,
clk => clk_r,
ce => rinc,
bcnt => bcnt_r,
bnxt => bnxt_r,
gcnt => gcnt_r,
gnxt => gnxt_r
);
end Behavioral;