Initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@5 cc03376c-175c-47c8-b038-4cd826a8556b
2008-08-23 08:20:30 +00:00
parent bfbeba5129
commit d3bd08bb52
160 changed files with 56260 additions and 0 deletions
@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/dpram.vhd"
+vcom -explicit  -93 "../src/async_fifo_ctrl.vhd"
+vcom -explicit  -93 "../src/tb_async_fifo_ctrl.vhd"
+vsim -t 1ps   -lib work tb_async_fifo_ctrl
+view wave
+do {tb_async_fifo_ctrl.wdo}
+view structure
+view signals
+
+run 10us
@@ -0,0 +1,36 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/rst
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_w
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_w
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_r
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/re
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_r
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_empty
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_full
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/dout
+add wave -noupdate -format Logic /tb_async_fifo_ctrl/uut/inst_gray_counter_w/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/uut/bnxt_w
+add wave -noupdate -format Literal /tb_async_fifo_ctrl/uut/bcnt_r
+add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffw
+add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
+configure wave -namecolwidth 190
+configure wave -valuecolwidth 80
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {115874 ps} {612358 ps}
@@ -0,0 +1,13 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/tb_gray_counter.vhd"
+vsim -t 1ps   -lib work tb_gray_counter
+view wave
+do {tb_gray_counter.wdo}
+view structure
+view signals
+
+run 1us
@@ -0,0 +1,25 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_gray_counter/rst
+add wave -noupdate -format Logic /tb_gray_counter/ce
+add wave -noupdate -format Logic /tb_gray_counter/clk
+add wave -noupdate -format Literal /tb_gray_counter/bcnt
+add wave -noupdate -format Literal /tb_gray_counter/bnxt
+add wave -noupdate -format Literal /tb_gray_counter/gcnt
+add wave -noupdate -format Literal /tb_gray_counter/gnxt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {20898 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {134759 ps}
@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/dpram.vhd"
+vcom -explicit  -93 "../src/sync_fifo_ctrl.vhd"
+vcom -explicit  -93 "../src/tb_sync_fifo_ctrl.vhd"
+vsim -t 1ps   -lib work tb_sync_fifo_ctrl
+view wave
+do {tb_sync_fifo_ctrl.wdo}
+view structure
+view signals
+
+run 10us
@@ -0,0 +1,32 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/rst
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_w
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/re
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_r
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_empty
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_empty
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_full
+add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/dout
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pw_next
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pr_next
+add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/diff
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {290000 ps} 0}
+configure wave -namecolwidth 190
+configure wave -valuecolwidth 80
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {2166667 ps}
@@ -0,0 +1,244 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+entity async_fifo_ctrl is
+	Generic (
+		addr_width : integer := 3;
+		almost_full_thresh : integer := 6;
+		almost_empty_thresh : integer := 2
+	);
+	Port
+	(
+		rst					: in  STD_LOGIC;
+		clk_w				: in  STD_LOGIC;
+		clk_r				: in  STD_LOGIC;
+		we					: in  STD_LOGIC;
+		re					: in  STD_LOGIC;
+		ptr_w				: out unsigned (addr_width-1 downto 0);
+		ptr_r				: out unsigned (addr_width-1 downto 0);
+		fifo_full			: out STD_LOGIC;
+		fifo_empty			: out STD_LOGIC;
+		fifo_afull			: out STD_LOGIC;
+		fifo_aempty			: out STD_LOGIC
+	);
+end async_fifo_ctrl;
+
+architecture Behavioral of async_fifo_ctrl is
+
+	signal gcnt_w		: unsigned (addr_width downto 0);
+	signal gcnt2_w		: unsigned (addr_width downto 0);
+	signal bcnt2_aw		: unsigned (addr_width downto 0);
+	signal bcnt_w		: unsigned (addr_width downto 0);
+	signal gnxt_w		: unsigned (addr_width downto 0);
+	signal bnxt_w		: unsigned (addr_width downto 0);
+	signal gcnt_r		: unsigned (addr_width downto 0);
+	signal gcnt2_r		: unsigned (addr_width downto 0);
+	signal bcnt2_ar		: unsigned (addr_width downto 0);
+	signal bcnt_r		: unsigned (addr_width downto 0);
+	signal gnxt_r		: unsigned (addr_width downto 0);
+	signal bnxt_r		: unsigned (addr_width downto 0);
+
+	signal empty, full : std_logic;
+	signal write_inhibit, read_inhibit : std_logic;
+	signal winc, rinc : std_logic;
+
+	-- synthesis translate_off
+	signal diffw		: signed (addr_width downto 0);
+	signal diffr		: signed (addr_width downto 0);
+	-- synthesis translate_on
+
+begin
+
+	ptr_w		<= bcnt_w(addr_width-1 downto 0);
+	ptr_r		<= bcnt_r(addr_width-1 downto 0);
+	winc		<= we and (not write_inhibit);
+	rinc		<= re and (not read_inhibit);
+	fifo_full	<= write_inhibit;
+	fifo_empty	<= read_inhibit;
+	
+proc_write_inhibit:
+	process(rst, clk_w)
+	begin
+		if rst = '1' then
+			write_inhibit	<= '0';
+		elsif rising_edge(clk_w) then
+			write_inhibit	<= full;
+		end if;
+	end process;
+	
+proc_read_inhibit:
+	process(rst, clk_r)
+	begin
+		if rst = '1' then
+			read_inhibit	<= '1';
+		elsif rising_edge(clk_r) then
+			read_inhibit	<= empty;
+		end if;
+	end process;
+
+proc_sync_grptr:
+	process(clk_w)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_w) then
+			gcnt2_r <= p2;
+			p2 := p1;
+			p1 := gcnt_r;
+		end if;
+	end process;
+
+proc_ptr_gwptr:
+	process(clk_r)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_r) then
+			gcnt2_w <= p2;
+			p2 := p1;
+			p1 := gcnt_w;
+		end if;
+	end process;
+	
+proc_status_full:
+	process(gnxt_w, gcnt2_r)
+	begin
+		if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
+			full <= '1';
+		else
+			full <= '0';
+		end if;
+	end process;
+
+proc_status_empty:
+	process(gnxt_r, gcnt2_w)
+	begin
+		if (gnxt_r = gcnt2_w) then
+			empty <= '1';
+		else
+			empty <= '0';
+		end if;
+	end process;
+	
+proc_sync_arptr:
+	process(clk_w)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_w) then
+			bcnt2_ar <= p2;
+			p2 := p1;
+			p1 := bcnt_r;
+		end if;
+	end process;
+
+proc_ptr_awptr:
+	process(clk_r)
+	variable p1, p2	: unsigned (addr_width downto 0);
+	begin
+		if rising_edge(clk_r) then
+			bcnt2_aw <= p2;
+			p2 := p1;
+			p1 := bcnt_w;
+		end if;
+	end process;
+	
+proc_status_almost_full:
+	process(rst, clk_w)
+	variable diff : unsigned (addr_width downto 0);
+	begin
+	-- synthesis translate_off
+		diffw <= signed(diff);
+	-- synthesis translate_on
+		if rst = '1' then
+			fifo_afull <= '0';
+			diff := (others => '0');
+		elsif rising_edge(clk_w) then
+			if diff >= almost_full_thresh-1 then
+				fifo_afull <= '1';
+			else
+				fifo_afull <= '0';
+			end if;	
+			diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
+		end if;
+	end process;
+
+proc_status_almost_empty:
+	process(rst, clk_r)
+	variable diff : unsigned (addr_width downto 0);
+	begin
+	-- synthesis translate_off
+		diffr <= signed(diff);
+	-- synthesis translate_on
+		if rst = '1' then
+			fifo_aempty <= '1';
+			diff := (others => '0');
+		elsif rising_edge(clk_r) then
+			if diff <= almost_empty_thresh+1 then
+				fifo_aempty <= '1';
+			else
+				fifo_aempty <= '0';
+			end if;	
+			diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
+		end if;
+	end process;
+
+inst_gray_counter_w : entity work.gray_counter
+	generic map (
+		width => addr_width+1,
+		init_value => 0
+		)
+	port map (
+		rst			=> rst,
+		clk			=> clk_w,
+		ce			=> winc, 
+		bcnt		=> bcnt_w,
+		bnxt		=> bnxt_w,
+		gcnt		=> gcnt_w,
+		gnxt		=> gnxt_w
+	);
+
+inst_gray_counter_r : entity work.gray_counter
+	generic map (
+		width => addr_width+1,
+		init_value => 0
+		)
+	port map (
+		rst			=> rst,
+		clk			=> clk_r,
+		ce			=> rinc, 
+		bcnt		=> bcnt_r,
+		bnxt		=> bnxt_r,
+		gcnt		=> gcnt_r,
+		gnxt		=> gnxt_r
+	);
+
+end Behavioral;
+
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/dpram.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram;
+
+architecture Behavioral of dpram is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+	if en_b = '1' then
+		dout_b <= RAM(to_integer(addr_b));
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+
@@ -0,0 +1,46 @@
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/fifo_ctrl_pkg.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+package fifo_ctrl_pkg is
+
+	-- Constants
+	-- Types
+	
+	-- Functions
+	function bin2gray(xb : unsigned) return unsigned;
+	function gray2bin(xg : unsigned) return unsigned;
+
+end fifo_ctrl_pkg;
+
+package body fifo_ctrl_pkg is
+
+	function bin2gray(xb : unsigned) return unsigned is
+	variable xg : unsigned(xb'left downto xb'right);
+	begin
+	
+    	xg(xg'left) := xb(xb'left);
+		for i in 1 to xb'left loop
+			xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
+		end loop;
+	
+		return xg;
+	end bin2gray;
+	
+	function gray2bin(xg : unsigned) return unsigned is
+	variable xb : unsigned(xg'left downto xg'right);
+	begin
+
+     	xb(xb'left) := xg(xg'left);
+		for i in 1 to xg'left loop
+			xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
+		end loop;
+		
+		return xb;
+	end gray2bin;
+
+end fifo_ctrl_pkg;
+
@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+entity gray_counter is
+	Generic (
+		width : natural := 3;
+		init_value : natural := 0
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		bcnt		: out unsigned (width-1 downto 0);
+		bnxt		: out unsigned (width-1 downto 0);
+		gcnt		: out unsigned (width-1 downto 0);
+		gnxt		: out unsigned (width-1 downto 0)
+	);
+end gray_counter;
+
+architecture Behavioral of gray_counter is
+
+	signal cntb : unsigned (width-1 downto 0);
+	signal nxtb : unsigned (width-1 downto 0);
+	signal cntg : unsigned (width-1 downto 0);
+	signal nxtg : unsigned (width-1 downto 0);
+
+begin
+
+	bnxt	<= nxtb;
+	gnxt	<= nxtg;
+
+	process(rst, clk, ce, cntb, nxtb)
+	begin
+		if rst = '1' then
+			cntb	<= to_unsigned(init_value, width);
+			nxtb	<= to_unsigned(init_value, width);
+			cntg	<= to_unsigned(init_value, width);
+			nxtg	<= to_unsigned(init_value, width);
+			bcnt	<= to_unsigned(init_value, width);
+			gcnt	<= to_unsigned(init_value, width);
+		else
+			if rising_edge(clk) then
+				bcnt	<= nxtb;
+				gcnt	<= nxtg;
+				cntb	<= nxtb;
+				cntg	<= nxtg;
+			end if;	
+			nxtg <= bin2gray(nxtb);
+			nxtb <= cntb;
+			if ce = '1' then
+				nxtb <= cntb + 1;
+			end if;	
+		end if;	
+	end process;
+
+end Behavioral;
+
@@ -0,0 +1,199 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity sync_fifo_ctrl is
+	Generic (
+		addr_width : integer := 3;
+		almost_full_thresh : integer := 6;
+		almost_empty_thresh : integer := 2
+	);
+	Port
+	(
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		we				: in  STD_LOGIC;
+		re				: in  STD_LOGIC;
+		ptr_w			: out unsigned (addr_width-1 downto 0);
+		ptr_r			: out unsigned (addr_width-1 downto 0);
+		fifo_full		: out STD_LOGIC;
+		fifo_empty		: out STD_LOGIC;
+		fifo_afull		: out STD_LOGIC;
+		fifo_aempty		: out STD_LOGIC
+	);
+end sync_fifo_ctrl;
+
+architecture Behavioral of sync_fifo_ctrl is
+
+	signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
+	signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
+	signal empty, full : std_logic;
+	signal pre_empty, pre_full : std_logic;
+	signal was_write : std_logic;
+	signal write, read : std_logic;
+	signal diff : unsigned (addr_width downto 0);
+	
+begin
+
+	read <= '1' when re = '1' and empty = '0' else '0';
+	write <= '1' when we = '1' and full = '0' else '0';
+
+	fifo_full <= full;
+	fifo_empty <= empty;
+
+
+proc_diff_gen:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			diff <= (others => '0');
+		elsif rising_edge(clk) then
+			if write = '1' and read = '0' then
+				diff <= diff + 1;
+			elsif write = '0' and read = '1' then
+				diff <= diff - 1;
+			end if;
+		end if;
+	end process;
+
+proc_status_almost_full:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			fifo_afull <= '0';
+		elsif rising_edge(clk) then
+			if diff >= almost_full_thresh-1 then
+				fifo_afull <= '1';
+			else
+				fifo_afull <= '0';
+			end if;	
+		end if;
+	end process;
+
+proc_status_almost_empty:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			fifo_aempty <= '1';
+		elsif rising_edge(clk) then
+			if diff <= almost_empty_thresh+1 then
+				fifo_aempty <= '1';
+			else
+				fifo_aempty <= '0';
+			end if;	
+		end if;
+	end process;
+
+proc_full_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			full <= '0';
+		elsif rising_edge(clk) then
+			full <= pre_full;
+		end if;
+	end process;
+	
+proc_empty_reg:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			empty <= '1';
+		elsif rising_edge(clk) then
+			empty <= pre_empty;
+		end if;
+	end process;
+	
+proc_status_w:
+	process(was_write, pW_next, pR_next, pW, pR, we, re)
+	begin
+		if (pW_next = pR) and (we = '1' or was_write = '1') then
+			pre_full <= '1';
+		else
+			pre_full <= '0';
+		end if;
+		if (pR_next = pW) and (re = '1' or was_write = '0') then
+			pre_empty <= '1';
+		else
+			pre_empty <= '0';
+		end if;
+	end process;
+
+proc_flag_write:
+	process(rst, clk)
+	begin
+		if rst = '1' then
+			was_write <= '0';
+		elsif rising_edge(clk) then
+			if write = '1' then
+				was_write <= '1';
+			elsif read = '1' then
+				was_write <= '0';
+			end if;
+		end if;
+	end process;
+	
+proc_ptr_w:
+	process(rst, clk, pW, we, full)
+	begin
+		if rst = '1' then
+			pW <= to_unsigned(0, addr_width);
+			pW_next <= to_unsigned(0, addr_width);
+		elsif rising_edge(clk) then
+			if we = '1' then 
+				pW <= pW_next;
+			end if;
+		end if;
+		pW_next <= pW;
+		if we = '1' and full = '0' then 
+			pW_next <= pW + 1;
+		end if;
+		ptr_w		<= pW;
+	end process;
+
+proc_ptr_r:
+	process(rst, clk, pR_next, pR, re, empty)
+	begin
+		if rst = '1' then
+			pR <= to_unsigned(0, addr_width);
+			pR_next <= to_unsigned(0, addr_width);
+		elsif rising_edge(clk) then
+			if re = '1' then
+				pR <= pR_next;
+			end if;	
+		end if;
+		pR_next	<= pR;
+		if re = '1' and empty = '0' then
+			pR_next	<= pR + 1;
+		end if;
+		ptr_r		<= pR_next;
+	end process;
+
+end Behavioral;
+
@@ -0,0 +1,176 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_async_fifo_ctrl IS
+END tb_async_fifo_ctrl;
+
+ARCHITECTURE behavior OF tb_async_fifo_ctrl IS 
+
+	--Constants
+	constant PERIOD_W 	: time := 10 ns;
+	constant PERIOD_R 	: time := 20 ns;
+	constant ADDR_WIDTH : integer := 3;
+
+	--Inputs
+	signal rst					: STD_LOGIC := '1';
+	signal clk_w				: STD_LOGIC := '0';
+	signal clk_r				: STD_LOGIC := '0';
+	signal we					: STD_LOGIC := '0';
+	signal re					: STD_LOGIC := '0';
+	signal din					: unsigned (7 downto 0);
+	--Outputs
+
+	signal ptr_w				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal ptr_r				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal dout					: unsigned (7 downto 0);
+	signal fifo_full			: STD_LOGIC;
+	signal fifo_empty			: STD_LOGIC;
+	signal fifo_almost_full		: STD_LOGIC;
+	signal fifo_almost_empty	: STD_LOGIC;
+	signal mem_we				: STD_LOGIC;
+
+	signal write_en				: STD_LOGIC := '0';
+	signal read_en				: STD_LOGIC := '0';
+
+	signal wdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata2				: unsigned (7 downto 0) := (others => '0');
+
+BEGIN
+
+	din <= wdata;
+	
+	-- Instantiate the Unit Under Test (UUT)
+	uut: entity work.async_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> ADDR_WIDTH,
+		almost_full_thresh	=> 6,
+		almost_empty_thresh	=> 2
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk_w		=>	clk_w,
+		clk_r		=>	clk_r,
+		we			=>	we,
+		re			=>	re,
+		ptr_w		=>	ptr_w,
+		ptr_r		=>	ptr_r,
+		fifo_full	=>	fifo_full,
+		fifo_empty	=>	fifo_empty,
+		fifo_afull	=>	fifo_almost_full,
+		fifo_aempty	=>	fifo_almost_empty
+
+	);
+
+	inst_dpram: entity work.dpram
+	GENERIC MAP (
+		addr_width	=> ADDR_WIDTH,
+		data_width	=> 8
+	)
+	PORT MAP(
+		clka		=> clk_w,
+		clkb		=> clk_r,
+		en_a		=> '1',
+		en_b		=> '1',
+		we_a		=> mem_we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> din,
+		dout_b		=> dout
+	);
+
+ 	tb_clk_w : PROCESS
+	BEGIN
+		clk_w <= not clk_w;
+		wait for PERIOD_W/2;
+	END PROCESS;
+
+ 	tb_clk_r : PROCESS
+	BEGIN
+		clk_r <= not clk_r;
+		wait for PERIOD_R/2;
+	END PROCESS;
+
+ 	tb_write : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 5*PERIOD_W;
+		rst			<= '0';
+		wait for 5*PERIOD_W;
+		write_en <= '1';
+		wait for 15*PERIOD_W;
+		write_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+ 	tb_read : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 15*PERIOD_R;
+		read_en <= '1';
+		
+		wait; 
+		
+	END PROCESS;
+	
+	we <= write_en and not fifo_full;
+	mem_we <= we;
+	
+ 	tb_w : PROCESS(rst, clk_w)
+	BEGIN
+
+		if rst = '1' then
+			wdata <= (others => '0');
+		elsif rising_edge(clk_w) then
+			if we = '1' then
+				wdata <= wdata + 1;
+			end if;				
+		end if;	
+
+	END PROCESS;
+	
+	re	<= read_en and not fifo_empty;
+	
+ 	tb_r : PROCESS(rst, clk_r)
+	BEGIN
+
+		if rst = '1' then
+			rdata <= (others => '0');
+		elsif rising_edge(clk_r) then
+			rdata2 <= rdata;
+			if re = '1' then
+				assert rdata2 = dout report "FIFO read error!" severity failure;
+				rdata <= rdata + 1;
+			end if;				
+		end if;	
+		
+	END PROCESS;
+
+END behavior;
@@ -0,0 +1,83 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_gray_counter
+-- Module Name:   tb_gray_counter.vhd
+-- Project Name:  gray_counter package
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+LIBRARY WORK;
+USE WORK.FIFO_CTRL_PKG.ALL;
+
+ENTITY tb_gray_counter IS
+END tb_gray_counter;
+
+ARCHITECTURE behavior OF tb_gray_counter IS 
+
+	constant PERIOD		: time := 10 ns;
+	constant WIDTH		: integer := 3;
+
+	--Signals
+	signal gcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal bcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal gnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal bnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
+	signal rst			: STD_LOGIC := '1';
+	signal clk			: STD_LOGIC := '0';
+	signal ce			: STD_LOGIC := '0';
+
+BEGIN
+
+inst_gray_counter : entity work.gray_counter
+	generic map (width => WIDTH)
+	port map (
+		rst			=> rst,
+		clk			=> clk,
+		ce			=> ce, 
+		bcnt		=> bcnt,
+		bnxt		=> bnxt,
+		gcnt		=> gcnt,
+		gnxt		=> gnxt
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+ 	tb_counter : PROCESS
+ 	
+	BEGIN
+
+		wait for 4*PERIOD;
+		rst <= '0';
+		wait for 1*PERIOD;
+		ce <= '1';
+		wait for 3*PERIOD;
+		ce <= '0';
+		wait for 4*PERIOD;
+		ce <= '1';
+		wait for 1*PERIOD;
+		ce <= '0';
+		wait for 1*PERIOD;
+		ce <= '1';
+		
+		wait;
+		
+	END PROCESS;
+
+END behavior;
@@ -0,0 +1,221 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-----------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE STD.TEXTIO.ALL;
+
+-- LIBRARY WORK;
+-- USE.YOURLIB.WHATELSE
+
+ENTITY tb_sync_fifo_ctrl IS
+END tb_sync_fifo_ctrl;
+
+ARCHITECTURE behavior OF tb_sync_fifo_ctrl IS 
+
+	--Constants
+	constant PERIOD 	: time := 10 ns;
+	constant ADDR_WIDTH : integer := 3;
+
+	--Inputs
+	signal rst					: STD_LOGIC := '1';
+	signal clk					: STD_LOGIC := '0';
+	signal we					: STD_LOGIC := '0';
+	signal re					: STD_LOGIC := '0';
+	signal din					: unsigned (7 downto 0);
+	--Outputs
+
+	signal ptr_w				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal ptr_r				: unsigned (ADDR_WIDTH-1 downto 0);
+	signal dout					: unsigned (7 downto 0);
+	signal fifo_full			: STD_LOGIC;
+	signal fifo_empty			: STD_LOGIC;
+	signal fifo_almost_full		: STD_LOGIC;
+	signal fifo_almost_empty	: STD_LOGIC;
+	signal mem_we				: STD_LOGIC;
+
+	signal write_en				: STD_LOGIC := '0';
+	signal read_en				: STD_LOGIC := '0';
+
+	signal wdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata				: unsigned (7 downto 0) := (others => '0');
+	signal rdata2				: unsigned (7 downto 0) := (others => '0');
+
+BEGIN
+
+	din <= wdata;
+	
+	-- Instantiate the Unit Under Test (UUT)
+	uut: entity work.sync_fifo_ctrl
+	GENERIC MAP
+	(
+		addr_width			=> ADDR_WIDTH,
+		almost_full_thresh	=> 6,
+		almost_empty_thresh	=> 2
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk			=>	clk,
+		we			=>	we,
+		re			=>	re,
+		ptr_w		=>	ptr_w,
+		ptr_r		=>	ptr_r,
+		fifo_full	=>	fifo_full,
+		fifo_empty	=>	fifo_empty,
+		fifo_afull	=>	fifo_almost_full,
+		fifo_aempty	=>	fifo_almost_empty
+
+	);
+
+	inst_dpram: entity work.dpram
+	GENERIC MAP (
+		addr_width	=> ADDR_WIDTH,
+		data_width	=> 8
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> '1',
+		en_b		=> '1',
+		we_a		=> mem_we,
+		addr_a		=> ptr_w,
+		addr_b		=> ptr_r,
+		din_a		=> din,
+		dout_b		=> dout
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+ 	tb_write : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 5*PERIOD;
+		rst			<= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		wait for 7*PERIOD;
+		write_en <= '1';
+		wait for 1*PERIOD;
+		write_en <= '0';
+		wait for 1*PERIOD;
+		write_en <= '1';
+		wait for 1*PERIOD;
+		write_en <= '0';
+		wait for 3*PERIOD;
+		write_en <= '1';
+		wait for 4*PERIOD;
+		write_en <= '0';
+		wait for 17*PERIOD;
+		write_en <= '1';
+		wait for 25*PERIOD;
+		write_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+ 	tb_read : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 25*PERIOD;
+		read_en <= '1';
+		wait for 25*PERIOD;
+		read_en <= '0';
+		wait for 25*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 5*PERIOD;
+		read_en <= '1';
+		wait for 1*PERIOD;
+		read_en <= '0';
+		wait for 7*PERIOD;
+		read_en <= '1';
+		wait for 15*PERIOD;
+		read_en <= '0';
+		
+		wait; 
+		
+	END PROCESS;
+
+	we <= write_en and not fifo_full;
+	mem_we <= we;
+
+ 	tb_w : PROCESS(rst, clk)
+	BEGIN
+
+		if rst = '1' then
+			wdata <= (others => '0');
+		elsif rising_edge(clk) then
+			if we = '1' then
+				wdata <= wdata + 1;
+			end if;				
+		end if;	
+
+	END PROCESS;
+	
+	re	<= read_en and not fifo_empty;
+
+ 	tb_r : PROCESS(rst, clk)
+	BEGIN
+
+		if rst = '1' then
+			rdata <= (others => '0');
+		elsif rising_edge(clk) then
+			rdata2 <= rdata;
+			if re = '1' then
+				assert rdata = dout report "FIFO read error!" severity failure;
+				rdata <= rdata + 1;
+			end if;				
+		end if;	
+		
+	END PROCESS;
+
+END behavior;