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- fixed cycle counter

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1229 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-25 10:51:06 +00:00
parent d0da5022ef
commit d1893931ed
2 changed files with 11 additions and 15 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+9 -13
View File
@@ -54,16 +54,17 @@ architecture behaviour of sdram_cmd is
subtype cycle_cnt_t is natural range 0 to 15; subtype cycle_cnt_t is natural range 0 to 15;
subtype burst_cnt_t is natural range 0 to 2**(LMR_BL_CURR)-1; subtype burst_cnt_t is natural range 0 to 2**(LMR_BL_CURR)-1;
signal st_sdr, st_sdr_next : sdr_state_t; signal cc_preset : cycle_cnt_t;
signal cc_preset : natural range 0 to 15;
signal cc_load_en : std_logic; signal cc_load_en : std_logic;
signal cycle_finished : std_logic; signal cycle_finished : std_logic;
signal cycle_cnt : cycle_cnt_t;
signal burst_load_en : std_logic; signal burst_load_en : std_logic;
signal burst_finished : std_logic; signal burst_finished : std_logic;
signal burst_cnt : burst_cnt_t; signal burst_cnt : burst_cnt_t;
signal st_sdr, st_sdr_next : sdr_state_t;
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t := constant TIMING : part_timing_array_t :=
-- command cycle_cnt -- command cycle_cnt
@@ -248,20 +249,15 @@ fsm_sdr_state_next:
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
cycle_counter: cycle_counter:
process (clk) process (clk)
variable cycle_cnt : natural range 0 to 15;
begin begin
if rising_edge(clk) then if rising_edge(clk) then
cycle_finished <= '0'; cycle_finished <= '0';
if rst = '1' then if cc_load_en = '1' then
cycle_cnt := 0; cycle_cnt <= cc_preset;
elsif cycle_cnt /= 0 then
cycle_cnt <= cycle_cnt - 1;
else else
if cc_load_en = '1' then cycle_finished <= '1';
cycle_cnt := cc_preset;
elsif cycle_cnt /= 0 then
cycle_cnt := cycle_cnt - 1;
else
cycle_finished <= '1';
end if;
end if; end if;
end if; end if;
end process; end process;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
+1 -1
View File
@@ -47,7 +47,7 @@ package sdram_config is
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_PRE_ALL : std_logic := '1';
constant ENABLE_AUTO_PRE : std_logic := '0'; constant ENABLE_AUTO_PRE : std_logic := '0';
constant LMR_BL_CURR : natural := LMR_BL8; constant LMR_BL_CURR : natural := LMR_BL2;
-- DDR-SDR TIMING constants ------------------------------------------------------------------ -- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh