From d1893931ede8f9719ef205223f2ad8d8044a2200 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 25 May 2015 10:51:06 +0000 Subject: [PATCH] - fixed cycle counter git-svn-id: http://moon:8086/svn/vhdl/trunk@1229 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd | 24 ++++++++----------- .../src/sdram_config_mt48lc16m16.vhd | 2 +- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd index ff119c7..da213e3 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd @@ -54,16 +54,17 @@ architecture behaviour of sdram_cmd is subtype cycle_cnt_t is natural range 0 to 15; subtype burst_cnt_t is natural range 0 to 2**(LMR_BL_CURR)-1; - signal st_sdr, st_sdr_next : sdr_state_t; - - signal cc_preset : natural range 0 to 15; + signal cc_preset : cycle_cnt_t; signal cc_load_en : std_logic; signal cycle_finished : std_logic; + signal cycle_cnt : cycle_cnt_t; signal burst_load_en : std_logic; signal burst_finished : std_logic; signal burst_cnt : burst_cnt_t; + signal st_sdr, st_sdr_next : sdr_state_t; + type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; constant TIMING : part_timing_array_t := -- command cycle_cnt @@ -248,21 +249,16 @@ fsm_sdr_state_next: ------------------------------------------------------------------------------------------ cycle_counter: process (clk) - variable cycle_cnt : natural range 0 to 15; begin if rising_edge(clk) then cycle_finished <= '0'; - if rst = '1' then - cycle_cnt := 0; + if cc_load_en = '1' then + cycle_cnt <= cc_preset; + elsif cycle_cnt /= 0 then + cycle_cnt <= cycle_cnt - 1; else - if cc_load_en = '1' then - cycle_cnt := cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt := cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; + cycle_finished <= '1'; + end if; end if; end process; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd index 71e569f..d01234b 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd @@ -47,7 +47,7 @@ package sdram_config is constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_AUTO_PRE : std_logic := '0'; - constant LMR_BL_CURR : natural := LMR_BL8; + constant LMR_BL_CURR : natural := LMR_BL2; -- DDR-SDR TIMING constants ------------------------------------------------------------------ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh