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- added blitter loop

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git-svn-id: http://moon:8086/svn/vhdl/trunk@677 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-22 22:37:20 +00:00
parent fc1a9e7b3d
commit cd8a49ad18
1 changed files with 85 additions and 78 deletions
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lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+12 -5
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@@ -83,9 +83,9 @@ BEGIN
inst_vga_frontend64 : entity work.vga_frontend64
GENERIC MAP
(
fifo_depth => 256,
fifo_almost_full_thresh => 240,
fifo_almost_empty_thresh => 16,
fifo_depth => 2048,
fifo_almost_full_thresh => 2048-128,
fifo_almost_empty_thresh => 512,
tsvga => tsvga
)
PORT MAP
@@ -351,6 +351,8 @@ STIMULUS: process
wait for 60000*CLK_PERIOD;
for i in 0 to 3 loop
-- BLIT test
-- Read status
CYC_O <= '1';
@@ -402,7 +404,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_007F";
SDAT_O <= X"0000_12BF";
ADDR_O <= X"0000_0038";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -411,7 +413,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_00FF";
SDAT_O <= X"0000_0000";
ADDR_O <= X"0000_003C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -427,6 +429,11 @@ STIMULUS: process
CYC_O <= '0';
WE_O <= '0';
wait for 600000*CLK_PERIOD;
end loop;
wait;
end process;