diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
index 9ec5f25..5ce0c34 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
@@ -83,9 +83,9 @@ BEGIN
 inst_vga_frontend64 : entity work.vga_frontend64
 	GENERIC MAP
 	(
-		fifo_depth					=> 256,
-		fifo_almost_full_thresh		=> 240,
-		fifo_almost_empty_thresh	=> 16,
+		fifo_depth					=> 2048,
+		fifo_almost_full_thresh		=> 2048-128,
+		fifo_almost_empty_thresh	=> 512,
 		tsvga						=> tsvga
 	)
 	PORT MAP
@@ -351,81 +351,88 @@ STIMULUS: process
 
 		wait for 60000*CLK_PERIOD;
 
-		-- BLIT test
-		-- Read status
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
-		-- set src addr
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"4100_0000";
-		ADDR_O	<= X"0000_0020";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		-- set src dim-x
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0140";
-		ADDR_O	<= X"0000_002C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		-- set dst addr
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"4200_0000";
-		ADDR_O	<= X"0000_0028";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		-- set dst dim-x
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0140";
-		ADDR_O	<= X"0000_0034";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		-- set nx
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_007F";
-		ADDR_O	<= X"0000_0038";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		-- set ny
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_00FF";
-		ADDR_O	<= X"0000_003C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		-- set blit request
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= read_reg or X"0000_0100";
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		CYC_O	<= '0';
-		WE_O	<= '0';
+		for i in 0 to 3 loop
+		
+			-- BLIT test
+			-- Read status
+			CYC_O	<= '1';
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '1';
+			WE_O	<= '0';
+			ADDR_O	<= X"0000_0000";
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '0';
+			wait until rising_edge(CLK_O) and ACK_I = '1';
+			-- set src addr
+			CYC_O	<= '1';
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SDAT_O	<= X"4100_0000";
+			ADDR_O	<= X"0000_0020";
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '0';
+			-- set src dim-x
+			CYC_O	<= '1';
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SDAT_O	<= X"0000_0140";
+			ADDR_O	<= X"0000_002C";
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '0';
+			-- set dst addr
+			CYC_O	<= '1';
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SDAT_O	<= X"4200_0000";
+			ADDR_O	<= X"0000_0028";
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '0';
+			-- set dst dim-x
+			CYC_O	<= '1';
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SDAT_O	<= X"0000_0140";
+			ADDR_O	<= X"0000_0034";
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '0';
+			-- set nx
+			CYC_O	<= '1';
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SDAT_O	<= X"0000_12BF";
+			ADDR_O	<= X"0000_0038";
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '0';
+			-- set ny
+			CYC_O	<= '1';
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SDAT_O	<= X"0000_0000";
+			ADDR_O	<= X"0000_003C";
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '0';
+			-- set blit request
+			CYC_O	<= '1';
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '1';
+			WE_O	<= '1';
+			SDAT_O	<= read_reg or X"0000_0100";
+			ADDR_O	<= X"0000_0000";
+			wait until rising_edge(CLK_O) and SRDY_I = '1';
+			STB_O	<= '0';
+			CYC_O	<= '0';
+			WE_O	<= '0';
+			
+			wait for 600000*CLK_PERIOD;
+
+		
+		end loop;
 		
 		wait;