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- added blitter loop

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git-svn-id: http://moon:8086/svn/vhdl/trunk@677 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-22 22:37:20 +00:00
parent fc1a9e7b3d
commit cd8a49ad18
1 changed files with 85 additions and 78 deletions
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lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+85 -78
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@@ -83,9 +83,9 @@ BEGIN
inst_vga_frontend64 : entity work.vga_frontend64 inst_vga_frontend64 : entity work.vga_frontend64
GENERIC MAP GENERIC MAP
( (
fifo_depth => 256, fifo_depth => 2048,
fifo_almost_full_thresh => 240, fifo_almost_full_thresh => 2048-128,
fifo_almost_empty_thresh => 16, fifo_almost_empty_thresh => 512,
tsvga => tsvga tsvga => tsvga
) )
PORT MAP PORT MAP
@@ -351,81 +351,88 @@ STIMULUS: process
wait for 60000*CLK_PERIOD; wait for 60000*CLK_PERIOD;
-- BLIT test for i in 0 to 3 loop
-- Read status
CYC_O <= '1'; -- BLIT test
wait until rising_edge(CLK_O) and SRDY_I = '1'; -- Read status
STB_O <= '1'; CYC_O <= '1';
WE_O <= '0'; wait until rising_edge(CLK_O) and SRDY_I = '1';
ADDR_O <= X"0000_0000"; STB_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; WE_O <= '0';
STB_O <= '0'; ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and ACK_I = '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
-- set src addr STB_O <= '0';
CYC_O <= '1'; wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; -- set src addr
STB_O <= '1'; CYC_O <= '1';
WE_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
SDAT_O <= X"4100_0000"; STB_O <= '1';
ADDR_O <= X"0000_0020"; WE_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; SDAT_O <= X"4100_0000";
STB_O <= '0'; ADDR_O <= X"0000_0020";
-- set src dim-x wait until rising_edge(CLK_O) and SRDY_I = '1';
CYC_O <= '1'; STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1'; -- set src dim-x
STB_O <= '1'; CYC_O <= '1';
WE_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
SDAT_O <= X"0000_0140"; STB_O <= '1';
ADDR_O <= X"0000_002C"; WE_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; SDAT_O <= X"0000_0140";
STB_O <= '0'; ADDR_O <= X"0000_002C";
-- set dst addr wait until rising_edge(CLK_O) and SRDY_I = '1';
CYC_O <= '1'; STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1'; -- set dst addr
STB_O <= '1'; CYC_O <= '1';
WE_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
SDAT_O <= X"4200_0000"; STB_O <= '1';
ADDR_O <= X"0000_0028"; WE_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; SDAT_O <= X"4200_0000";
STB_O <= '0'; ADDR_O <= X"0000_0028";
-- set dst dim-x wait until rising_edge(CLK_O) and SRDY_I = '1';
CYC_O <= '1'; STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1'; -- set dst dim-x
STB_O <= '1'; CYC_O <= '1';
WE_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
SDAT_O <= X"0000_0140"; STB_O <= '1';
ADDR_O <= X"0000_0034"; WE_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; SDAT_O <= X"0000_0140";
STB_O <= '0'; ADDR_O <= X"0000_0034";
-- set nx wait until rising_edge(CLK_O) and SRDY_I = '1';
CYC_O <= '1'; STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1'; -- set nx
STB_O <= '1'; CYC_O <= '1';
WE_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
SDAT_O <= X"0000_007F"; STB_O <= '1';
ADDR_O <= X"0000_0038"; WE_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; SDAT_O <= X"0000_12BF";
STB_O <= '0'; ADDR_O <= X"0000_0038";
-- set ny wait until rising_edge(CLK_O) and SRDY_I = '1';
CYC_O <= '1'; STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1'; -- set ny
STB_O <= '1'; CYC_O <= '1';
WE_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
SDAT_O <= X"0000_00FF"; STB_O <= '1';
ADDR_O <= X"0000_003C"; WE_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; SDAT_O <= X"0000_0000";
STB_O <= '0'; ADDR_O <= X"0000_003C";
-- set blit request wait until rising_edge(CLK_O) and SRDY_I = '1';
CYC_O <= '1'; STB_O <= '0';
wait until rising_edge(CLK_O) and SRDY_I = '1'; -- set blit request
STB_O <= '1'; CYC_O <= '1';
WE_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1';
SDAT_O <= read_reg or X"0000_0100"; STB_O <= '1';
ADDR_O <= X"0000_0000"; WE_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1'; SDAT_O <= read_reg or X"0000_0100";
STB_O <= '0'; ADDR_O <= X"0000_0000";
CYC_O <= '0'; wait until rising_edge(CLK_O) and SRDY_I = '1';
WE_O <= '0'; STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait for 600000*CLK_PERIOD;
end loop;
wait; wait;