[DE0-Nano]

- reduce uart buffer to introduce more delay (work around for bus timeout) git-svn-id: http://moon:8086/svn/vhdl/trunk@1361 cc03376c-175c-47c8-b038-4cd826a8556b
2016-12-21 21:14:07 +00:00
parent ab321735e8
commit cb8367c67a
1 changed files with 1 additions and 1 deletions
@@ -332,7 +332,7 @@ inst_uart : entity work.uart_wb
 	(
 		f_sysclk			=> F_SYSCLK,
 		baudrate_default	=> 115200.0,
-		fifo_depth_bits		=> 4
+		fifo_depth_bits		=> 1
 	)
 	PORT MAP
 	(