jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[DE0-Nano]

Browse Source 
- increased CPU reset duration

git-svn-id: http://moon:8086/svn/vhdl/trunk@1374 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-01-20 18:41:25 +00:00
parent 8043f0b373
commit cb25248c3f
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_de0_nano/quartus/mips/mips_sys.vhd
+1 -1
View File
@@ -134,7 +134,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR
signal sys_rst : STD_LOGIC := '1'; -- pre-init for POR signal sys_rst : STD_LOGIC := '1'; -- pre-init for POR
signal cpu_rst_count : unsigned(23 downto 0) := (others => '1'); -- pre-init for POR signal cpu_rst_count : unsigned(24 downto 0) := (others => '1'); -- pre-init for POR
signal sys_rst_count : unsigned(7 downto 0) := (others => '1'); -- pre-init for POR signal sys_rst_count : unsigned(7 downto 0) := (others => '1'); -- pre-init for POR
BEGIN BEGIN