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- refacored

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1609 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-31 08:15:41 +00:00
parent 1970a91580
commit c922fbe961
2 changed files with 14 additions and 14 deletions
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lib/FIFO/src/reg_stage.vhd
+8 -8
View File
@@ -39,22 +39,22 @@ entity reg_stage is
we : in STD_LOGIC; we : in STD_LOGIC;
re : in STD_LOGIC; re : in STD_LOGIC;
full : out STD_LOGIC; full : out STD_LOGIC;
dvld_r : out STD_LOGIC; vld_dout : out STD_LOGIC;
data_w : in unsigned (data_width-1 downto 0); din : in unsigned (data_width-1 downto 0);
data_r : out unsigned (data_width-1 downto 0) dout : out unsigned (data_width-1 downto 0)
); );
end reg_stage; end reg_stage;
architecture Behavioral of reg_stage is architecture Behavioral of reg_stage is
signal dvld : std_logic; signal dvld : std_logic;
signal d : std_logic; signal fct : std_logic;
begin begin
full <= dvld and not re; full <= dvld and not re;
dvld_r <= dvld; vld_dout <= dvld;
d <= we or (dvld and not re); fct <= we or (dvld and not re);
proc_dvld_reg: proc_dvld_reg:
process(clk) process(clk)
@@ -63,7 +63,7 @@ proc_dvld_reg:
if rst = '1' then if rst = '1' then
dvld <= '0'; dvld <= '0';
else else
dvld <= d; dvld <= fct;
end if; end if;
end if; end if;
end process; end process;
@@ -73,7 +73,7 @@ proc_data_reg:
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if we = '1' then if we = '1' then
data_r <= data_w; dout <= din;
end if; end if;
end if; end if;
end process; end process;
lib/FIFO/src/tb_reg_stage.vhd
+5 -5
View File
@@ -51,7 +51,7 @@ ARCHITECTURE behavior OF tb_reg_stage IS
signal dout : unsigned (7 downto 0); signal dout : unsigned (7 downto 0);
signal full : STD_LOGIC; signal full : STD_LOGIC;
signal dvld_r : STD_LOGIC; signal vld_dout : STD_LOGIC;
signal write_en : STD_LOGIC := '0'; signal write_en : STD_LOGIC := '0';
signal read_en : STD_LOGIC := '0'; signal read_en : STD_LOGIC := '0';
@@ -72,10 +72,10 @@ BEGIN
clk => clk, clk => clk,
we => we, we => we,
re => re, re => re,
data_w => din, din => din,
data_r => dout, dout => dout,
full => full, full => full,
dvld_r => dvld_r vld_dout => vld_dout
); );
tb_clk : PROCESS tb_clk : PROCESS
@@ -179,7 +179,7 @@ BEGIN
END PROCESS; END PROCESS;
re <= read_en and dvld_r; re <= read_en and vld_dout;
tb_r : PROCESS(rst, clk) tb_r : PROCESS(rst, clk)
BEGIN BEGIN