From c922fbe96141247355214868a0567b59af1da89d Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Wed, 31 Mar 2021 08:15:41 +0000
Subject: [PATCH] - refacored

git-svn-id: http://moon:8086/svn/vhdl/trunk@1609 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/FIFO/src/reg_stage.vhd    | 18 +++++++++---------
 lib/FIFO/src/tb_reg_stage.vhd | 10 +++++-----
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/lib/FIFO/src/reg_stage.vhd b/lib/FIFO/src/reg_stage.vhd
index b2b5574..c011fb6 100644
--- a/lib/FIFO/src/reg_stage.vhd
+++ b/lib/FIFO/src/reg_stage.vhd
@@ -39,22 +39,22 @@ entity reg_stage is
 		we			: in  STD_LOGIC;
 		re			: in  STD_LOGIC;
 		full		: out STD_LOGIC;
-		dvld_r		: out STD_LOGIC;
-		data_w		: in  unsigned (data_width-1 downto 0);
-		data_r		: out unsigned (data_width-1 downto 0)
+		vld_dout	: out STD_LOGIC;
+		din			: in  unsigned (data_width-1 downto 0);
+		dout		: out unsigned (data_width-1 downto 0)
 	);
 end reg_stage;
 
 architecture Behavioral of reg_stage is
 	
 	signal dvld		: std_logic;
-	signal d		: std_logic;
+	signal fct		: std_logic;
 		
 begin
 
-	full	<= dvld and not re;
-	dvld_r	<= dvld;
-	d		<= we or (dvld and not re);
+	full		<= dvld and not re;
+	vld_dout	<= dvld;
+	fct			<= we or (dvld and not re);
 	
 proc_dvld_reg:
 	process(clk)
@@ -63,7 +63,7 @@ proc_dvld_reg:
 			if rst = '1' then
 				dvld <= '0';
 			else
-				dvld <= d;
+				dvld <= fct;
 			end if;
 		end if;
 	end process;
@@ -73,7 +73,7 @@ proc_data_reg:
 	begin
 		if rising_edge(clk) then
 			if we = '1' then
-				data_r <= data_w;
+				dout <= din;
 			end if;
 		end if;
 	end process;
diff --git a/lib/FIFO/src/tb_reg_stage.vhd b/lib/FIFO/src/tb_reg_stage.vhd
index 04fba84..a947b26 100644
--- a/lib/FIFO/src/tb_reg_stage.vhd
+++ b/lib/FIFO/src/tb_reg_stage.vhd
@@ -51,7 +51,7 @@ ARCHITECTURE behavior OF tb_reg_stage IS
 
 	signal dout					: unsigned (7 downto 0);
 	signal full					: STD_LOGIC;
-	signal dvld_r				: STD_LOGIC;
+	signal vld_dout				: STD_LOGIC;
 
 	signal write_en				: STD_LOGIC := '0';
 	signal read_en				: STD_LOGIC := '0';
@@ -72,10 +72,10 @@ BEGIN
 		clk			=>	clk,
 		we			=>	we,
 		re			=>	re,
-		data_w		=>	din,
-		data_r		=>	dout,
+		din			=>	din,
+		dout		=>	dout,
 		full		=>	full,
-		dvld_r		=>	dvld_r
+		vld_dout	=>	vld_dout
 	);
 
  	tb_clk : PROCESS
@@ -179,7 +179,7 @@ BEGIN
 
 	END PROCESS;
 	
-	re	<= read_en and dvld_r;
+	re	<= read_en and vld_dout;
 
  	tb_r : PROCESS(rst, clk)
 	BEGIN