- changed read, write order (should have no effect)
git-svn-id: http://moon:8086/svn/vhdl/trunk@243 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -21,7 +21,7 @@
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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library IEEE;
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library IEEE;
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@@ -63,10 +63,10 @@ process (clk_a)
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begin
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begin
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if clk_a'event and clk_a = '1' then
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if clk_a'event and clk_a = '1' then
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if en_a = '1' then
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if en_a = '1' then
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dout_a <= RAM(to_integer(addr_a));
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if we_a = '1' then
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if we_a = '1' then
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RAM(to_integer(addr_a)) := din_a;
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RAM(to_integer(addr_a)) := din_a;
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end if;
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end if;
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dout_a <= RAM(to_integer(addr_a));
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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@@ -75,10 +75,10 @@ process (clk_b)
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begin
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begin
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if clk_b'event and clk_b = '1' then
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if clk_b'event and clk_b = '1' then
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if en_b = '1' then
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if en_b = '1' then
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dout_b <= RAM(to_integer(addr_b));
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if we_b = '1' then
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if we_b = '1' then
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RAM(to_integer(addr_b)) := din_b;
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RAM(to_integer(addr_b)) := din_b;
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end if;
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end if;
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dout_b <= RAM(to_integer(addr_b));
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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