[mips_de0_nano]
- initial import git-svn-id: http://moon:8086/svn/vhdl/trunk@1340 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,420 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: Testbench for JCPU
|
||||
-- also writes 'opc.lst' for JASM-assembler
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.sdram_types.all;
|
||||
use work.sdram_config.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
use altera_mf.altera_mf_components.sld_virtual_jtag;
|
||||
|
||||
ENTITY mips_sys IS
|
||||
GENERIC
|
||||
(
|
||||
ICACHE_SIZE : natural := 4096; -- words
|
||||
DCACHE_SIZE : natural := 4096; -- words
|
||||
F_SYSCLK : real := 50.0
|
||||
);
|
||||
PORT
|
||||
(
|
||||
sys_nmi_n : in std_logic;
|
||||
sys_rst_n : in std_logic;
|
||||
sys_clk : in std_logic;
|
||||
|
||||
-- SDRAM signals
|
||||
sys_sdram_clk : out STD_LOGIC;
|
||||
sys_sdram_cke : out STD_LOGIC;
|
||||
sys_sdram_cs_n : out STD_LOGIC;
|
||||
sys_sdram_cas_n : out STD_LOGIC;
|
||||
sys_sdram_ras_n : out STD_LOGIC;
|
||||
sys_sdram_we_n : out STD_LOGIC;
|
||||
sys_sdram_addr : out sdr_addr_t;
|
||||
sys_sdram_ba : out sdr_ba_t;
|
||||
sys_sdram_dqm : out unsigned(PART_DM_WIDTH-1 downto 0);
|
||||
sys_sdram_data : inout unsigned(PART_DATA_WIDTH-1 downto 0);
|
||||
|
||||
spi_ss_n : out std_logic;
|
||||
spi_clk : out std_logic;
|
||||
spi_miso : in std_logic;
|
||||
spi_mosi : out std_logic;
|
||||
|
||||
sys_leds : out unsigned(7 downto 0)
|
||||
);
|
||||
END mips_sys;
|
||||
|
||||
ARCHITECTURE behavior OF mips_sys IS
|
||||
|
||||
signal cpu_debug : unsigned(1 downto 0);
|
||||
signal INT : unsigned (5 downto 0) := (others => '0');
|
||||
|
||||
-- J-BUS Master
|
||||
signal ACK_I : STD_LOGIC;
|
||||
signal SRDY_I : STD_LOGIC;
|
||||
signal ADDR_O : unsigned(31 downto 0);
|
||||
signal DAT_I : unsigned(31 downto 0);
|
||||
signal DAT_O : unsigned(31 downto 0);
|
||||
signal WE_O : STD_LOGIC;
|
||||
signal SEL_O : unsigned(3 downto 0);
|
||||
signal CYC_O : STD_LOGIC;
|
||||
signal STB_O : STD_LOGIC;
|
||||
signal MRDY_O : STD_LOGIC;
|
||||
|
||||
-- J-BUS Slaves
|
||||
signal CYC_I_rom : std_logic;
|
||||
signal ACK_O_rom : std_logic;
|
||||
signal SRDY_O_rom : std_logic;
|
||||
signal DAT_O_rom : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_ram : std_logic;
|
||||
signal ACK_O_ram : std_logic;
|
||||
signal SRDY_O_ram : std_logic;
|
||||
signal DAT_O_ram : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_gpio : std_logic;
|
||||
signal ACK_O_gpio : std_logic;
|
||||
signal SRDY_O_gpio : std_logic;
|
||||
signal DAT_O_gpio : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_uart : std_logic;
|
||||
signal ACK_O_uart : std_logic;
|
||||
signal SRDY_O_uart : std_logic;
|
||||
signal DAT_O_uart : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_flash : std_logic;
|
||||
signal ACK_O_flash : std_logic;
|
||||
signal SRDY_O_flash : std_logic;
|
||||
signal DAT_O_flash : unsigned(31 downto 0);
|
||||
|
||||
signal spi_ss : std_LOGIC;
|
||||
signal cpu_tx_data : unsigned(7 downto 0);
|
||||
signal cpu_tx_data_vld : std_logic;
|
||||
|
||||
signal int_timer : std_logic;
|
||||
signal int_uart : std_logic;
|
||||
signal int_flash : std_logic;
|
||||
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_ram, mem_rom, mem_gpio, mem_uart);
|
||||
signal mem_area : mem_area_t;
|
||||
|
||||
signal gpo0 : unsigned(31 downto 0);
|
||||
signal gpi0 : unsigned(31 downto 0) := (others => '0');
|
||||
|
||||
signal sys_rst : STD_LOGIC;
|
||||
signal sys_nmi : STD_LOGIC;
|
||||
|
||||
signal reset_counter : unsigned(7 downto 0) := (others => '1');
|
||||
signal reset : STD_LOGIC := '1';
|
||||
|
||||
subtype addr_t is unsigned (2 downto 0);
|
||||
subtype reg_t is unsigned (7 downto 0);
|
||||
type reg_map_t is array (0 to 7) of reg_t;
|
||||
|
||||
signal regs : reg_map_t;
|
||||
signal reg_addr : addr_t;
|
||||
signal reg_din : reg_t;
|
||||
signal reg_dout : reg_t;
|
||||
signal reg_re : STD_LOGIC;
|
||||
signal reg_we : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
sys_rst <= reset;
|
||||
sys_nmi <= not sys_nmi_n;
|
||||
sys_leds <= cpu_debug & gpo0(5 downto 0);
|
||||
spi_ss_n <= not spi_ss;
|
||||
|
||||
reg_dout <= regs(to_integer(reg_addr));
|
||||
|
||||
process(sys_clk)
|
||||
begin
|
||||
if rising_edge(sys_clk) then
|
||||
if reg_we = '1' then
|
||||
regs(to_integer(reg_addr)) <= reg_din;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
inst_jtag_reg: entity work.jtag_reg
|
||||
GENERIC MAP
|
||||
(
|
||||
INSTANCE_INDEX => 1,
|
||||
DATA_WIDTH => reg_t'length, -- bits
|
||||
ADDR_WIDTH => addr_t'length -- bits
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
rst => sys_rst,
|
||||
clk => sys_clk,
|
||||
addr_o => reg_addr,
|
||||
reg_i => reg_dout,
|
||||
reg_o => reg_din,
|
||||
we_o => reg_we,
|
||||
re_o => reg_re
|
||||
);
|
||||
|
||||
power_up_reset:
|
||||
process(sys_clk)
|
||||
begin
|
||||
if rising_edge(sys_clk) then
|
||||
if sys_rst_n = '0' then
|
||||
reset <= '1';
|
||||
reset_counter <= (others => '1');
|
||||
elsif (reset_counter /= 0) then
|
||||
reset_counter <= reset_counter - 1;
|
||||
else
|
||||
reset <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
-- Memory mux
|
||||
------------------------------------------------------------------
|
||||
mem_mux:
|
||||
process(ADDR_O)
|
||||
begin
|
||||
mem_area <= mem_dead;
|
||||
if ADDR_O(31 downto 28) = X"0" then
|
||||
mem_area <= mem_flash;
|
||||
elsif ADDR_O(31 downto 28) = X"A" then
|
||||
if ADDR_O(27 downto 26) = "00" then
|
||||
if ADDR_O(18 downto 16) = "000" then
|
||||
mem_area <= mem_gpio;
|
||||
elsif ADDR_O(18 downto 16) = "001" then
|
||||
mem_area <= mem_uart;
|
||||
end if;
|
||||
elsif ADDR_O(27 downto 26) = "01" then
|
||||
mem_area <= mem_flash;
|
||||
end if;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
|
||||
mem_area <= mem_rom;
|
||||
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
|
||||
mem_area <= mem_ram;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
signal_mux:
|
||||
process(mem_area, CYC_O)
|
||||
begin
|
||||
|
||||
CYC_I_gpio <= '0';
|
||||
CYC_I_uart <= '0';
|
||||
CYC_I_flash <= '0';
|
||||
CYC_I_rom <= '0';
|
||||
CYC_I_ram <= '0';
|
||||
|
||||
case mem_area is
|
||||
|
||||
when mem_gpio =>
|
||||
CYC_I_gpio <= CYC_O;
|
||||
|
||||
when mem_uart =>
|
||||
CYC_I_uart <= CYC_O;
|
||||
|
||||
when mem_flash =>
|
||||
CYC_I_flash <= CYC_O;
|
||||
|
||||
when mem_rom =>
|
||||
CYC_I_rom <= CYC_O;
|
||||
|
||||
when mem_ram =>
|
||||
CYC_I_ram <= CYC_O;
|
||||
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
SRDY_I <= SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_flash or SRDY_O_gpio;
|
||||
ACK_I <= ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_flash or ACK_O_gpio;
|
||||
DAT_I <= DAT_O_ram when CYC_I_ram = '1' else
|
||||
DAT_O_rom when CYC_I_rom = '1' else
|
||||
DAT_O_uart when CYC_I_uart = '1' else
|
||||
DAT_O_flash when CYC_I_flash = '1' else
|
||||
DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_mips_top: entity work.mips_top
|
||||
GENERIC MAP
|
||||
(
|
||||
icache_size => ICACHE_SIZE, -- words
|
||||
dcache_size => DCACHE_SIZE -- words
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
debug => cpu_debug,
|
||||
nmi => sys_nmi,
|
||||
eb => '1',
|
||||
cpu_clk => sys_clk,
|
||||
RST_I => sys_rst,
|
||||
CLK_I => sys_clk,
|
||||
ACK_I => ACK_I,
|
||||
SRDY_I => SRDY_I,
|
||||
ADDR_O => ADDR_O,
|
||||
DAT_I => DAT_I,
|
||||
DAT_O => DAT_O,
|
||||
WE_O => WE_O,
|
||||
SEL_O => SEL_O,
|
||||
CYC_O => CYC_O,
|
||||
STB_O => STB_O,
|
||||
MRDY_O => MRDY_O,
|
||||
INT => INT
|
||||
);
|
||||
|
||||
INT <= "000" & int_flash & int_uart & int_timer;
|
||||
|
||||
inst_rom : entity work.rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => sys_clk,
|
||||
RST_I => sys_rst,
|
||||
CYC_I => CYC_I_rom,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_rom,
|
||||
MRDY_I => MRDY_O,
|
||||
SRDY_O => SRDY_O_rom,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_O => DAT_O_rom
|
||||
);
|
||||
|
||||
inst_gpio : entity work.gpio_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
f_sysclk => F_SYSCLK
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => sys_clk,
|
||||
RST_I => sys_rst,
|
||||
CYC_I => CYC_I_gpio,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_gpio,
|
||||
SRDY_O => SRDY_O_gpio,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_gpio,
|
||||
INT_TIM_O => int_timer,
|
||||
sys_gpi_0 => gpi0,
|
||||
sys_gpo_0 => gpo0
|
||||
);
|
||||
|
||||
inst_uart : entity work.uart_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => sys_clk,
|
||||
RST_I => sys_rst,
|
||||
CYC_I => CYC_I_uart,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_uart,
|
||||
SRDY_O => SRDY_O_uart,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_uart,
|
||||
INT_O => int_uart,
|
||||
ser_rx => '1',
|
||||
ser_tx => open
|
||||
);
|
||||
|
||||
inst_spi_flash : entity work.spi_flash_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
FLASH_ADDR_BITS => 24,
|
||||
CACHE_ADDR_BITS => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => sys_clk,
|
||||
RST_I => sys_rst,
|
||||
CYC_I => CYC_I_flash,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_flash,
|
||||
SRDY_O => SRDY_O_flash,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_flash,
|
||||
INT_O => int_flash,
|
||||
spi_hold => '0',
|
||||
spi_ss => spi_ss,
|
||||
spi_clk => spi_clk,
|
||||
spi_miso => spi_miso,
|
||||
spi_mosi => spi_mosi
|
||||
);
|
||||
|
||||
-- DDR SDRAM Controller Core
|
||||
inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32
|
||||
GENERIC MAP
|
||||
(
|
||||
F_SYSCLK => 50.000,
|
||||
F_SDRCLK_IN => 50.000,
|
||||
F_SDRCLK => 100.000,
|
||||
FIFO_DEPTH => 4,
|
||||
TPD_BOARD_SIM => 3100 ps
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
RST_I => sys_rst,
|
||||
CLK_I => sys_clk,
|
||||
SDRAM_CLK_I => sys_clk,
|
||||
SDRAM_CLK_FB_I => sys_clk,
|
||||
|
||||
CYC_I => CYC_I_ram,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_ram,
|
||||
SRDY_O => SRDY_O_ram,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => DAT_O,
|
||||
DAT_O => DAT_O_ram,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk => sys_sdram_clk,
|
||||
sd_cke => sys_sdram_cke,
|
||||
sd_cs_n => sys_sdram_cs_n,
|
||||
sd_cas_n => sys_sdram_cas_n,
|
||||
sd_ras_n => sys_sdram_ras_n,
|
||||
sd_we_n => sys_sdram_we_n,
|
||||
sd_addr => sys_sdram_addr,
|
||||
sd_ba => sys_sdram_ba,
|
||||
sd_dqm => sys_sdram_dqm,
|
||||
sd_data => sys_sdram_data
|
||||
|
||||
);
|
||||
|
||||
END;
|
||||
Reference in New Issue
Block a user