diff --git a/projects/mips_de0_nano/quartus/mips/JMips.qpf b/projects/mips_de0_nano/quartus/mips/JMips.qpf
new file mode 100644
index 0000000..75c430a
--- /dev/null
+++ b/projects/mips_de0_nano/quartus/mips/JMips.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+# Date created = 08:21:44 May 14, 2015
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.0"
+DATE = "08:21:44 May 14, 2015"
+
+# Revisions
+
+PROJECT_REVISION = "JMips"
diff --git a/projects/mips_de0_nano/quartus/mips/JMips.sdc b/projects/mips_de0_nano/quartus/mips/JMips.sdc
new file mode 100644
index 0000000..17f30e1
--- /dev/null
+++ b/projects/mips_de0_nano/quartus/mips/JMips.sdc
@@ -0,0 +1,111 @@
+## Generated SDC file "JMips.out.sdc"
+
+## Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+## Your use of Altera Corporation's design tools, logic functions
+## and other software and tools, and its AMPP partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Altera Program License
+## Subscription Agreement, the Altera Quartus II License Agreement,
+## the Altera MegaCore Function License Agreement, or other
+## applicable license agreement, including, without limitation,
+## that your use is for the sole purpose of programming logic
+## devices manufactured by Altera and sold by Altera or its
+## authorized distributors. Please refer to the applicable
+## agreement for further details.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 15.0.0 Build 145 04/22/2015 SJ Web Edition"
+
+## DATE "Sat May 30 18:14:14 2015"
+
+##
+## DEVICE "EP4CE22F17C6"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
+create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { sys_clk }]
+create_clock -name {SDRAM_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_sdram_clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/projects/mips_de0_nano/quartus/mips/JTag-Test.lnk b/projects/mips_de0_nano/quartus/mips/JTag-Test.lnk
new file mode 100644
index 0000000..d04d259
Binary files /dev/null and b/projects/mips_de0_nano/quartus/mips/JTag-Test.lnk differ
diff --git a/projects/mips_de0_nano/quartus/mips/VJ-UART.lnk b/projects/mips_de0_nano/quartus/mips/VJ-UART.lnk
new file mode 100644
index 0000000..abba77f
Binary files /dev/null and b/projects/mips_de0_nano/quartus/mips/VJ-UART.lnk differ
diff --git a/projects/mips_de0_nano/quartus/mips/jtag_test.tcl b/projects/mips_de0_nano/quartus/mips/jtag_test.tcl
new file mode 100644
index 0000000..924d4a2
--- /dev/null
+++ b/projects/mips_de0_nano/quartus/mips/jtag_test.tcl
@@ -0,0 +1,70 @@
+#This portion of the script is derived from some of the examples from Altera
+
+global usbblaster_name
+global test_device
+
+set jtag_instance 1
+
+# List all available programming hardwares, and select the USBBlaster.
+# (Note: this example assumes only one USBBlaster connected.)
+# Programming Hardwares:
+foreach hardware_name [get_hardware_names] {
+ puts $hardware_name
+ if { [string match "USB-Blaster*" $hardware_name] } {
+ set usbblaster_name $hardware_name
+ }
+}
+
+puts "\nSelect JTAG chain connected to $usbblaster_name.\n";
+
+# List all devices on the chain, and select the first device on the chain.
+#Devices on the JTAG chain:
+
+foreach device_name [get_device_names -hardware_name $usbblaster_name] {
+# puts $device_name
+ if { [string match "@1*" $device_name] } {
+ set test_device $device_name
+ }
+}
+puts "\nSelect device: $test_device.\n";
+
+# Open device
+proc openport {} {
+ global usbblaster_name
+ global test_device
+ open_device -hardware_name $usbblaster_name -device_name $test_device
+}
+
+# Close device. Just used if communication error occurs
+proc closeport { } {
+ catch {device_unlock}
+ catch {close_device}
+}
+
+proc testit {regNum} {
+ global jtag_instance
+ openport
+ device_lock -timeout 10000
+ puts "Read Virtual register #$regNum (sample #[device_virtual_ir_shift -no_captured_ir_value -instance_index $jtag_instance -ir_value $regNum]): [device_virtual_dr_shift -instance_index $jtag_instance -length 8 -value_in_hex]"
+ closeport
+}
+
+proc readReg {regNum} {
+ global jtag_instance
+ openport
+ device_lock -timeout 10000
+ device_virtual_ir_shift -no_captured_ir_value -instance_index $jtag_instance -ir_value $regNum
+ puts "Read Virtual register #$regNum [device_virtual_dr_shift -instance_index $jtag_instance -length 8 -value_in_hex]"
+ closeport
+}
+
+proc writeReg {regNum regValue} {
+ global jtag_instance
+ openport
+ device_lock -timeout 10000
+ puts "Write Virtual register #$regNum = $regValue"
+ set effReg [expr $regNum + 0x08]
+ device_virtual_ir_shift -no_captured_ir_value -instance_index $jtag_instance -ir_value $effReg
+ device_virtual_dr_shift -instance_index $jtag_instance -no_captured_dr_value -dr_value $regValue -length 8 -value_in_hex
+ closeport
+}
diff --git a/projects/mips_de0_nano/quartus/mips/mips_sys.vhd b/projects/mips_de0_nano/quartus/mips/mips_sys.vhd
new file mode 100644
index 0000000..7ad3b9b
--- /dev/null
+++ b/projects/mips_de0_nano/quartus/mips/mips_sys.vhd
@@ -0,0 +1,420 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+-- also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.sdram_types.all;
+use work.sdram_config.all;
+
+LIBRARY altera_mf;
+use altera_mf.altera_mf_components.sld_virtual_jtag;
+
+ENTITY mips_sys IS
+ GENERIC
+ (
+ ICACHE_SIZE : natural := 4096; -- words
+ DCACHE_SIZE : natural := 4096; -- words
+ F_SYSCLK : real := 50.0
+ );
+ PORT
+ (
+ sys_nmi_n : in std_logic;
+ sys_rst_n : in std_logic;
+ sys_clk : in std_logic;
+
+ -- SDRAM signals
+ sys_sdram_clk : out STD_LOGIC;
+ sys_sdram_cke : out STD_LOGIC;
+ sys_sdram_cs_n : out STD_LOGIC;
+ sys_sdram_cas_n : out STD_LOGIC;
+ sys_sdram_ras_n : out STD_LOGIC;
+ sys_sdram_we_n : out STD_LOGIC;
+ sys_sdram_addr : out sdr_addr_t;
+ sys_sdram_ba : out sdr_ba_t;
+ sys_sdram_dqm : out unsigned(PART_DM_WIDTH-1 downto 0);
+ sys_sdram_data : inout unsigned(PART_DATA_WIDTH-1 downto 0);
+
+ spi_ss_n : out std_logic;
+ spi_clk : out std_logic;
+ spi_miso : in std_logic;
+ spi_mosi : out std_logic;
+
+ sys_leds : out unsigned(7 downto 0)
+ );
+END mips_sys;
+
+ARCHITECTURE behavior OF mips_sys IS
+
+ signal cpu_debug : unsigned(1 downto 0);
+ signal INT : unsigned (5 downto 0) := (others => '0');
+
+ -- J-BUS Master
+ signal ACK_I : STD_LOGIC;
+ signal SRDY_I : STD_LOGIC;
+ signal ADDR_O : unsigned(31 downto 0);
+ signal DAT_I : unsigned(31 downto 0);
+ signal DAT_O : unsigned(31 downto 0);
+ signal WE_O : STD_LOGIC;
+ signal SEL_O : unsigned(3 downto 0);
+ signal CYC_O : STD_LOGIC;
+ signal STB_O : STD_LOGIC;
+ signal MRDY_O : STD_LOGIC;
+
+ -- J-BUS Slaves
+ signal CYC_I_rom : std_logic;
+ signal ACK_O_rom : std_logic;
+ signal SRDY_O_rom : std_logic;
+ signal DAT_O_rom : unsigned(31 downto 0);
+
+ signal CYC_I_ram : std_logic;
+ signal ACK_O_ram : std_logic;
+ signal SRDY_O_ram : std_logic;
+ signal DAT_O_ram : unsigned(31 downto 0);
+
+ signal CYC_I_gpio : std_logic;
+ signal ACK_O_gpio : std_logic;
+ signal SRDY_O_gpio : std_logic;
+ signal DAT_O_gpio : unsigned(31 downto 0);
+
+ signal CYC_I_uart : std_logic;
+ signal ACK_O_uart : std_logic;
+ signal SRDY_O_uart : std_logic;
+ signal DAT_O_uart : unsigned(31 downto 0);
+
+ signal CYC_I_flash : std_logic;
+ signal ACK_O_flash : std_logic;
+ signal SRDY_O_flash : std_logic;
+ signal DAT_O_flash : unsigned(31 downto 0);
+
+ signal spi_ss : std_LOGIC;
+ signal cpu_tx_data : unsigned(7 downto 0);
+ signal cpu_tx_data_vld : std_logic;
+
+ signal int_timer : std_logic;
+ signal int_uart : std_logic;
+ signal int_flash : std_logic;
+
+ type mem_area_t is (mem_dead, mem_flash, mem_ram, mem_rom, mem_gpio, mem_uart);
+ signal mem_area : mem_area_t;
+
+ signal gpo0 : unsigned(31 downto 0);
+ signal gpi0 : unsigned(31 downto 0) := (others => '0');
+
+ signal sys_rst : STD_LOGIC;
+ signal sys_nmi : STD_LOGIC;
+
+ signal reset_counter : unsigned(7 downto 0) := (others => '1');
+ signal reset : STD_LOGIC := '1';
+
+ subtype addr_t is unsigned (2 downto 0);
+ subtype reg_t is unsigned (7 downto 0);
+ type reg_map_t is array (0 to 7) of reg_t;
+
+ signal regs : reg_map_t;
+ signal reg_addr : addr_t;
+ signal reg_din : reg_t;
+ signal reg_dout : reg_t;
+ signal reg_re : STD_LOGIC;
+ signal reg_we : STD_LOGIC;
+
+BEGIN
+ sys_rst <= reset;
+ sys_nmi <= not sys_nmi_n;
+ sys_leds <= cpu_debug & gpo0(5 downto 0);
+ spi_ss_n <= not spi_ss;
+
+ reg_dout <= regs(to_integer(reg_addr));
+
+ process(sys_clk)
+ begin
+ if rising_edge(sys_clk) then
+ if reg_we = '1' then
+ regs(to_integer(reg_addr)) <= reg_din;
+ end if;
+ end if;
+ end process;
+
+inst_jtag_reg: entity work.jtag_reg
+ GENERIC MAP
+ (
+ INSTANCE_INDEX => 1,
+ DATA_WIDTH => reg_t'length, -- bits
+ ADDR_WIDTH => addr_t'length -- bits
+ )
+ PORT MAP
+ (
+ rst => sys_rst,
+ clk => sys_clk,
+ addr_o => reg_addr,
+ reg_i => reg_dout,
+ reg_o => reg_din,
+ we_o => reg_we,
+ re_o => reg_re
+ );
+
+power_up_reset:
+ process(sys_clk)
+ begin
+ if rising_edge(sys_clk) then
+ if sys_rst_n = '0' then
+ reset <= '1';
+ reset_counter <= (others => '1');
+ elsif (reset_counter /= 0) then
+ reset_counter <= reset_counter - 1;
+ else
+ reset <= '0';
+ end if;
+ end if;
+ end process;
+
+------------------------------------------------------------------
+-- Memory mux
+------------------------------------------------------------------
+mem_mux:
+ process(ADDR_O)
+ begin
+ mem_area <= mem_dead;
+ if ADDR_O(31 downto 28) = X"0" then
+ mem_area <= mem_flash;
+ elsif ADDR_O(31 downto 28) = X"A" then
+ if ADDR_O(27 downto 26) = "00" then
+ if ADDR_O(18 downto 16) = "000" then
+ mem_area <= mem_gpio;
+ elsif ADDR_O(18 downto 16) = "001" then
+ mem_area <= mem_uart;
+ end if;
+ elsif ADDR_O(27 downto 26) = "01" then
+ mem_area <= mem_flash;
+ end if;
+ elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
+ mem_area <= mem_rom;
+ elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
+ mem_area <= mem_ram;
+ end if;
+ end process;
+
+signal_mux:
+ process(mem_area, CYC_O)
+ begin
+
+ CYC_I_gpio <= '0';
+ CYC_I_uart <= '0';
+ CYC_I_flash <= '0';
+ CYC_I_rom <= '0';
+ CYC_I_ram <= '0';
+
+ case mem_area is
+
+ when mem_gpio =>
+ CYC_I_gpio <= CYC_O;
+
+ when mem_uart =>
+ CYC_I_uart <= CYC_O;
+
+ when mem_flash =>
+ CYC_I_flash <= CYC_O;
+
+ when mem_rom =>
+ CYC_I_rom <= CYC_O;
+
+ when mem_ram =>
+ CYC_I_ram <= CYC_O;
+
+ when others => null;
+
+ end case;
+
+ end process;
+
+ SRDY_I <= SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_flash or SRDY_O_gpio;
+ ACK_I <= ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_flash or ACK_O_gpio;
+ DAT_I <= DAT_O_ram when CYC_I_ram = '1' else
+ DAT_O_rom when CYC_I_rom = '1' else
+ DAT_O_uart when CYC_I_uart = '1' else
+ DAT_O_flash when CYC_I_flash = '1' else
+ DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
+
+------------------------------------------------------------------
+inst_mips_top: entity work.mips_top
+ GENERIC MAP
+ (
+ icache_size => ICACHE_SIZE, -- words
+ dcache_size => DCACHE_SIZE -- words
+ )
+ PORT MAP
+ (
+ debug => cpu_debug,
+ nmi => sys_nmi,
+ eb => '1',
+ cpu_clk => sys_clk,
+ RST_I => sys_rst,
+ CLK_I => sys_clk,
+ ACK_I => ACK_I,
+ SRDY_I => SRDY_I,
+ ADDR_O => ADDR_O,
+ DAT_I => DAT_I,
+ DAT_O => DAT_O,
+ WE_O => WE_O,
+ SEL_O => SEL_O,
+ CYC_O => CYC_O,
+ STB_O => STB_O,
+ MRDY_O => MRDY_O,
+ INT => INT
+ );
+
+ INT <= "000" & int_flash & int_uart & int_timer;
+
+inst_rom : entity work.rom_wb
+ PORT MAP
+ (
+ CLK_I => sys_clk,
+ RST_I => sys_rst,
+ CYC_I => CYC_I_rom,
+ STB_I => STB_O,
+ WE_I => WE_O,
+ ACK_O => ACK_O_rom,
+ MRDY_I => MRDY_O,
+ SRDY_O => SRDY_O_rom,
+ ADDR_I => ADDR_O,
+ DAT_O => DAT_O_rom
+ );
+
+inst_gpio : entity work.gpio_wb
+ GENERIC MAP
+ (
+ f_sysclk => F_SYSCLK
+ )
+ PORT MAP
+ (
+ CLK_I => sys_clk,
+ RST_I => sys_rst,
+ CYC_I => CYC_I_gpio,
+ STB_I => STB_O,
+ SEL_I => SEL_O,
+ WE_I => WE_O,
+ ACK_O => ACK_O_gpio,
+ SRDY_O => SRDY_O_gpio,
+ MRDY_I => MRDY_O,
+ ADDR_I => ADDR_O,
+ DAT_I => DAT_O,
+ DAT_O => DAT_O_gpio,
+ INT_TIM_O => int_timer,
+ sys_gpi_0 => gpi0,
+ sys_gpo_0 => gpo0
+ );
+
+inst_uart : entity work.uart_wb
+ PORT MAP
+ (
+ CLK_I => sys_clk,
+ RST_I => sys_rst,
+ CYC_I => CYC_I_uart,
+ STB_I => STB_O,
+ SEL_I => SEL_O,
+ WE_I => WE_O,
+ ACK_O => ACK_O_uart,
+ SRDY_O => SRDY_O_uart,
+ MRDY_I => MRDY_O,
+ ADDR_I => ADDR_O,
+ DAT_I => DAT_O,
+ DAT_O => DAT_O_uart,
+ INT_O => int_uart,
+ ser_rx => '1',
+ ser_tx => open
+ );
+
+inst_spi_flash : entity work.spi_flash_wb
+ GENERIC MAP
+ (
+ FLASH_ADDR_BITS => 24,
+ CACHE_ADDR_BITS => 8
+ )
+ PORT MAP
+ (
+ CLK_I => sys_clk,
+ RST_I => sys_rst,
+ CYC_I => CYC_I_flash,
+ STB_I => STB_O,
+ SEL_I => SEL_O,
+ WE_I => WE_O,
+ ACK_O => ACK_O_flash,
+ SRDY_O => SRDY_O_flash,
+ MRDY_I => MRDY_O,
+ ADDR_I => ADDR_O,
+ DAT_I => DAT_O,
+ DAT_O => DAT_O_flash,
+ INT_O => int_flash,
+ spi_hold => '0',
+ spi_ss => spi_ss,
+ spi_clk => spi_clk,
+ spi_miso => spi_miso,
+ spi_mosi => spi_mosi
+ );
+
+-- DDR SDRAM Controller Core
+inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32
+ GENERIC MAP
+ (
+ F_SYSCLK => 50.000,
+ F_SDRCLK_IN => 50.000,
+ F_SDRCLK => 100.000,
+ FIFO_DEPTH => 4,
+ TPD_BOARD_SIM => 3100 ps
+ )
+ PORT MAP
+ (
+ RST_I => sys_rst,
+ CLK_I => sys_clk,
+ SDRAM_CLK_I => sys_clk,
+ SDRAM_CLK_FB_I => sys_clk,
+
+ CYC_I => CYC_I_ram,
+ STB_I => STB_O,
+ SEL_I => SEL_O,
+ WE_I => WE_O,
+ ACK_O => ACK_O_ram,
+ SRDY_O => SRDY_O_ram,
+ MRDY_I => MRDY_O,
+ ADDR_I => ADDR_O,
+ DAT_I => DAT_O,
+ DAT_O => DAT_O_ram,
+
+ -- SDRAM signals
+ sd_clk => sys_sdram_clk,
+ sd_cke => sys_sdram_cke,
+ sd_cs_n => sys_sdram_cs_n,
+ sd_cas_n => sys_sdram_cas_n,
+ sd_ras_n => sys_sdram_ras_n,
+ sd_we_n => sys_sdram_we_n,
+ sd_addr => sys_sdram_addr,
+ sd_ba => sys_sdram_ba,
+ sd_dqm => sys_sdram_dqm,
+ sd_data => sys_sdram_data
+
+ );
+
+END;
diff --git a/projects/mips_de0_nano/quartus/mips/tb_mips_sys.vhd b/projects/mips_de0_nano/quartus/mips/tb_mips_sys.vhd
new file mode 100644
index 0000000..160529d
--- /dev/null
+++ b/projects/mips_de0_nano/quartus/mips/tb_mips_sys.vhd
@@ -0,0 +1,175 @@
+-------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: Testbench for JCPU
+-- also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see .
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.sdram_types.all;
+use work.sdram_config.all;
+
+ENTITY tb_mips_sys IS
+END tb_mips_sys;
+
+ARCHITECTURE behavior OF tb_mips_sys IS
+
+ constant CLK_PERIOD : time := 20 ns;
+
+ signal debug : unsigned(1 downto 0);
+
+ -- Master
+ signal nmi_n : STD_LOGIC := '1';
+ signal rst_n : STD_LOGIC := '0';
+ signal clk : STD_LOGIC := '0';
+
+ -- SDRAM signals
+ signal sdram_clk : STD_LOGIC;
+ signal sdram_cke : STD_LOGIC;
+ signal sdram_cs_n : STD_LOGIC;
+ signal sdram_cas_n : STD_LOGIC;
+ signal sdram_ras_n : STD_LOGIC;
+ signal sdram_we_n : STD_LOGIC;
+ signal sdram_addr : sdr_addr_t;
+ signal sdram_ba : sdr_ba_t;
+ signal sdram_dqm : unsigned(PART_DM_WIDTH-1 downto 0);
+ signal sdram_data : unsigned(PART_DATA_WIDTH-1 downto 0);
+
+ signal spi_ss_n : std_logic;
+ signal spi_clk : std_logic;
+ signal spi_miso : std_logic := '1';
+ signal spi_mosi : std_logic;
+
+ signal leds : unsigned(7 downto 0);
+
+BEGIN
+
+------------------------------------------------------------------
+CLK_GEN: process
+ begin
+ wait for CLK_PERIOD/2;
+ clk <= not clk;
+ end process;
+
+------------------------------------------------------------------
+uut : entity work.mips_sys
+ PORT MAP
+ (
+ sys_nmi_n => nmi_n,
+ sys_rst_n => rst_n,
+ sys_clk => clk,
+
+ sys_sdram_clk => sdram_clk,
+ sys_sdram_cke => sdram_cke,
+ sys_sdram_cs_n => sdram_cs_n,
+ sys_sdram_cas_n => sdram_cas_n,
+ sys_sdram_ras_n => sdram_ras_n,
+ sys_sdram_we_n => sdram_we_n,
+ sys_sdram_addr => sdram_addr,
+ sys_sdram_ba => sdram_ba,
+ sys_sdram_dqm => sdram_dqm,
+ sys_sdram_data => sdram_data,
+
+ spi_ss_n => spi_ss_n,
+ spi_clk => spi_clk,
+ spi_miso => spi_miso,
+ spi_mosi => spi_mosi,
+
+ sys_leds => leds
+ );
+
+------------------------------------------------------------------
+ -- MICRON DDR SDRAM Simulation Model
+ -- 4M x16x4 Banks
+ -- IS42S16160B-7
+i_mt48lc16m16_0 : entity work.mt48lc16m16a2
+ generic map
+ (
+ tAC => 6.5 ns,
+ tHZ => 5.4 ns,
+ tOH => 2.7 ns,
+ tMRD => 2, -- 2 Clk Cycles
+ tRAS => 45.0 ns,
+ tRC => 67.5 ns,
+ tRCD => 20.0 ns,
+ tRP => 20.0 ns,
+ tRRD => 14.0 ns,
+ tAH => 0.8 ns,
+ tAS => 1.5 ns,
+ tCH => 0.8 ns,
+ tCL => 2.5 ns,
+ tCK => 10.0 ns,
+ tDH => 0.8 ns,
+ tDS => 1.5 ns,
+ tCKH => 0.8 ns,
+ tCKS => 1.5 ns,
+ tCMH => 0.8 ns,
+ tCMS => 1.5 ns
+ )
+ port map
+ (
+ unsigned(Dq) => std_logic_vector(sdram_data),
+ Addr => std_logic_vector(sdram_addr),
+ Ba => std_logic_vector(sdram_ba),
+ Clk => sdram_clk,
+ Cke => sdram_cke,
+ Cs_n => sdram_cs_n,
+ Ras_n => sdram_ras_n,
+ Cas_n => sdram_cas_n,
+ We_n => sdram_we_n,
+ Dqm => std_logic_vector(sdram_dqm)
+ );
+
+inst_spi_flash: entity work.S25fl064k
+ GENERIC MAP
+ (
+ UserPreload => TRUE,
+ mem_file_name => "dhry.elf.mem",
+ screg_file_name => "none"
+
+ )
+ PORT MAP (
+ SCK => spi_clk, -- serial clock input
+ SI => spi_mosi, -- serial data input
+ CSNeg => spi_ss_n, -- chip select input
+ SO => spi_miso -- SO
+ );
+
+------------------------------------------------------------------
+STIMULUS: process
+
+ begin
+
+
+ wait for 3*CLK_PERIOD;
+ wait until rising_edge(clk);
+ rst_n <= '1';
+ wait until rising_edge(clk);
+
+ wait;
+
+ end process;
+
+END;
diff --git a/projects/mips_de0_nano/quartus/mips/vjuart.tcl b/projects/mips_de0_nano/quartus/mips/vjuart.tcl
new file mode 100644
index 0000000..d5423c9
--- /dev/null
+++ b/projects/mips_de0_nano/quartus/mips/vjuart.tcl
@@ -0,0 +1,256 @@
+#!/usr/local/altera/quartus/bin/quartus_stp -t
+
+# vjuart.tcl - Virtual JTAG UART proxy for Altera devices
+#
+# Description: Create a TCP connection to listen for a telnet connection
+# and relay the telnet stream through the Altera VJTAG connection to a
+# I/O FIFO buffer. This TCL script requires Quartus STP to be installed.
+# Provides a simple interface to the Terasic DE0-Nano
+#
+# Copyright (C) 2014 Binary Logic (nhi.phan.logic at gmail.com).
+#
+# This file is part of the Virtual JTAG UART toolkit
+#
+# Virtual UART is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see .
+#
+
+###################### Parameters ###########################
+
+set service_port 2323
+set listen_address 0.0.0.0
+
+set REG_OFF_WRITE 8
+set REG_STATUS_INDEX 0
+set REG_TXDATA_INDEX 1
+set REG_RXDATA_INDEX 2
+
+###################### Code #################################
+
+# Setup connection
+proc setup_blaster {} {
+ global usbblaster_name
+ global test_device
+
+ foreach hardware_name [get_hardware_names] {
+ if { [string match "USB-Blaster*" $hardware_name] } {
+ set usbblaster_name $hardware_name
+ }
+ }
+
+ puts "Select JTAG chain connected to $usbblaster_name.";
+
+ # List all devices on the chain, and select the first device on the chain.
+ #Devices on the JTAG chain:
+
+
+ foreach device_name [get_device_names -hardware_name $usbblaster_name] {
+ if { [string match "@1*" $device_name] } {
+ set test_device $device_name
+ }
+ }
+ puts "Selected device: $test_device.";
+}
+
+# Open device
+proc openport {} {
+ global usbblaster_name
+ global test_device
+ open_device -hardware_name $usbblaster_name -device_name $test_device
+ device_lock -timeout 10000
+}
+
+
+# Close device. Just used if communication error occurs
+proc closeport { } {
+ global usbblaster_name
+ global test_device
+
+ # Set IR back to 0, which is bypass mode
+ device_virtual_ir_shift -instance_index 0 -ir_value 3 -no_captured_ir_value
+
+ catch {device_unlock}
+ catch {close_device}
+}
+
+# Convert decimal number to the required binary code
+proc dec2bin {i {width {}}} {
+
+ set res {}
+ if {$i<0} {
+ set sign -
+ set i [expr {abs($i)}]
+ } else {
+ set sign {}
+ }
+ while {$i>0} {
+ set res [expr {$i%2}]$res
+ set i [expr {$i/2}]
+ }
+ if {$res == {}} {set res 0}
+
+ if {$width != {}} {
+ append d [string repeat 0 $width] $res
+ set res [string range $d [string length $res] end]
+ }
+ return $sign$res
+}
+
+# Convert a binary string to a decimal/ascii number
+proc bin2dec {bin} {
+ if {$bin == 0} {
+ return 0
+ } elseif {[string match -* $bin]} {
+ set sign -
+ set bin [string range $bin[set bin {}] 1 end]
+ } else {
+ set sign {}
+ }
+ return $sign[expr 0b$bin]
+}
+
+# Send data to the Altera input FIFO buffer
+proc send {chr} {
+ global REG_STATUS_INDEX
+ global REG_TXDATA_INDEX
+ global REG_OFF_WRITE
+
+ set regeff [expr $REG_TXDATA_INDEX + $REG_OFF_WRITE]
+ device_virtual_ir_shift -instance_index 0 -ir_value $regeff -no_captured_ir_value
+ device_virtual_dr_shift -dr_value [dec2bin $chr 8] -instance_index 0 -length 8 -no_captured_dr_value
+}
+
+# Read data in from the Altera output FIFO buffer
+proc recv {} {
+ set result {}
+ set rx_count 0
+ global REG_STATUS_INDEX
+ global REG_RXDATA_INDEX
+ # Check if there is anything to read
+
+ while {1} {
+ device_virtual_ir_shift -instance_index 0 -ir_value $REG_STATUS_INDEX -no_captured_ir_value
+ set REG_STATUS [device_virtual_dr_shift -dr_value 00000000 -instance_index 0 -length 8]
+ if {[expr $REG_STATUS & 1]} {
+ break
+ }
+ set rx_count [expr $rx_count + 1]
+
+ device_virtual_ir_shift -instance_index 0 -ir_value $REG_RXDATA_INDEX -no_captured_ir_value
+ set REG_DATA [device_virtual_dr_shift -dr_value 00000000 -instance_index 0 -length 8]
+ set dec [bin2dec $REG_DATA]
+ append result [format %c $dec];
+ if {[expr $dec == 10]} {
+ break
+ }
+ if {[expr $rx_count == 80]} {
+ break
+ }
+
+ }
+ return $result
+}
+
+########## Process a connection on the port ###########################
+proc conn {channel_name client_address client_port} {
+ global service_port
+ global listen_address
+ global wait_connection
+
+ # Connect the USB Blaster
+ openport
+
+ # Configure the channel for binary
+ fconfigure $channel_name -translation binary -buffering none -blocking false
+
+ puts "Connection from $client_address"
+ # Do the "telnet mode character", command is:
+ # IAC WONT LINEMODE IAC WILL ECHO
+ puts -nonewline $channel_name "\377\375\042\377\373\001"
+ puts $channel_name "JTAG VComm, welcome $client_address on $listen_address:$service_port\r"
+ puts "Stream byte counters:"
+ flush $channel_name
+
+ # Wait for telnet client to return 'junk'
+ # Read and discard the junk
+ after 100
+ read $channel_name 4096
+
+ variable cnt_in 0
+ variable cnt_out 0
+
+ while {1} {
+ # Try to read a character from the buffer
+ set onechar [read $channel_name 1]
+ set numchars [string length $onechar]
+
+ # Check for EOF first
+ if {[eof $channel_name]} break
+
+ # Did we receive something?
+ if { $numchars > 0 } {
+ # Convert the character to ascii code
+ scan $onechar %c ascii
+
+ #Transmit this recieved character
+ send $ascii
+
+ # Update the counters
+ incr cnt_in
+ puts -nonewline "\rin: $cnt_in, out: $cnt_out"
+ flush stdout
+ }
+
+ # Now check data coming out from VComm
+ if {[eof $channel_name]} break
+ set str [recv]
+ set len [string length $str]
+
+ if {[expr $len > 0]} {
+ puts -nonewline $channel_name $str
+ incr cnt_out
+ puts -nonewline "\rin: $cnt_in, out: $cnt_out"
+ }
+ }
+ close $channel_name
+ puts "\nClosed connection"
+
+ closeport
+
+ set wait_connection 1
+}
+
+####################### Main code ###################################
+global usbblaster_name
+global test_device
+global wait_connection
+
+# Find the USB Blaster
+setup_blaster
+
+# Start the server socket
+socket -server conn -myaddr $listen_address $service_port
+
+# Loop forever
+while {1} {
+
+ # Set the exit variable to 0
+ set wait_connection 0
+
+ # Display welcome message
+ puts "JTAG VComm listening on $listen_address:$service_port"
+
+ # Wait for the connection to exit
+ vwait wait_connection
+}
+##################### End Code ########################################