[mips_de0_nano]

- initial import

git-svn-id: http://moon:8086/svn/vhdl/trunk@1340 cc03376c-175c-47c8-b038-4cd826a8556b

projects/mips_de0_nano/quartus/mips/JMips.sdc

@@ -0,0 +1,111 @@
+## Generated SDC file "JMips.out.sdc"
+
+## Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, the Altera Quartus II License Agreement,
+## the Altera MegaCore Function License Agreement, or other 
+## applicable license agreement, including, without limitation, 
+## that your use is for the sole purpose of programming logic 
+## devices manufactured by Altera and sold by Altera or its 
+## authorized distributors.  Please refer to the applicable 
+## agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 15.0.0 Build 145 04/22/2015 SJ Web Edition"
+
+## DATE    "Sat May 30 18:14:14 2015"
+
+##
+## DEVICE  "EP4CE22F17C6"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
+create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { sys_clk }]
+create_clock -name {SDRAM_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_sdram_clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+