[UART]

- added UART with FIFO

git-svn-id: http://moon:8086/svn/vhdl/trunk@1353 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/uart_rx.vhd

@@ -0,0 +1,133 @@
+-- UART Receiver with integral 16 byte FIFO buffer
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for UART_TX
+--
+entity uart_rx is
+	Generic 
+	(
+		fifo_depth_bits	: integer := 4
+	);
+    Port
+	(
+		rst				: in std_logic;
+		clk				: in std_logic;
+		re				: in std_logic;
+		full			: out std_logic;
+		half_full		: out std_logic;
+		ser_in			: in std_logic;
+		dout_vld		: out std_logic;
+		dout			: out unsigned(7 downto 0);
+		en_16_x_baud	: in std_logic
+	);
+end uart_rx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for UART_TX
+--	 
+architecture rtl of uart_rx is
+--
+------------------------------------------------------------------------------------
+--
+-- Components used in UART_TX and defined in subsequent entities.
+--	
+------------------------------------------------------------------------------------
+--
+-- Constant (K) Compact UART Transmitter
+--
+component juart_rx 
+	Port
+	(
+		rst				: in std_logic;
+		clk				: in std_logic;
+		ser_in			: in std_logic;  
+		dout			: out unsigned(7 downto 0);
+		dout_vld		: out std_logic;
+		en_16_x_baud	: in std_logic
+	);
+end component;
+--
+-- 'Bucket Brigade' FIFO 
+--
+component bbfifo 
+	Generic 
+	(
+		depth_bits	: integer := 4;
+		data_width	: integer := 8
+	);
+    Port
+	( 
+		rst			: in std_logic;
+		clk			: in std_logic;
+		we			: in std_logic;
+		din			: in unsigned(7 downto 0);
+		full		: out std_logic;
+		half_full	: out std_logic;
+		re			: in std_logic;
+		dout		: out unsigned(7 downto 0);
+		dout_vld	: out std_logic
+	);
+end component;
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in UART_TX
+--
+------------------------------------------------------------------------------------
+--
+signal uart_data_out		: unsigned(7 downto 0);
+signal fifo_write			: std_logic;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of UART_TX circuit description
+--
+------------------------------------------------------------------------------------
+--	
+begin
+
+juart: juart_rx
+port map
+(
+	rst					=> rst,
+	clk					=> clk,
+	en_16_x_baud		=> en_16_x_baud,
+	dout_vld			=> fifo_write,
+	dout				=> uart_data_out,
+	ser_in				=> ser_in
+);
+
+
+buf: bbfifo 
+GENERIC MAP 
+(
+	depth_bits	=> fifo_depth_bits,
+	data_width	=> 8
+)
+port map
+(
+	clk			=> clk,
+	rst			=> rst,
+	din			=> uart_data_out,
+	dout		=> dout,
+	we			=> fifo_write,
+	re			=> re,
+	full		=> full,
+	half_full	=> half_full,
+	dout_vld	=> dout_vld
+);
+
+end rtl;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_TX.VHD
+--
+------------------------------------------------------------------------------------
+