From c5d08ec384f19565dde29189215b04547e549101 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 20 Dec 2016 20:36:04 +0000 Subject: [PATCH] [UART] - added UART with FIFO git-svn-id: http://moon:8086/svn/vhdl/trunk@1353 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/uart/sim/tb_uart.fdo | 18 +++++ lib/uart/sim/tb_uart.wdo | 37 +++++++++ lib/uart/tb_uart.vhd | 166 +++++++++++++++++++++++++++++++++++++++ lib/uart/uart_rx.vhd | 133 +++++++++++++++++++++++++++++++ lib/uart/uart_tx.vhd | 140 +++++++++++++++++++++++++++++++++ 5 files changed, 494 insertions(+) create mode 100644 lib/uart/sim/tb_uart.fdo create mode 100644 lib/uart/sim/tb_uart.wdo create mode 100644 lib/uart/tb_uart.vhd create mode 100644 lib/uart/uart_rx.vhd create mode 100644 lib/uart/uart_tx.vhd diff --git a/lib/uart/sim/tb_uart.fdo b/lib/uart/sim/tb_uart.fdo new file mode 100644 index 0000000..c534a4b --- /dev/null +++ b/lib/uart/sim/tb_uart.fdo @@ -0,0 +1,18 @@ +## NOTE: Do not edit this file. +## + +vlib work +vcom -explicit -93 "../juart_tx.vhd" +vcom -explicit -93 "../juart_rx.vhd" +vcom -explicit -93 "../../misc/bbfifo.vhd" +vcom -explicit -93 "../uart_tx.vhd" +vcom -explicit -93 "../uart_rx.vhd" +vcom -explicit -93 "../tb_uart.vhd" + +#restart -force +vsim -t 1ps -lib work tb_uart +do {tb_uart.wdo} +view wave +view structure +view signals +run 880.0us diff --git a/lib/uart/sim/tb_uart.wdo b/lib/uart/sim/tb_uart.wdo new file mode 100644 index 0000000..c8a5858 --- /dev/null +++ b/lib/uart/sim/tb_uart.wdo @@ -0,0 +1,37 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_uart/rst +add wave -noupdate -format Logic /tb_uart/clk +add wave -noupdate -format Logic /tb_uart/en_16_x_baud +add wave -noupdate -format Logic /tb_uart/tx_we +add wave -noupdate -format Logic /tb_uart/ser_out +add wave -noupdate -format Logic /tb_uart/tx_full +add wave -noupdate -format Logic /tb_uart/tx_half_full +add wave -noupdate -format Logic /tb_uart/rx_full +add wave -noupdate -format Logic /tb_uart/rx_half_full +add wave -noupdate -format Literal -radix hexadecimal /tb_uart/tx_din +add wave -noupdate -format Logic /tb_uart/ser_in +add wave -noupdate -format Logic /tb_uart/rx_dout_vld +add wave -noupdate -format Logic /tb_uart/rx_re +add wave -noupdate -format Literal -radix hexadecimal /tb_uart/rx_dout +add wave -noupdate -format Literal -radix hexadecimal /tb_uart/baud_count +add wave -noupdate -format Literal -radix hexadecimal /tb_uart/baud_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_uart/data_rx +add wave -noupdate -format Literal -radix hexadecimal /tb_uart/data_tx +add wave -noupdate -format Literal /tb_uart/count_rx +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {878977587 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {924 us} diff --git a/lib/uart/tb_uart.vhd b/lib/uart/tb_uart.vhd new file mode 100644 index 0000000..9314ce8 --- /dev/null +++ b/lib/uart/tb_uart.vhd @@ -0,0 +1,166 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: cpu_embedded using cpu_core and rom +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +-------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity tb_uart is +end; + +architecture behave of tb_uart is + + -- Number of user data words for simulation + constant CLK_PERIOD : time := 10 ns; + constant BAUD_DIV : natural := 2; + + -- Common + signal rst : std_logic := '1'; + signal clk : std_logic := '1'; + signal en_16_x_baud : std_logic := '1'; + + -- TX + signal tx_we : std_logic := '0'; + signal ser_out : std_logic; + signal tx_full : std_logic; + signal tx_half_full : std_logic; + signal tx_din : unsigned(7 downto 0) := (others => '0'); + + -- RX + signal ser_in : std_logic := '1'; + signal rx_dout_vld : std_logic; + signal rx_full : std_logic; + signal rx_half_full : std_logic; + signal rx_dout : unsigned(7 downto 0); + signal rx_re : std_logic := '0'; + + -- Others + signal baud_count : unsigned(15 downto 0); + signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length); + signal data_rx : unsigned(7 downto 0); + signal data_tx : unsigned(7 downto 0); + signal count_rx : natural; + +begin + + ser_in <= ser_out; + +inst_uart_tx : entity work.uart_tx + PORT MAP + ( + rst => rst, + clk => clk, + we => tx_we, + din => tx_din, + en_16_x_baud => en_16_x_baud, + full => tx_full, + half_full => tx_half_full, + ser_out => ser_out + ); + +inst_uart_rx : entity work.uart_rx + PORT MAP + ( + rst => rst, + clk => clk, + en_16_x_baud => en_16_x_baud, + dout_vld => rx_dout_vld, + dout => rx_dout, + re => rx_re, + full => rx_full, + half_full => rx_half_full, + ser_in => ser_in + ); + +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + clk <= not clk; + end process; + +PROC_DATAREG_RX: + process (clk) + begin + if rising_edge(clk) then + if rst = '1' then + count_rx <= 0; + elsif rx_dout_vld = '1' and rx_re = '1' then +-- assert rx_dout = count_rx report "Data mismatch" severity failure; + data_rx <= rx_dout; + count_rx <= count_rx + 1; + end if; + end if; + end process; + +PROC_RX_RE: process + begin + wait for 10 us; + rx_re <= rx_dout_vld; + end process; + +PROC_DATAREG_TX: process + begin + wait until rising_edge(clk) and tx_we = '1'; + data_tx <= tx_din; + end process; + +baud_timer: +process(clk) +begin + if rising_edge(clk) then + en_16_x_baud <= '0'; + if rst = '1' then + baud_count <= (others => '0'); + elsif baud_count = baud_reg then + baud_count <= (others => '0'); + en_16_x_baud <= '1'; + else + baud_count <= baud_count + 1; + end if; + end if; +end process; + +------------------------------------------------------------------------------------------ + +STIMULUS: process + + + begin + + wait for 3*CLK_PERIOD; + rst <= '0'; + wait for 3*CLK_PERIOD; + wait until rising_edge(clk); + + for i in 0 to 255 loop + wait until rising_edge(clk); + tx_din <= to_unsigned(i, 8); + tx_we <= '1'; + wait until rising_edge(clk) and tx_full = '0'; + tx_we <= '0'; + end loop; + wait; + + end process; + +end architecture behave; diff --git a/lib/uart/uart_rx.vhd b/lib/uart/uart_rx.vhd new file mode 100644 index 0000000..d7edfe3 --- /dev/null +++ b/lib/uart/uart_rx.vhd @@ -0,0 +1,133 @@ +-- UART Receiver with integral 16 byte FIFO buffer +-- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; +-- +------------------------------------------------------------------------------------ +-- +-- Main Entity for UART_TX +-- +entity uart_rx is + Generic + ( + fifo_depth_bits : integer := 4 + ); + Port + ( + rst : in std_logic; + clk : in std_logic; + re : in std_logic; + full : out std_logic; + half_full : out std_logic; + ser_in : in std_logic; + dout_vld : out std_logic; + dout : out unsigned(7 downto 0); + en_16_x_baud : in std_logic + ); +end uart_rx; +-- +------------------------------------------------------------------------------------ +-- +-- Start of Main Architecture for UART_TX +-- +architecture rtl of uart_rx is +-- +------------------------------------------------------------------------------------ +-- +-- Components used in UART_TX and defined in subsequent entities. +-- +------------------------------------------------------------------------------------ +-- +-- Constant (K) Compact UART Transmitter +-- +component juart_rx + Port + ( + rst : in std_logic; + clk : in std_logic; + ser_in : in std_logic; + dout : out unsigned(7 downto 0); + dout_vld : out std_logic; + en_16_x_baud : in std_logic + ); +end component; +-- +-- 'Bucket Brigade' FIFO +-- +component bbfifo + Generic + ( + depth_bits : integer := 4; + data_width : integer := 8 + ); + Port + ( + rst : in std_logic; + clk : in std_logic; + we : in std_logic; + din : in unsigned(7 downto 0); + full : out std_logic; + half_full : out std_logic; + re : in std_logic; + dout : out unsigned(7 downto 0); + dout_vld : out std_logic + ); +end component; +-- +------------------------------------------------------------------------------------ +-- +-- Signals used in UART_TX +-- +------------------------------------------------------------------------------------ +-- +signal uart_data_out : unsigned(7 downto 0); +signal fifo_write : std_logic; +-- +------------------------------------------------------------------------------------ +-- +-- Start of UART_TX circuit description +-- +------------------------------------------------------------------------------------ +-- +begin + +juart: juart_rx +port map +( + rst => rst, + clk => clk, + en_16_x_baud => en_16_x_baud, + dout_vld => fifo_write, + dout => uart_data_out, + ser_in => ser_in +); + + +buf: bbfifo +GENERIC MAP +( + depth_bits => fifo_depth_bits, + data_width => 8 +) +port map +( + clk => clk, + rst => rst, + din => uart_data_out, + dout => dout, + we => fifo_write, + re => re, + full => full, + half_full => half_full, + dout_vld => dout_vld +); + +end rtl; + +------------------------------------------------------------------------------------ +-- +-- END OF FILE UART_TX.VHD +-- +------------------------------------------------------------------------------------ + diff --git a/lib/uart/uart_tx.vhd b/lib/uart/uart_tx.vhd new file mode 100644 index 0000000..f3de00b --- /dev/null +++ b/lib/uart/uart_tx.vhd @@ -0,0 +1,140 @@ +-- UART Transmitter with integral 16 byte FIFO buffer +-- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; +-- +------------------------------------------------------------------------------------ +-- +-- Main Entity for UART_TX +-- +entity uart_tx is + Generic + ( + fifo_depth_bits : integer := 4 + ); + Port + ( + rst : in std_logic; + clk : in std_logic; + we : in std_logic; + din : in unsigned(7 downto 0); + full : out std_logic; + half_full : out std_logic; + ser_out : out std_logic; + tx_complete : out std_logic; + tx_empty : out std_logic; + en_16_x_baud : in std_logic + ); +end uart_tx; +-- +------------------------------------------------------------------------------------ +-- +-- Start of Main Architecture for UART_TX +-- +architecture rtl of uart_tx is +-- +------------------------------------------------------------------------------------ +-- +-- Components used in UART_TX and defined in subsequent entities. +-- +------------------------------------------------------------------------------------ +-- +-- Constant (K) Compact UART Transmitter +-- +component juart_tx + Port + ( + rst : in std_logic; + clk : in std_logic; + din : in unsigned(7 downto 0); + we : in std_logic; + en_16_x_baud : in std_logic; + ser_out : out std_logic; + Tx_complete : out std_logic + ); +end component; +-- +-- 'Bucket Brigade' FIFO +-- +component bbfifo + Generic + ( + depth_bits : integer := 4; + data_width : integer := 8 + ); + Port + ( + rst : in std_logic; + clk : in std_logic; + we : in std_logic; + din : in unsigned(7 downto 0); + full : out std_logic; + half_full : out std_logic; + re : in std_logic; + dout : out unsigned(7 downto 0); + dout_vld : out std_logic + ); +end component; +-- +------------------------------------------------------------------------------------ +-- +-- Signals used in UART_TX +-- +------------------------------------------------------------------------------------ +-- +signal fifo_data_out : unsigned(7 downto 0); +signal fifo_data_present : std_logic; +signal fifo_read : std_logic; +-- +------------------------------------------------------------------------------------ +-- +-- Start of UART_TX circuit description +-- +------------------------------------------------------------------------------------ +-- +begin + + tx_complete <= fifo_read; + tx_empty <= not fifo_data_present; + +juart: juart_tx +port map +( + rst => rst, + clk => clk, + din => fifo_data_out, + we => fifo_data_present, + en_16_x_baud => en_16_x_baud, + ser_out => ser_out, + Tx_complete => fifo_read +); + + +buf: bbfifo +GENERIC MAP +( + depth_bits => fifo_depth_bits, + data_width => 8 +) +port map +( + clk => clk, + rst => rst, + din => din, + dout => fifo_data_out, + we => we, + re => fifo_read, + full => full, + half_full => half_full, + dout_vld => fifo_data_present +); + +end rtl; + +------------------------------------------------------------------------------------ +-- +-- END OF FILE UART_TX.VHD +-- +------------------------------------------------------------------------------------ +