jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- modified uart_status in simulation mode. Good for debugging.

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@992 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-07-28 19:53:15 +00:00
parent 2f047f8efb
commit c40a774db8
1 changed files with 6 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/uart/uart_wb.vhd
+6 -1
View File
@@ -81,6 +81,8 @@ ARCHITECTURE behavior OF uart_wb IS
signal irq_tx : std_logic;
signal tx_complete : std_logic;
signal tx_empty : std_logic;
signal status_real : unsigned(15 downto 0);
signal status_sim : unsigned(15 downto 0);
begin
@@ -208,7 +210,10 @@ inst_uart_rx: uart_rx
clk => CLK_I
);
uart_status_port <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
status_sim <= "0000000000000000";
status_real <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
uart_status_port <= status_sim when simulate_tx else status_real;
INT_O <= irq_rx or irq_tx;
end behavior;