diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd
index 6cb13d5..2b724e1 100644
--- a/lib/uart/uart_wb.vhd
+++ b/lib/uart/uart_wb.vhd
@@ -81,6 +81,8 @@ ARCHITECTURE behavior OF uart_wb IS
 	signal irq_tx			: std_logic;
 	signal tx_complete		: std_logic;
 	signal tx_empty			: std_logic;
+	signal status_real		: unsigned(15 downto 0);
+	signal status_sim		: unsigned(15 downto 0);
 	
 begin
 
@@ -208,7 +210,10 @@ inst_uart_rx: uart_rx
 		clk					=> CLK_I
 	);  
 	
-	uart_status_port	<= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full;
+	status_sim	 		<= "0000000000000000";
+	status_real	 		<= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
+	uart_status_port	<= status_sim when simulate_tx else status_real;
+	
 	INT_O				<= irq_rx or irq_tx;
 
 end behavior;