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- added register after scaler

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git-svn-id: http://moon:8086/svn/vhdl/trunk@174 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-12-30 06:24:39 +00:00
parent 4cd2e0fd19
commit c11d040f68
1 changed files with 14 additions and 20 deletions
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lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
+14 -20
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@@ -115,10 +115,6 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
signal resample_cnt : natural range 1 to ratio_max; signal resample_cnt : natural range 1 to ratio_max;
signal resample_vld : std_logic; signal resample_vld : std_logic;
signal x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
signal xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
signal xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
BEGIN BEGIN
assert false report "min_gain_bits = " & natural'image(min_gain_bits) & "." severity note; assert false report "min_gain_bits = " & natural'image(min_gain_bits) & "." severity note;
@@ -128,22 +124,20 @@ BEGIN
vld_i <= vld_i_pipe(nstages); vld_i <= vld_i_pipe(nstages);
input_scale:
x <= resize(din, x); process(clk)
xs <= x sra min_gain_bits; variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
xsi <= xs sra shift_in; variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
word_i_pipe(0) <= xsi; variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
vld_i_pipe(0) <= vld_in; begin
if rising_edge(clk) then
-- input_scale: x := resize(din, x);
-- process(clk) xs := x sra min_gain_bits;
-- variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); xsi := xs sra shift_in;
-- variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); word_i_pipe(0) <= xsi;
-- variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); vld_i_pipe(0) <= vld_in;
-- begin end if;
-- if rising_edge(clk) then end process;
-- end if;
-- end process;
gen_i_stages: gen_i_stages:
for i in 1 to nstages generate for i in 1 to nstages generate