From c11d040f683031f037b70d7804351f45cf9b7b8c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 30 Dec 2008 06:24:39 +0000 Subject: [PATCH] - added register after scaler git-svn-id: http://moon:8086/svn/vhdl/trunk@174 cc03376c-175c-47c8-b038-4cd826a8556b --- .../decimator/CIC/src/cic_decim_pipe.vhd | 34 ++++++++----------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd index c641cf2..c07ef73 100644 --- a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd +++ b/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd @@ -115,10 +115,6 @@ ARCHITECTURE behavior OF cic_decim_pipe IS signal resample_cnt : natural range 1 to ratio_max; signal resample_vld : std_logic; - signal x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); - signal xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); - signal xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); - BEGIN assert false report "min_gain_bits = " & natural'image(min_gain_bits) & "." severity note; @@ -128,22 +124,20 @@ BEGIN vld_i <= vld_i_pipe(nstages); - - x <= resize(din, x); - xs <= x sra min_gain_bits; - xsi <= xs sra shift_in; - word_i_pipe(0) <= xsi; - vld_i_pipe(0) <= vld_in; - --- input_scale: --- process(clk) --- variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); --- variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); --- variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); --- begin --- if rising_edge(clk) then --- end if; --- end process; +input_scale: + process(clk) + variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); + variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); + variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); + begin + if rising_edge(clk) then + x := resize(din, x); + xs := x sra min_gain_bits; + xsi := xs sra shift_in; + word_i_pipe(0) <= xsi; + vld_i_pipe(0) <= vld_in; + end if; + end process; gen_i_stages: for i in 1 to nstages generate